JP4999361B2 - Processing equipment - Google Patents

Description

The present invention relates to a processing device capable of realizing a plurality of functions such as four arithmetic operations and logical operations.

  In recent years, attention has been paid to a reconfigurable circuit configured not to use hardware in a fixed manner but to be able to change the operation to some extent according to given data. Such reconfigurable circuits often have a configuration in which many ALUs (Arithmetic and Logic Units) are operated in parallel. Each ALU performs arithmetic processing according to a given command.

  In this type of circuit, it is necessary to simultaneously supply commands to all ALUs at each timing at which arithmetic processing is to be performed. For example, when 4 × 6 = 24 ALUs are used, even if a command given to one ALU is expressed by a 4-bit digital signal, a total of 96-bit command data is required for each command supply. Become.

  This command data is normally stored in a command RAM (Random Access Memory) built in the reconfigurable circuit, and the increase in the command data causes an increase in the circuit scale of the reconfigurable circuit. For this reason, in this type of circuit, how to reduce the amount of command data is an important issue.

  A technique for reducing the amount of command data is disclosed in Patent Document 1 below. In Patent Document 1 below, the fact that the ALU is not constantly operating, and that the invalid command (NOP) is supplied to the ALU when not operating is utilized. Specifically, except for invalid commands, data describing only valid commands is formed, and data such as an index indicating validity / invalidity of each command is formed.

JP 7-175648 A

  The technique described in Patent Document 1 contributes to a reduction in the required memory area of the command RAM, and can function effectively in a certain aspect. However, the frequency of appearance of invalid commands varies greatly depending on the application, and it is necessary to prepare a command RAM suitable for the application with the largest use memory, so that a sufficient command compression effect can always be obtained. I can't say that.

  In addition, since a memory for storing the index is necessary, when the number of bits of the original command is small, the ratio of the data amount of the index to all data is increased, and the compression effect is reduced. Further, when decoding, it is necessary to decompress the data described in a packed manner, and the decompression circuit becomes large, resulting in an increase in power consumption.

Therefore, an object of the present invention is to provide a processing apparatus that contributes to a reduction in the amount of data that needs to be supplied to a variable function realizing means such as an ALU.

Processing apparatus according to the present invention includes a first ALU, among the input signals from a plurality of ALU, a selection unit and outputs the selected signal in accordance with selection No.択信the first ALU, the instruction signal for the first ALU An instruction generation unit for generating the selection signal, and a selection signal generation unit for generating a selection signal to be supplied to the selection unit, the selection signal generation unit from the ALU from any of the plurality of ALUs When there is no input signal, a part of the instruction signal for the first ALU is generated .

  The present invention contributes to a reduction in the amount of data that needs to be supplied to a variable function realization means such as an ALU.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings. In the drawings to be referred to, the same parts are denoted by the same reference numerals. FIG. 1 is a schematic block diagram of an integrated circuit 1 according to an embodiment of the present invention.

  The integrated circuit 1 includes an ALU (Arithmetic and Logic Unit) 10, selectors SELA, SELB and SELC, ALUs 11, 12 and 13, and RAMs (Random Access Memory) 14, 15, 16 and 17.

  The integrated circuit 1 is, for example, a reconfigurable circuit having a function that enables reconfiguration of a logic circuit, and includes a plurality of ALUs that perform four arithmetic operations and logical operations. For example, several tens to several hundreds of ALUs (not shown) that perform parallel processing are incorporated in the integrated circuit 1, and commands are simultaneously supplied to the respective ALUs.

  FIG. 1 illustrates only a portion focused on one ALU 10 among the plurality of ALUs. The selectors SELA, SELB, and SELC are provided in association with the ALU 10, and a number of parts that are the same as or similar to the parts that include the ALU 10, the selectors SELA, SELB, and SELC are provided in the integrated circuit 1.

  FIG. 2 is a configuration block diagram of peripheral circuits of the ALU 10. The integrated circuit 1 in FIG. 1 further includes selection signal generation units 21, 22, and 23, a main command signal generation unit 24, and a decoder 25 shown in FIG. The selection signal generation units 22 and 23 and the main command signal generation unit 24 form an ALU control unit (control means) 26.

  The selector SELA receives as input signals a total of five signals, that is, output signals from the ALUs 11, 12 and 13, and output signals from the RAM 14 and RAM 15, respectively. Then, based on the selection signal INA generated by the selection signal generation unit 21 in FIG. 2, one input signal is selected from the five input signals, and the selected signal is output to the ALU 10. The selector SELA is configured to be able to select any of the five input signals to itself, and thus the selection signal INA is formed from a 3-bit digital signal.

  The selector SELB receives, as input signals, a total of five signals: output signals from the ALUs 11, 12 and 13 and output signals from the RAM 16 and RAM 17, respectively. Then, based on the selection signal INB generated by the selection signal generation unit 22 in FIG. 2, one input signal is selected from the five input signals, and the selected signal is output to the ALU 10. The selector SELB is configured to be able to select any of the five input signals to itself. Therefore, the selection signal INB is formed from a 3-bit digital signal.

  The selector SELC receives a total of three output signals from the ALUs 11, 12, and 13 as input signals. Then, based on the selection signal INC generated by the selection signal generation unit 23 in FIG. 2, one input signal is selected from the three input signals, and the selected signal is output to the ALU 10. The selector SELC is configured to be able to select any of the three input signals to itself. Therefore, the selection signal INC is formed from a 2-bit digital signal.

  The ALU 10 receives the output signals of the selectors SELA, SELB, and SELC as input signals to itself. Signals given from the selectors SELA, SELB, and SELC to the ALU 10 are referred to as signal A, signal B, and signal C, respectively. Each input signal to the selectors SELA, SELB, and SELC is a digital signal, and the signals A, B, and C are also digital signals. Accordingly, the signals A, B, and C each have a discrete value.

  The ALU 10 is configured to be able to realize a plurality of functions, and functions as a variable function realization means. The ALU 10 executes necessary processes one after another in synchronization with a clock signal or the like, but the type (content) of the process actually executed at each timing of executing the process is a function control signal given from the decoder 25. It is determined.

  The main command signal generator 24 outputs a main command signal α (command signal) for designating a function realized by the ALU 10. The main command signal α is formed from a 2-bit digital signal.

  The decoder 25 generates the function control signal based on the main command signal α and the selection signals INB and INC, and supplies the function control signal to the ALU 10.

  Since the selection signals INA, INB, and INC are for specifying an input signal to the ALU 10, the selection signals INA, INB, and INC can also be interpreted as command signals for the ALU 10.

  With reference to FIG. 3, the types (contents) of processing that can be executed by the ALU 10 are illustrated. The function control signal from the decoder 25 functions as a command for instructing the ALU 10 to perform a desired process, and there are eleven types of function control signals (that is, command types).

  In order to selectively select a desired function from these 11 types of functions, a signal of 4 bits is usually required. However, in the present embodiment, the main command signal α is expressed by 2 bits. The explanation of the technique for realizing this will be continued.

  The eleven types of commands are composed of commands COM0, COM1, COM2, COM3, COM4, COM5, COM6, COM7, COM8, COM9, and COM10. In FIG. 3, the digital output signal of the ALU 10 is represented by Y.

  The process corresponding to the commands COM0 to COM2 is a one-input process that depends only on one input signal. The commands COM0 and COM1 are so-called through commands. When receiving the function control signal corresponding to the command COM0, the ALU 10 outputs the signal A as it is. When receiving the function control signal corresponding to the command COM1, the ALU 10 outputs the signal B as it is. The command COM2 is a command corresponding to negation. When receiving the function control signal corresponding to the command COM2, the ALU 10 outputs a negation of the signal A (a value obtained by inverting the signal A).

  The process corresponding to the commands COM3 to COM8 is a two-input process that depends only on two input signals. When receiving the function control signal corresponding to the commands COM3 to COM8, the ALU 10 outputs the calculation result of the calculation using the signals A and B.

  Specifically, when receiving the function control signals corresponding to the commands COM3 and COM4, the ALU 10 outputs the sum of the signals A and B (A + B) and the difference between the signals A and B (A−B), respectively. To do. When receiving the function control signals corresponding to the commands COM5 and COM6, the ALU 10 outputs the logical product of the signals A and B and the logical sum of the signals A and B, respectively. When receiving the function control signal corresponding to the command COM7, the ALU 10 compares the value of the signal A with the value of the signal B, and outputs “1” when the value of the signal B is larger, and otherwise. “0” is output. When receiving the function control signal corresponding to the command COM8, the ALU 10 compares the value of the signal A with the value of the signal B, and outputs “1” if the value of the signal A is larger, and otherwise. “0” is output.

  The process corresponding to the commands COM9 and COM10 is a three-input process that depends on all three input signals. Specifically, when receiving the function control signal corresponding to the command COM9, the ALU 10 refers to the value of the signal C. If the value of the signal C is “1”, the ALU 10 outputs the signal A, while the value of the signal C If B is “0”, signal B is output. When the function control signal corresponding to the command COM10 is received, the ALU 10 refers to the value of the signal C. If the value of the signal C is “1”, the ALU 10 outputs the signal B, while if the value of the signal C is “0”. Signal A is output.

  As described above, the processing of the ALU 10 includes one-input processing that depends only on one input signal, two-input processing that depends only on two input signals, and three-input processing that depends on all three input signals. By the way, when executing 1-input processing, selection signals (commands) for the remaining 2 inputs are unnecessary, and when executing 2-input processing, selection signals (commands) for the remaining 1 input are not required. is there.

  In this embodiment, paying attention to this point, an unnecessary selection signal (command) is used for selecting the above-described 11 types of functions.

  The specific method for assigning signals is shown in the right column of the table shown in FIG. FIG. 4 shows an internal block diagram of the decoder 25.

  A 2-bit digital value forming the main command signal α is expressed by α = (i, j). A 2-bit digital value forming the selection signal INC is expressed by INC = (i, j). A 3-bit digital value forming the selection signal INB is expressed by INB = (i, j, k). Here, i, j, and k each independently take a value of 1 or 0. In FIG. 3 and the like, the notation “,” is omitted.

  Since the processing corresponding to the commands COM0 and COM2 is one-input processing that depends only on the signal A, when executing these, the ALU control unit 26 sends the selection signals INC and INB to the ALU10 in addition to the main command signal α. Used as a function selection signal.

  When “α = (1, 1), INC = (1, 1) and INB = (0, X, X)” is received from the ALU control unit 26, “α = (1, 1), INC When the signal “= (1, 1) and INB = (1, X, X)” is received, the decoder 25 supplies the ALU 10 with function control signals representing the commands COM0 and COM2, respectively. Here, “X” in the notation indicating the content of the selection signal INB indicates that the digital value is arbitrary (that is, either 1 or 0 may be used).

  The process corresponding to the command COM1 is a one-input process but depends on the signal B. For this reason, when executing processing corresponding to the command COM1, the ALU control unit 26 uses the main command signal α and the selection signal INC as selection signals for the function of the ALU 10, and the selection signal INB as the selection signal. do not use.

  Further, since the processing corresponding to COM3 to 8 is a two-input processing that depends only on the signal A and the signal B, when executing these, the ALU control unit 26 outputs the selection signal INC in addition to the main command signal α. , And used as a function selection signal for the ALU 10.

Specifically, from the ALU control unit 26,
When “α = (1, 1) and INC = (1, 0) signal” is received,
When “α = (0, 1) and INC = (0, 0) signal” is received,
When “α = (0, 1) and INC = (0, 1) signal” is received,
When “α = (0, 1) and INC = (1, 0) signal” is received,
When “α = (0, 1) and INC = (1, 1) signal” is received,
When “α = (1,1) and INC = (0,0) signal” is received,
When “α = (1,1) and INC = (0,1) signal” is received,
The decoder 25 supplies function control signals representing the commands COM1, COM3, COM4, COM5, COM6, COM7, and COM8 to the ALU 10, respectively.

  Since the process corresponding to the commands COM 9 and 10 is a three-input process that depends on all three input signals, the ALU control unit 26 uses only the main command signal α as a function selection signal for the ALU 10.

  When “α = (0,0) signal” is received from the ALU control unit 26 and “α = (1,0) signal” is received, the decoder 25 represents commands COM9 and COM10, respectively. A function control signal is supplied to the ALU 10.

  Data representing a command to be specified in the ALU 10 is stored in a command RAM (not shown) built in the integrated circuit 1. However, with the configuration described above, 4 bits are usually required. The command signal (main command signal α in this embodiment) is reduced to 2 bits. As a result, the memory area necessary for storing the command is reduced, and the chip area of the integrated circuit can be reduced and the power consumption can be reduced. For example, if there are a total of 24 ALUs similar to the ALU 10 in the integrated circuit 1, a 48-bit memory area is reduced in response to a single command supply, and an enormous amount of data can be obtained by considering the entire series of processes. Memory area will be reduced.

  FIG. 5 shows a signal allocation procedure as shown in the table of FIG. First, in step S1, the main command signal α is assigned to the commands COM9 and 10 corresponding to the three-input process. Next, the main command signal α not used in step S1 and the selection signal INC are assigned to the commands COM3 to COM8 corresponding to the two-input process (step S2). Finally, a “combination of the main command signal α and the selection signal INC” not used in steps S1 and S2 is assigned to the commands COM0 to COM2 corresponding to one input process, and to the commands COM0 and COM2. Further assigns a selection signal INB (step S3).

<< Deformation, etc. >>
The functions of the integrated circuit 1 described above can be realized by hardware, software, or a combination thereof.

  In the above-described embodiment, the variable function realization apparatus includes the ALU 10 as the variable function realization means and the decoder 25 as the function selection means (function designation means). It can be considered that the decoder 25 and the ALU control unit 26 form a function selection unit (function designation unit).

It is a schematic block diagram of an integrated circuit according to an embodiment of the present invention. FIG. 2 is a configuration block diagram of a peripheral circuit of the ALU in FIG. 1. 3 is a table showing a plurality of processes that can be executed by the ALU of FIG. 2 and signals corresponding to the processes. FIG. 3 is an internal block diagram of the decoder of FIG. 2. It is a flowchart which shows the procedure of how to allocate a signal as shown in the table | surface of FIG.

Explanation of symbols

1 Integrated circuit 10 ALU
21, 22, 23 Selection signal generator 24 Main command signal generator 25 Decoder 26 ALU controller SELA, SELB, SELC selector

Claims (1)

A first ALU that inputs a plurality of input signals and performs an operation ;
A plurality of ALUs arranged in front of the first ALU and outputting data to the first ALU ;
A plurality of selection units provided for each input of the first ALU, for selecting data from the plurality of ALUs according to a selection signal and outputting the data as respective input signals of the first ALU ;
An instruction generator for generating an instruction signal for the first ALU;
A plurality of selection signal generation units provided corresponding to each of the plurality of selection units, and generating a selection signal to be supplied to each selection unit,
At least one of the plurality of selection signal generation units generates a part of the instruction signal for the first ALU when there is no input signal from any of the plurality of ALUs to the corresponding selection unit. The processing apparatus characterized by the above-mentioned.

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