JP2004302827A - Microcontroller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcontroller capable of dissolving a time lag required for frequency change under operation and reducing power consumption, by accurately and quickly performing frequency control, in response to tasks. <P>SOLUTION: The frequency control can be practical in process of pipeline processing of an execution demand so that a frequency control signal determining the frequency-dividing ratio of a system clock is added to an operation code, and fetch-decoding of the frequency control signal is performed together with the operation code. Consequently, the time lag required for frequency change is dissolved, and power consumption of the microcontroller is reduced by accurately and quickly performing frequency control, in response to the tasks. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a microcontroller that operates in synchronization with a system clock and fetches, decodes, and executes an instruction program on a memory such as a ROM by pipeline processing.
[0002]
[Prior art]
When a system using a microcontroller is reviewed from the viewpoint of low power consumption, not all tasks require the operation of the microcontroller at the highest frequency. The point is that the operating frequency should be the minimum operating frequency that does not degrade the performance of the system.
[0003]
Such a case is assumed in a general microcontroller, and the configuration is such that the frequency division ratio can be changed in the process of generating the system clock from the original oscillation.
[0004]
In a conventional microcontroller, the division ratio is often controlled by setting arbitrary data in an address-mapped register. In such a configuration, the power consumption and the operating frequency are controlled in a fine manner. Also, the occurrence of a time loss corresponding to the instruction execution cycle for writing becomes an obstacle, and the intended frequency control and power control effects may not be obtained. As a countermeasure against these problems, on the other hand, there is a method in which the frequency is changed according to the accessed memory space (for example, see Patent Document 1). However, since it is necessary to execute a jump instruction to the memory space allocated to the frequency to be changed, the problem has not been completely solved in any case.
[0005]
The conventional microcontroller as described above will be described below. FIGS. 10 and 11 are block diagrams showing a schematic configuration of a conventional microcontroller. FIG. 10 shows the configuration of a clock generator inside the microcontroller in detail, and FIG. 11 shows the configuration of a CPU inside the microcontroller in detail. Things.
[0006]
In FIG. 10, reference numeral 1000 denotes a microcontroller, and 100 denotes a CPU. The ROM 700 is connected via a bus, and the clock generator 800 receives a system clock sysclk from the clock generator 800 in addition to the connection via the bus, and the microcontroller 1000 operates in synchronization with the sysclk. The clock generator 800 receives the original oscillation oscin, and includes a clock frequency dividing circuit 801, a selector 802, a clock frequency dividing control circuit 803, and a clock frequency dividing control register 804. The clock frequency dividing circuit 801 frequency-divides oscin, and generates a plurality of frequency-divided signals in addition to the 1-frequency-divided signal. The clock frequency division control register 804 holds information for selecting one of the frequency division signals generated by the clock frequency division circuit 801 based on data set in a register readable / writable by an instruction processed by the CPU 100. The clock division control circuit 803 adjusts the clock switching timing based on the data set in the clock division control register 804, and outputs a control signal oscsel for the selector 802. The selector 802 selects one of the frequency-divided signals output from the clock frequency-dividing circuit 801 according to the oscsel, and transmits it to the CPU 100 as sysclk.
[0007]
11, the CPU 100 includes an instruction decoder 400, a data path 300, a data register 500, an address register 600, and a bus interface 200. Data exchange inside the CPU is performed via the bus interface 200, and the operation of the CPU is Controlled by microcode (MIR). Next, the general operation of the microcontroller configured as described above will be described below using an 8-bit microcontroller as an example.
[0008]
First, data input from the ROM 700 is fetched into the instruction fetch buffer (IFB) 401 in the instruction decoder 400 via the bus interface 200, passes through the instruction buffer (IB) 402, and then has an operation code and an operand. Is divided into
[0009]
The operation code output from the IB 402 is input to an instruction register (IR) 403 and then decoded by a programmable logic array (PLA) 404. The supplied constituent blocks execute processing operations according to the input MIR.
[0010]
The operand output from IB 402 is transmitted to data path 300, data register 600, address register 700, or the like according to the MIR.
[0011]
In order to change the frequency division ratio of the system clock sysclk, the switching timing is adjusted by the clock frequency division control circuit 803 by writing a set value corresponding to each frequency division ratio to the clock frequency division control register 804 to which the address is mapped. , The selection signal osscsel is output to the selector 802, and the selector 802 selects the frequency-divided signal in response to the selection signal osscsel, and transmits it to the CPU 100 as sysclk.
[0012]
The operation of the above-described conventional microcontroller will be described with reference to a program example and a timing chart.
[0013]
(A), (b), and (c) of FIG. 12 are an instruction format, a program example, and an operation timing chart of a conventional microcontroller.
[0014]
The instruction format includes a 4-bit extension code indicating the number of pages of the instruction map, an 8-bit operation code (operation code), and 4 × n-bit (n = 1, 2,...) Operands.
[0015]
In the program example, the instructions of (1) to (7) are executed. After executing the instruction (1) by dividing sysclk by 1 for oscin, the dividing ratio is reduced from 1 to 2 by the instruction (2). Switch to Zhou. After executing the commands (3) and (4), the frequency is returned to 1 again by the command (5), and the commands (6) and (7) are executed. In the symbols shown in the timing chart, (1) -1 indicates the machine code of the first nibble of the instruction (1) of the program example, and (1) μ-1 indicates the first execution cycle of the instruction (1). Shall be. T1 and T2 indicate the timing of the falling edge and the rising edge of sysclk, respectively. At the timing A, since osscsel is “L”, sysclk operates at a period of 1/1 oscin. The IFB 401 and the IB 402 fetch the instructions (1) -1 and (1) -2 from the ROM 700 at T1. Instruction (1) -1 is an extension code, and (1) -2 is the first nibble of an operation code and is not an operand, so that any data is output to the IR 403. At the timing B, the IR 403 latches (1) -1 and (2) at T2, outputs it to the PLA 404, and the PLA 404 starts decoding. (1) -1 is an extended code, and (1) -2 is not processed until the second nibble of the operation code is fetched. Therefore, at the next timing T1, at timing C1, the MIR ((1) Only μ-1) is output as an extension code recognition cycle. At the same time, the IFB 401 fetches the instructions (1) -3 and (2) -1. At the timing D, the IR 403 takes in the operation code (1) -3 of the remaining one nibble of the instruction (1) and decodes it with the PLA 404 together with the processing wait (1) -2. At timing E, the MIR (1) μ-2 of (1) -2,3 is output, and the IFB 401 fetches (2) -2,3. Also, (2) -1 not taken into the IR 403 at the timing D is shifted to the IB 402 at the timing E. When the extension code passes through the IFB 401 and the IB 402 as shown in (3) -1, it is recognized during that time. Therefore, at the timing F, it is not taken into the IR 403, and the operation code (3) -2, 3 is stored in the IR 403. It is captured.
[0016]
In the instruction (2), osscsel becomes 'H' at timing G by writing to the clock frequency division control register 804 in the execution cycle (2) μ-3, and the cycle of sysclk is changed from 1/1 oscin to 1/2 oscin. . Similarly, the cycle of sysclk is returned from 1/2 oscin to 1/1 oscin by the instruction (5).
[0017]
As described above, the conventional microcontroller can control the frequency by the write command to the clock frequency division control register 804.
[0018]
[Patent Document 1]
Japanese Patent Application Laid-Open No. H02-118811
[0019]
[Problems to be solved by the invention]
However, in the above-described conventional microcontroller, several cycles are required to execute a write instruction to a register in order to change a frequency. As a result, there is a problem that power consumption adjustment by frequency control cannot be finely performed while maintaining the performance of the system.
[0020]
SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems. It is possible to eliminate a time lag required for frequency change, and reduce power consumption by performing frequency control appropriately and quickly according to a task. To provide a microcontroller that can
[0021]
[Means for Solving the Problems]
A microcontroller according to a first aspect of the present invention responds to frequency information from a plurality of clock signals having a frequency of 1 / n (n is an integer of 1 or more in a dividing ratio) of an oscillation frequency and different frequencies. A clock signal is input as a system clock, operates in synchronization with the system clock, and fetches and decodes an operation code and an operand by pipeline processing for an instruction program including an operation code and an operand stored in a memory; A processor for executing an instruction program based on the decoding result is provided, and an operation code is stored in a memory with a frequency control signal for determining a frequency division ratio of a system clock added thereto. Fetch and decode by pipeline processing with And outputs a frequency information corresponding to the frequency control signal by Rukoto.
[0022]
According to this configuration, since the information for controlling the frequency is processed in the pipeline in the same manner as the operation code, it is not necessary to write the setting data to the frequency control register as in the related art, and the frequency is maintained without lowering the performance of the system. Control can be performed finely, and power consumption of the microcontroller can be effectively reduced.
[0023]
The microcontroller according to the second aspect of the present invention converts frequency information from a plurality of clock signals having a frequency of 1 / n (where n is an integer of 1 or more) of the oscillation frequency and different frequencies. A corresponding clock signal is input as a system clock, operates in synchronization with the system clock, and executes an expansion code, an operation code, and an operation code by pipeline processing on an instruction program including an extension code, an operation code, and an operand stored in a memory. Equipped with a processor that fetches and decodes operands and executes an instruction program based on the result of decoding, and configures the operation code as an instruction map consisting of multiple pages classified into pages corresponding to each division ratio by machine code And pipelined with the operation code The extension code indicates a page of the instruction map, and the processor fetches and decodes the extension code by pipeline processing to output frequency information corresponding to a division ratio corresponding to the instruction map page indicated by the extension code. Features.
[0024]
According to this configuration, since the existing extended code area has the frequency control information, there is no increase in the circuit size, and the execution cycle of the instruction to be changed in frequency and the frequency change timing are synchronized by being decoded before the operation code. It is possible to easily and more precisely reduce the power consumption according to the intention of the program developer.
[0025]
Further, like the microcontroller according to the third aspect, in the microcontroller according to the first or second aspect, the oscillation frequency is 1 / n (where n is an integer of 1 or more in the frequency division ratio) and is different from the A clock generator that generates a plurality of clock signals, selects a clock signal according to the frequency information output from the processor from among them, and outputs the selected clock signal to the processor as a system clock may be provided.
[0026]
In addition, the clock generator outputs a plurality of clock signals having frequencies different from 1 / n (n is an integer of 1 or more) of the oscillation frequency and different frequencies. Selecting means for selecting one clock signal based on a selection signal from a plurality of clock signals output from the frequency dividing means and outputting the selected signal as a system clock; and selecting a selection signal corresponding to frequency information output from the processor And a control means for outputting to the means.
[0027]
According to a fifth aspect of the present invention, in the microcontroller according to the first aspect, a frequency control signal is generated according to a frequency division ratio setting description for determining a frequency division ratio of a system clock described in a source program. There is provided a means for adding to an operation code generated from an instruction at a later stage of the ratio setting description and converting it into ROM code.
[0028]
Thus, the addition of the frequency control signal to the operation code can be automatically machine-coded by the compiler without the burden of the program developer.
[0029]
According to a sixth aspect of the present invention, in the microcontroller according to the first aspect, a frequency control signal is generated according to a frequency division ratio setting description for determining a frequency division ratio of a system clock described in a source program. If the number of execution cycles of the instruction preceding the ratio setting description is less than the reference, the frequency control signal is added to the operation code generated from the instruction preceding the division ratio setting description. There is provided a means for adding to an operation code generated from an instruction at a subsequent stage of the cycle ratio setting description and converting it into a ROM code.
[0030]
As a result, it is possible to reduce an error between the execution cycle of an instruction to change the frequency and the frequency change timing due to the processing time until the frequency control signal is decoded together with the operation code and executed.
[0031]
According to a seventh aspect of the present invention, there is provided the microcontroller according to the second aspect, wherein the extension code corresponding to the frequency division ratio is written in accordance with the frequency division ratio setting description for determining the frequency division ratio of the system clock described in the source program. There is provided means for selecting an operation code corresponding to the instruction at the latter stage of the division ratio setting description from the page of the instruction map indicated by the extension code and converting the operation code into ROM code.
[0032]
As a result, the setting of the frequency division ratio of the system clock and the selection of the instruction code corresponding to the frequency division ratio can be automatically machine-coded by the compiler without the burden on the program developer by the description of the specific frequency division ratio setting.
[0033]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
[0034]
(Embodiment 1)
The microcontroller according to the first embodiment of the present invention will be described. 1 and 2 are block diagrams showing a schematic configuration of a microcontroller according to the first embodiment. FIG. 1 shows a detailed configuration of a clock generator inside the microcontroller, and FIG. 2 shows a configuration of a CPU inside the microcontroller. This is shown in detail.
[0035]
In FIG. 1, reference numeral 1000 denotes a microcontroller, and 100 denotes a CPU. The CPU 100 and the ROM 700 are connected via a bus. The clock generator 800 receives the original oscillation oscin, is constituted by a clock frequency dividing circuit 801, a selector 802, and a clock frequency dividing control circuit 803. The microcode MIR output from the CPU 100 , The frequency division ratio of the system clock sysclk is determined and transmitted to the CPU 100. The microcontroller 1000 operates in synchronization with this sysclk. The clock frequency dividing circuit 801 divides the frequency of the original oscillation oscin, and generates a plurality of frequency-divided signals in addition to the 1-frequency-divided signal. The clock frequency division control circuit 803 adjusts the clock switching timing based on the MIR output from the CPU 100 and outputs a control signal oscsel for the selector 802. The selector 802 selects one of the frequency-divided signals output from the clock frequency-dividing circuit 801 according to the oscsel, and transmits it to the CPU 100 as sysclk.
[0036]
2, the CPU 100 includes an instruction decoder 400, a data path 300, a data register 500, an address register 600, and a bus interface 200. Data exchange inside the CPU is performed through the bus interface 200, and the operation of the CPU is Controlled by microcode (MIR).
[0037]
Next, the operation of the microcontroller according to the first embodiment configured as described above will be described.
[0038]
First, data input from the ROM 700 is taken into the instruction fetch buffer (IFB) 401 in the instruction decoder 400 via the bus interface 200, passes through the instruction buffer (IB) 402, and is then divided into operation codes and operands. You.
[0039]
The operation code output from the IB 402 is input to an instruction register (IR) 403 and then decoded by a programmable logic array (PLA) 404 to be used as an MIR to each block of the bus interface 200, data path 300, and instruction decoder 400. The supplied constituent blocks execute processing operations according to the input MIR.
[0040]
The operand output from the IB 402 is transmitted to the data path 300 or the data register 600 or the address register 700 according to the MIR.
[0041]
The mechanism for changing the frequency division ratio of the system clock sysclk decodes the frequency control signal added to the operation code together with the operation code, and is transmitted to the clock frequency division control circuit 803 as the MIR. The clock division control circuit 803 adjusts the switching timing based on the transmitted MIR, outputs the selection signal oscsel to the selector 802, selects the frequency division signal by the selector 802, and transmits it to the CPU 100 as sysclk.
[0042]
The operation of the microcontroller according to the first embodiment as described above will be described using a program example and a timing chart.
[0043]
3A, 3B, and 3C are an instruction format, a program example, and an operation timing chart of the microcontroller according to the first embodiment. Here, an operation of switching the frequency division ratio of sysclk from 1 frequency division of oscin to 2 frequency division and again to 1 frequency division is shown taking an 8-bit microcontroller as an example.
[0044]
The instruction format includes a 4-bit extension code indicating the number of pages of the instruction map, an 8-bit operation code (operation code), a 1-bit frequency control signal added to the operation code, and 4 × n bits (n = 1, 2). ...)).
[0045]
In the example of the program, the instructions of (1) to (7) are executed, and the dividing ratio of sysclk is switched from 1 to 2 of oscin from the instruction (3). Switch to The frequency control signal added to the operation code is represented by * 0 or * 1, and when * 0, frequency division by 1 is selected, and when * 1, frequency division by 2 is selected. In the symbols shown in the timing chart, (1) -1 indicates the machine code of the first nibble of the instruction (1) of the program example, and (1) μ-1 indicates the first cycle of the execution cycle of the instruction (1). Shall be represented. T1 and T2 indicate the timing of the falling edge and the rising edge of sysclk, respectively.
[0046]
At the timing A, since osscsel is “L”, sysclk operates at a period of 1/1 oscin. The IFB 401 and the IB 402 fetch the instructions (1) -1 and (1) -2 from the ROM 700 at T1. Instruction (1) -1 is an extension code, and (1) -2 is the first nibble of an operation code and is not an operand, so that any data is output to the IR 403. At the timing B, the IR 403 latches (1) -1 and (2) at T2, outputs it to the PLA 404, and the PLA 404 starts decoding. (1) -1 is an extended code, and (1) -2 is not processed until the second nibble of the operation code is fetched. Therefore, at the next timing T1, at timing C1, the MIR ((1) Only μ-1) is output as an extension code recognition cycle. At the same time, the IFB 401 fetches the instructions (1) -3 and (3) -1. At the timing D, the IR 403 captures the remaining one nibble of the operation code (1) -3 of the instruction (1) and decodes it by the PLA 404 together with the processing wait (1) -2. At timing E, the MIRs (1) -2 of (1) -2, 3 are output, and the IFB 401 fetches (3) -2,3. Further, (3) -1 not taken into the IR 403 at the timing D is shifted to the IB 402 at the timing E. When the extension code passes through the IFB 401 and the IB 402 as shown in (3) -1, it is recognized during that time, and is not taken into the IR 403 at the timing F. It is captured.
[0047]
Since (3) -3 holds information (* 1) of the frequency-divided-by-2 control in the added frequency control signal, it is output to the clock generator 800 as an MIR during the (3) μ-1 cycle. The clock frequency division control circuit 803 adjusts the switching timing, sets osscsel to “H” at timing G, and switches sysclk to 1 / 2oscin. Similarly, the frequency is returned to 1/1 oscin by the frequency control signal added to the instruction (6).
[0048]
The frequency control signal to be added is not limited to one bit but may be several bits depending on the specifications of the microcontroller.
[0049]
As described above, according to the first embodiment, the operation code is processed in the pipeline similarly to the operation code by adding the frequency control signal for determining the frequency division ratio of the system clock. As described above, the time for writing the setting data to the frequency control register (804) is not required, and the power consumption of the microcontroller can be effectively reduced without lowering the performance of the system. Further, in this embodiment, an 8-bit microcontroller is described as an example. However, as the number of bits increases, the effect of the added bits on the circuit scale becomes extremely small, and the effect of the present invention further increases. .
[0050]
(Embodiment 2)
A microcontroller according to a second embodiment of the present invention will be described.
[0051]
FIG. 4 is a block diagram illustrating a schematic configuration of the microcontroller according to the second embodiment. The only difference from the first embodiment is that the operation code transmitted from IFB 401, IB 402, IR 403, and PLA 404 is constituted by 8 bits because no frequency control signal is added to the operation code. It is. Therefore, the internal configuration of clock generator 800 is the same as that of FIG.
[0052]
Next, the operation of the microcontroller according to the second embodiment configured as described above will be described.
[0053]
FIGS. 5A and 5B are examples of an instruction map of the microcontroller according to the second embodiment. The instruction map is composed of a plurality of pages, and is classified into each page for each division ratio. Therefore, the same operation code is executed at different frequencies depending on the extension code indicating the number of pages of the instruction map. For example, the instruction map A and the instruction map B correspond to frequency division by 1 and frequency division by 2, respectively, and are classified by extension codes '0011' and '0101'. MC1 and MC2 in the map are both instructions having the same execution contents, and have the same machine code other than the extension code. When these codes are processed by the CPU, the same operation is performed by MC1 by dividing by 1 and MC2 is performed by dividing by 2. The extension code corresponding to the frequency division ratio is decoded in the pipeline processing in the same manner as the operation code, and transmitted to the clock frequency division control circuit 803 as the MIR. The clock division control circuit 803 adjusts the switching timing based on the transmitted MIR, outputs the selection signal oscsel to the selector 802, and selects the divided signal in response to the selection signal osscsel, and transmits the divided signal to the CPU 100 as sysclk. I do.
[0054]
The operation of the microcontroller according to the second embodiment as described above will be described using a program example and a timing chart.
[0055]
FIGS. 6A, 6B, and 6C are an instruction format, a program example, and an operation timing chart of the microcontroller according to the second embodiment. Here, similarly to the description of the operation of the microcontroller according to the first embodiment, an operation of switching the frequency division ratio of sysclk from the frequency division of oscin to the frequency division of 1 to 2 and again to the frequency division of 1 by taking an 8-bit microcontroller as an example.
[0056]
The instruction format includes a 4-bit extension code indicating the number of pages of the instruction map, an 8-bit operation code (operation code), and 4 × n-bit (n = 1, 2,...) Operands. The only difference from the microcontroller of the first embodiment is that no frequency control signal is added.
[0057]
In the example of the program, the instructions of (1) to (7) are executed, and the dividing ratio of sysclk is switched from 1 to 2 of oscin from the instruction (3). Switch to The extension code “0011” indicates that the instruction is to set sysclk to oscin divided by 1, and indicates that it is “0101” divided by 2.
[0058]
At the timing A, since the osscsel is “L”, the sysclk operates at a period of 1/1 oscin. The IFB 401 and the IB 402 fetch the instructions (1) -1 and (1) -2 from the ROM 700 at T1. The instruction {circle around (1)}-1 is an extension code, and {circle around (1)}-2 is the first nibble of the operation code and is not an operand, so that any data is output to the IR 403. At timing B, the IR 403 latches (1) -1 and (2) at T2, outputs the latched data to the PLA 404, and the PLA 404 starts decoding. (1) -1 is an extended code, and (1) -2 is not processed until the second nibble of the operation code is fetched. Therefore, at the next timing T1, at timing C1, the MIR ((1) Only μ-1) is output as an extension code recognition cycle. At the same time, the IFB 401 fetches the instructions (1) -3 and (3) -1. At the timing D, the IR 403 captures the remaining one nibble of the operation code (1) -3 of the instruction (1) and decodes it by the PLA 404 together with the processing wait (1) -2. At timing E, the MIR (1) μ-2 of (1) -2,3 is output, and the IFB 401 fetches (3) -2,3. Further, (3) -1 not taken into the IR 403 at the timing D is shifted to the IB 402 at the timing E. When the extension code passes through the IFB 401 and the IB 402 as shown in (3) -1, it is recognized during that time, and is not taken into the IR 403 at the timing F. It is captured.
[0059]
{Circle around (3)}-1 is an extension code, which holds information “0101” of divide-by-2 control, and is decoded while passing through IFB 401 and IB 402 and output to clock generator 800 as MIR. The clock frequency division control circuit 803 adjusts the switching timing, sets osscsel to “H” at timing G, and switches sysclk to 1 / 2oscin. Similarly, it is returned to 1/1 oscin by the extension code of the instruction (6). Since the extension code is fetched and decoded before the operation code, it is desired to operate by the original frequency division by two: (3) μ-1, (3) μ-2, (4) μ-1, (4) μ-2, (6) μ−1, (7) μ−1, and (7) μ−2 to be operated by frequency division can be executed as expected.
[0060]
As described above, according to the second embodiment, by providing the extension code with information for determining the frequency division ratio of the system clock, decoding can be performed in a cycle earlier than the operation code. This makes it possible to minimize the time lag for performing the frequency control, thereby enabling the program developer to more easily and accurately execute the frequency control. Therefore, the power consumption of the microcontroller can be reduced by eliminating the time lag required for the frequency change and executing the frequency control appropriately and quickly according to the task.
[0061]
The number of instructions is not limited to two, ie, frequency division by one and frequency division by two. In addition, the number of instructions does not need to be the same for each division ratio.For example, the number of instructions corresponding to the default division ratio can be limited to several for the instruction corresponding to the default division ratio. is there.
[0062]
The microcontroller 1000 according to the first and second embodiments has a configuration in which a clock generator 800 that generates a system clock is built in, like most general microcontrollers. It may be external.
[0063]
(Embodiment 3)
A microcontroller according to a third embodiment of the present invention will be described.
[0064]
FIG. 7A is a flowchart showing a procedure for generating a machine code and arranging the same in a ROM in the microcontroller according to the third embodiment. FIG. FIG. 4 is a diagram showing a method for performing the operation. As shown in FIG. 7A, a program source created by program development is usually converted into ROM code based on a data file generated by a compiler or the like, and then generated as a layout pattern and stored in the ROM. You. However, in the conventional machine code generation flow, the frequency control signal cannot be added to the machine code unlike the microcontroller according to the first embodiment.
[0065]
In the machine code generation flow according to the third embodiment, the frequency control signal can be added to the machine code by inserting the frequency division ratio setting description into the program source. For example, as shown in the example of the program in FIG. Is executed by dividing by 1 and the instructions (3) and (4) are to be executed by dividing by 2. If the instruction (1) is to be executed, write 'set fast' before the instruction (1) and 'set fast' before the instruction (3). "set fast" is described before the instruction "6". The compiler receives the instruction and the information of 'set fast' or 'set slow' of the preceding stage as input, converts the instruction into machine code, and furthermore, if the preceding frequency division setting description is 'set fast', sets the operation code to '0'. , And if it is 'set slow', '1' is added. If there is no description before the instruction, the additional signal of the previous machine code is continued.
[0066]
That is, the microcontroller according to the third embodiment has the same configuration as that of the first embodiment except that the above-described compiler, the means for converting the machine code generated by the compiler into ROM code, and the means for arranging the ROM are provided. It is.
[0067]
As described above, according to the third embodiment, the addition of the frequency control signal to the operation code can be automatically machine-coded by the compiler without the burden on the program developer. Can be utilized.
[0068]
(Embodiment 4)
A microcontroller according to a fourth embodiment of the present invention will be described.
[0069]
FIG. 8A is a flowchart showing a procedure for generating a machine code and arranging the same in a ROM in the microcontroller according to the fourth embodiment. FIG. FIG. 8C is a timing chart showing the operation of the microcontroller according to the fourth embodiment. The procedure for arranging in the ROM is the same as that in the third embodiment, but the generation rules are different in the process of generating the machine code from the program source by the compiler.
[0070]
In the third embodiment, the frequency control signal to be added to the operation code is determined by 'set fast' and 'set slow'. However, when the frequency division ratio is changed in the microcontroller of the first embodiment, the frequency control signal is added to the operation code. Therefore, it takes a little time from fetching to decoding and execution to switching of the oscsel. For this reason, there is a case where the execution timing of an instruction which originally needs to switch the frequency division ratio cannot be met, and the program developer needs to study the frequency control in detail.
[0071]
In the machine code generation flow of the present embodiment, when the machine codes of the instructions (1) to (7) are generated as in the third embodiment, the division ratio setting description and the execution cycle of the preceding instruction are also changed. Then, the frequency control signal is determined.
[0072]
For example, 'set slow' at the preceding stage of the instruction (3) is originally inserted for the purpose of operating the instruction (3) by dividing by two, but is added to the operation code as shown in FIG. 3 in the first embodiment. Therefore, the switching of the oscsel is delayed, and the switching is actually performed from the execution cycle (4) μ-1 of the instruction (4). As a countermeasure in this case, in order to execute the instruction (3) by dividing by two, the preceding instruction (1) is provided with an additional signal of the control of dividing by two, so that the execution timing G of (3) μ−1 is just obtained. Switches to frequency division by 2. However, when the execution cycle of the instruction (1) is long, the processing frequency of the instruction (1) is divided by two. In the fourth embodiment, if the execution cycle of the preceding instruction of 'set fast' and 'set slow' is less than the reference cycle, it is added to the machine code of the preceding instruction. To the machine code. In the example of FIG. 8, the reference cycle is set to three cycles, and if the execution cycle of the instruction at the preceding stage of 'set fast' and 'set slow' is less than three cycles (that is, two cycles or less), it is added to the machine code of the preceding instruction. If the number of cycles is three or more, the instruction is added to the machine code of the subsequent instruction.
[0073]
That is, the microcontroller of the fourth embodiment has the same configuration as that of the first embodiment, except that the above-mentioned compiler, the means for converting the machine code generated by the compiler into the ROM code, and the means for arranging the ROM are provided. It is.
[0074]
As described above, according to the fourth embodiment, since the addition of the frequency control signal to the operation code is determined according to the number of execution cycles of the instruction, the frequency can be controlled more precisely at the intended timing. Since there is no need for the program developer to perform programming in consideration of the number of execution cycles, the program development efficiency can be improved.
[0075]
(Embodiment 5)
A microcontroller according to a fifth embodiment of the present invention will be described.
[0076]
FIG. 9A is a flowchart showing a procedure of generating a machine code and arranging the same in a ROM in the microcontroller according to the fifth embodiment. FIG. FIG. 4 is a diagram showing a method for performing the operation. The procedure for arranging in the ROM is the same as that in the third embodiment, but the generation rules are different in the process of generating the machine code from the program source by the compiler.
[0077]
In the machine code generation flow of the present embodiment, an extension code corresponding to the division ratio set by inserting the division ratio setting description into the program source is selected, and the instruction at the subsequent stage of the division ratio setting description is It is converted into the corresponding machine code from the instruction map classified by the extension code. For example, as in the example of the program shown in FIG. Is executed by dividing by 1 and the instructions (3) and (4) are to be executed by dividing by 2. If the instruction (1) is to be executed, write 'set fast' before the instruction (1) and 'set fast' before the instruction (3). "set fast" is described before the instruction "6". In the instruction map, an instruction group executed by one division has no extension code, an extension code '0010', an extension code '0011', and an instruction group executed by two divisions has an extension code '0100', extension code '0101', It is assumed that they are classified by the extension code '0110'. The instructions handled by the microcontroller according to the fifth embodiment have the same operation code except for the extension code in the instruction group of 1 and the instruction group of 2 as in the example of FIG. 5 described in the second embodiment. Perform the same operation. The compiler takes an instruction and information of 'set fast' or 'set slow' of the preceding stage as input, and if the preceding stage is' set fast ', converts it into a machine code of a map of an instruction group to be executed by dividing by one, and' set If it is slow ', it is converted into a machine code of a map of an instruction group to be executed by dividing by two. If there is no description in the preceding stage of the instruction, it is assumed that the division ratio is not changed, and the instruction is converted into a machine code of an instruction group having the same division ratio as the preceding stage instruction.
[0078]
That is, the microcontroller of the fifth embodiment has the same configuration as that of the second embodiment, except that the above-mentioned compiler, the means for converting the machine code generated by the compiler into the ROM code, and the means for arranging the ROM are provided. It is.
[0079]
As described above, according to the fifth embodiment, the setting of the division ratio can be reflected in the machine code only by inserting the division ratio setting description, and the characteristics of the microcontroller of the second embodiment can be maximized. Provide a program development environment that can be used effectively.
[0080]
【The invention's effect】
As described above, according to the present invention, by adding information for controlling the frequency to the operation code or retaining the information in the extension code, the frequency can be controlled in the pipeline processing of the execution instruction. The power consumption of the microcontroller can be reduced by eliminating the time lag required for the change and executing the frequency control appropriately and quickly according to the task.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a schematic configuration of a microcontroller according to a first embodiment of the present invention;
FIG. 2 is a block diagram illustrating a schematic configuration of a microcontroller according to the first embodiment of the present invention.
FIG. 3 is an instruction format, a program example, and an operation timing chart of the microcontroller according to the first embodiment of the present invention.
FIG. 4 is a block diagram illustrating a schematic configuration of a microcontroller according to a second embodiment of the present invention;
FIG. 5 is an explanatory diagram of an instruction map of the microcontroller according to the second embodiment of the present invention.
FIG. 6 is an instruction format, a program example, and an operation timing chart of the microcontroller according to the second embodiment of the present invention.
FIG. 7 is a flowchart showing a ROM code generation process in a microcontroller according to a third embodiment of the present invention, and an explanatory diagram thereof;
FIG. 8 is a flowchart showing ROM code generation processing in a microcontroller according to a fourth embodiment of the present invention, an explanatory diagram thereof, and an operation timing chart
FIG. 9 is a flowchart illustrating a ROM code generation process in the microcontroller according to the fifth embodiment of the present invention;
FIG. 10 is a block diagram showing a general schematic configuration of a conventional microcontroller.
FIG. 11 is a block diagram showing a general schematic configuration of a conventional microcontroller.
FIG. 12 is an instruction format, a program example, and an operation timing chart of a conventional microcontroller.
[Explanation of symbols]
100 CPU
200 bus interface
300 data paths
400 instruction decoder
401 Instruction Fetch Buffer (IFB)
402 Instruction Buffer (IB)
403 Instruction register (IR)
404 Programmable Logic Array (PLA)
500 data register
600 address register
700 ROM
800 clock generator
801 clock divider circuit
802 selector
803 Clock frequency division control circuit
804 Clock frequency division control register
1000 microcontroller

Claims (7)

A clock signal corresponding to frequency information is input as a system clock from among a plurality of clock signals having a frequency of 1 / n (n is an integer greater than or equal to 1 in a division ratio) of an oscillation frequency and different frequencies, and The instruction code, which operates in synchronization with a clock and includes an operation code and an operand stored in a memory, fetches and decodes the operation code and the operand by pipeline processing and decodes the instruction based on a result of the decoding. A processor that executes the program,
The operation code is stored in the memory with a frequency control signal for determining a frequency division ratio of the system clock added thereto,
A microcontroller, wherein the processor outputs the frequency information according to the frequency control signal by fetching and decoding the frequency control signal together with the operation code by pipeline processing. A clock signal corresponding to frequency information is input as a system clock from among a plurality of clock signals having a frequency of 1 / n (n is an integer of 1 or more in a division ratio) of an oscillation frequency and different frequencies, and It operates in synchronization with a clock, and fetches and decodes the extension code, the operation code, and the operand by pipeline processing for an instruction program including an extension code, an operation code, and an operand stored in a memory. A processor that executes the instruction program based on the decoding result,
The operation code is constituted by a machine code as an instruction map composed of a plurality of pages classified into pages corresponding to respective division ratios, and the extension code pipelined together with the operation code indicates a page of the instruction map. ,
A microcontroller, wherein the processor outputs the frequency information according to a frequency division ratio corresponding to a page of the instruction map indicated by the extension code by fetching and decoding the extension code by pipeline processing. . A plurality of clock signals having a frequency of 1 / n (n is an integer of 1 or more) of the oscillation frequency and different frequencies are generated, and a plurality of clock signals are generated from the clock signals according to the frequency information output from the processor. 3. The microcontroller according to claim 1, further comprising a clock generator that selects a clock signal and outputs the clock signal to the processor as the system clock. The clock generator includes:
Frequency dividing means for outputting a plurality of clock signals having a frequency of 1 / n (n is an integer of 1 or more in frequency division ratio) of the oscillation frequency and different frequencies;
Selecting means for selecting one clock signal from the plurality of clock signals output by the frequency dividing means based on a selection signal and outputting the selected signal as the system clock;
4. The microcontroller according to claim 3, further comprising control means for outputting the selection signal corresponding to the frequency information output from the processor to the selection means. The frequency control signal is generated in accordance with a division ratio setting description that determines a division ratio of the system clock described in a source program, and is added to the operation code generated from an instruction subsequent to the division ratio setting description. 2. The microcontroller according to claim 1, further comprising means for ROM coding. The frequency control signal is generated in accordance with the frequency division ratio setting description that determines the frequency division ratio of the system clock described in a source program, and the number of execution cycles of an instruction preceding the frequency division ratio setting description is less than a reference. If the frequency control signal is added to the operation code generated from the preceding instruction of the frequency division ratio setting description, and if the frequency control signal is equal to or higher than the reference, the frequency control signal is generated from the subsequent instruction of the frequency division ratio setting description. 2. The microcontroller according to claim 1, further comprising means for adding a ROM code to the operation code. The extension code corresponding to the frequency division ratio is selected according to the frequency division ratio setting description for determining the frequency division ratio of the system clock described in the source program, and the frequency division ratio setting is performed from the instruction map page indicated by the extension code. 3. The microcontroller according to claim 2, further comprising means for selecting the operation code corresponding to an instruction at a later stage of the description and converting the operation code into a ROM code.

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