JP2000298589A - Microprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microprocessor capable of improving operational performance while maintaining interchangeability with a conventional microprocessor as much as possible. SOLUTION: The microprocessor 1 includes plural operation units 7, 8, a register group 6 allowed to be connected to the units 7, 8, a control register 21 capable of setting a value for specifying the operation or non-operation of the unit 8, a decoder 28 for controlling the unit 8 to an operation state or a non-operation state by referring to the value set in the register 7, and a decoder 26 for distributing and allocating registers included in the register group 6 to the unit 7 and the other operation unit 8 controlled to the operation state by referring to the value set in the register 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor including a plurality of arithmetic units and a plurality of general-purpose registers, and capable of controlling the operation and non-operation of a plurality of built-in arithmetic units according to the value of a control register. About.

[0002]

2. Description of the Related Art In the recent market of information home appliances for processing video and audio, the generation change from analog information to digital information is rapidly advancing. Especially AV (Audio Visu
al) MPEG2 (Motion Picture Expert) in the field
In encoding methods such as Group phase 2), advanced arithmetic processing is performed to encode audio and video information, thereby greatly reducing the amount of information while maintaining the original audio and video quality. Is possible. MPEG
It is considered that an encoding method such as 2 is very likely to become a leading role in digital broadcasting in the future.

[0003] On the other hand, however, the data thus coded must be decoded at the time of using the information. Otherwise, you cannot enjoy the original audio or video. Data decoding requires a lot of arithmetic processing as in the case of encoding. In addition, unlike encoding, the time required for decoding is required to be as short as possible. Therefore, in order to reproduce higher-quality video and audio, a processor having advanced arithmetic processing capability is required.

[0004] As a technique for improving the arithmetic performance of a processor, it is conceivable to increase the degree of parallelism of the arithmetic operations performed simultaneously. One example is disclosed in, for example, JP-A-63-20183.
No. 0 discloses this. This publication discloses an information processing apparatus including a plurality of arithmetic units and a parallel control register indicating which arithmetic unit is used. Parallel operation on operation register words is possible by providing a mechanism to operate one or more operation units simultaneously based on the contents of the parallel control register or the operand specification indicating one or more operation registers after the instruction. It is stated that such a parallel operation and a general operation can be performed by the same instruction system.

[0005]

However, in this conventional technique, it is necessary to specify which operation unit executes the instruction and which operation register is used in the operation by the operand of the instruction. Therefore, even if, for example, a parallel operation and a general operation can be performed with the same instruction system, since the instruction system itself is different from the conventional instruction system, a single operation unit that already exists is provided. There has been a problem that software for the information processing device must be significantly changed.

On the other hand, for example, the simplest method for enhancing the processing capability of an information processing device (processor) having a single arithmetic unit already existing is to use a plurality of arithmetic units. . However, in this case, it is preferable to maintain compatibility with the software before such extension as much as possible.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor which has improved arithmetic performance while maintaining compatibility with a conventional microprocessor as much as possible.

Another object of the present invention is to provide a microprocessor which uses a plurality of arithmetic units to improve arithmetic performance and reduce power consumption while maintaining compatibility with conventional microprocessors as much as possible. To provide.

[0009]

According to a first aspect of the present invention, there is provided a microprocessor comprising: a plurality of operation units including a first operation unit; a register group connectable to the plurality of operation units; Of the arithmetic units
The control information storage means capable of setting a value for designating the operation or non-operation of each of the operation units other than the first operation unit, and the first value by referring to the value set in the control information storage means.
An operation unit control unit for controlling each of the operation units other than the operation unit to an operation state or a non-operation state, and a value set in a control information storage unit.
And a register allocating means for distributing and allocating registers included in the register group to the arithmetic unit controlled by the arithmetic unit control means.

By setting a certain value in the control information storage means, the operation units other than the first operation unit can be controlled to be in an operation state or a non-operation state. When only the first arithmetic unit is in the operating state, the same operation as that of the microprocessor having only a single arithmetic unit is possible. On the other hand, when the operation units other than the first operation unit are made operable, the operation performance can be improved.

According to a second aspect of the present invention, in addition to the configuration of the first aspect, the microprocessor according to the first aspect further comprises a clock signal to the arithmetic unit controlled to be in an inactive state by the arithmetic unit control means. Control for controlling the supply of the clock signal so as to stop the supply of the clock signal and to supply the clock signal to the first arithmetic unit and the arithmetic unit controlled to be in the operating state by the arithmetic unit control means And means.

According to the second aspect of the present invention, in addition to the operation of the first aspect of the present invention, the supply of the clock signal to the operation units controlled to the non-operation state is stopped. The included arithmetic unit does not operate at all. On the other hand, a clock signal for operation is supplied to each of the operation units controlled to the operation state,
Operations can be performed in parallel.

According to a third aspect of the present invention, in the microprocessor according to the first or second aspect, the arithmetic unit control means is provided for each of the plurality of arithmetic units. A selection means for selecting one of the instruction code and the NOP instruction code with reference to a value set in the control information storage means and providing the selected operation code to a corresponding arithmetic unit is included.

With this configuration, each operation unit can be easily set to either the operation state or the non-operation state by a simple mechanism.

[0015]

FIG. 1 schematically shows a hardware configuration of a 32-bit microprocessor according to an embodiment of the present invention. The microprocessor 1 includes an instruction decode unit 2 and an instruction RAM (Random Access Memory).
y) 3, a data RAM 4, a memory unit 5, a general-purpose register group 6 forming a register file, a first operation unit 7, a second operation unit 8, and a clock for the second operation unit 8. And a control unit 9.

The instruction decode unit 2 has a control register (CR) / processor status word (PSW: Processor Stat).
us Words) 21, a decoder 25 corresponding to the memory unit 5, and a decoder 26 corresponding to the general-purpose register group 6.
And a decoder 27 corresponding to the first arithmetic unit 7,
And a decoder 28 corresponding to the second arithmetic unit 8. The instruction decoder unit 2 has 64 instruction RAMs.
The instruction code sent through the data bus having a bit width is subjected to decoding processing using the decoders 25, 26, 27 and 28.

The decoder 25 decodes the instruction code from the instruction RAM 3 based on the CR / PSW 21 and generates a control signal 15 to the memory unit 5. CR / PSW2
1, the decoder 26 decodes the instruction code from the instruction RAM 3 so that the control signal 16 corresponding to the first operation unit 7 for the general-purpose register group 6 is obtained.
And a control signal 18 corresponding to the second arithmetic unit 8 are generated. Instruction RAM 3 based on CR / PSW 21
Is decoded by the decoder 27 to generate the control signal 17 to the first arithmetic unit 7. The decoder 28 decodes the instruction code from the instruction RAM 3 based on the CR / PSW 21,
A control signal 19 to the second arithmetic unit 8 is generated.

The instruction RAM 3 is connected to a 32-bit address bus 53 and a 64-bit data bus 32. The instruction RAM 3 outputs 64-bit instruction data corresponding to the address indicated by the address bus 53.
The data RAM 4 is connected to a 32-bit address bus 54 and a 64-bit data bus 55. Data RAM 4 can read and write 64-bit data corresponding to the address indicated by address bus 54.

The memory unit 5 includes a PC (program counter) controller 51 and a memory controller 52. P
The C control unit 51 calculates the PC value of the next command to be executed according to the command. That is, for instructions other than the jump operation and the branch operation, the PC control unit 51 adds 8 to the PC value of the executed instruction and calculates the PC value of the next instruction to be executed. In the jump operation and the branch operation, the PC control unit 51 calculates the PC value of the jump destination instruction by adding a branch displacement to the PC value of the executed instruction or performing a calculation according to the addressing mode specified by the operation.

The memory control unit 52 activates the instruction RAM 3 using the address bus 53 to the instruction RAM 3 based on the PC value calculated by the PC control unit 51, and outputs an instruction code specified by the PC value. Although not shown, data necessary for executing the instruction is provided by giving a data address to an address bus, reading the data from the data RAM 4, and transferring the data to the general-purpose register group 6 via the data bus.

Referring to FIG. 2, general-purpose register group 6 includes
Four 32-bit registers R0, R1, ..., R31, R
32,..., R63. These registers can simultaneously output as many register values as necessary for the operations in the first operation unit 7 and the second operation unit 8. The read data is supplied to first operation unit 7 or second operation unit 8 via data buses 67 and 68, respectively. The operation result values from the first operation unit 7 and the second operation unit 8 can be simultaneously written into the general-purpose register group 6.

The first arithmetic unit 7 includes a multiplier (MP)
Y) 71 and ALU (Arithmetic and Logic Unit) 72
And a shifter 73. Similarly, the second arithmetic unit 8
Includes a multiplier 81, an ALU 82, and a shifter 83. Multiplier 71 and multiplier 81, ALU 72 and ALU 8
2. The shifter 73 and the shifter 83 are arithmetic units having exactly the same function. Therefore, the first operation unit 7 and the second operation unit 8 are operation units having exactly the same function.

The clock control unit 9 for the second arithmetic unit 8 receives a chip clock 90 used inside the microprocessor 1 as an input, and
Is for generating or controlling a clock 91 to be supplied to the second arithmetic unit 8 based on the value of.

Referring to FIG. 3, CR / PSW 21 has the following configuration. The upper 16 bits 100 of the CR / PSW 21 include an SM field 101 for switching a stack pointer and a software debug trap (SDB).
T), an EA field 102 indicating detection of SDT, a DB field 103 specifying permission of SDBT, an IE field 104 specifying permission of interruption, an RP field 105 specifying permission of repeat operation, and a permission of modulo addressing. It includes an MD field 106 for specifying and a WM bit 120 for specifying whether to use the second arithmetic unit 8.

The lower 16 bits of the CR / PSW 21 are a flag field 110. Flag field 110
Includes eight flags F0 to F7. These flags are used to control the validity and invalidity of the operation, respectively.
The value of each flag changes depending on the result of the comparison operation or the arithmetic operation. The value of each flag is initialized by a flag initialization operation. Furthermore, the value of each flag is changed by writing an arbitrary value to the CR / PSW 21 by a flag value write operation. By using the flag value read operation, CR / PS
It is also possible to read the value of W21.

Referring to FIG. 4, the decoder 28 for the second arithmetic unit 8 includes an instruction code 200 which is the same as the instruction code given to the decoder 27 for the first arithmetic unit 7 as an input, and a NOP (no operation). ) NOP instruction fixed code 201 for fixedly outputting an instruction;
It receives the WM bit 120 in the R / PSW 21. As described above, the WM bit 120 is a value that specifies whether to use the second arithmetic unit 8.

The decoder 28 receives the instruction code 200 and NO
It includes a two-input selector 202 that receives P instruction fixed code 201 and is controlled by WM bit 120, and a decoder 210 that decodes an instruction code output from two-input selector 202. The decoder 210 has exactly the same configuration as the decoder 27 (see FIG. 1) corresponding to the first arithmetic unit 7. The selector 202 selects the NOP instruction fixed code 201 when the value of the WM bit 120 is “0”, and selects the instruction code 200 when the value of the WM bit 120 is “1”. I have.

Referring to FIG. 5, decoder 26 for general-purpose register group 6 is provided with WM bit 12 in CR / PSW 21.
0, general-purpose register (GPR) selection code (SEL_GP
R [0: 5]) 300 as input. The decoder 26 controls the control signal 16 for selecting the register used in the first arithmetic unit 7 from the 64 registers R0 to R63 and the register used in the second arithmetic unit 8 as 32 registers. A control signal 18 for selecting from R32 to R63 is output.

The decoder 26 outputs the inverted value of the WM bit 120 from the CR / PSW 21 and the GPR selection code 3
AND circuit 304 receiving the most significant bit 302 of 00
And a GPR decoder 310 for the second arithmetic unit that receives the lower 5 bits 301 of the GPR selection code 300
And the lower 5 bits of GPR selection code 300 and AN
Upon receiving the signal 303 output from the D circuit 304, the control signal 1
GPR decoder 3 for first arithmetic unit that outputs 6
20 and a GPR decoder 310 for the first arithmetic unit
Includes 32 AND circuits 340 for performing an AND operation on each of the 32-bit control signals 330 output by the.

Referring to FIG. 6, clock control unit 9 for second arithmetic unit 8 receives as input chip clock 90 used in microprocessor 1 and WM bit 120 in CR / PSW 21. The clock control unit 9 includes an AND circuit 92 for calculating a logical product of these two input signals and outputting the logical product as a clock 91 for the second arithmetic unit 8.

The microprocessor 1 configured as described above operates as follows. [When the second arithmetic unit is not used] When the second arithmetic unit 8 is not used, the WM bit 120 in the CR / PSW 21 is set to “0”. In this case, the first arithmetic unit 7
The control signal 17 given from the instruction decode unit 2 is the result of decoding the instruction code read from the instruction RAM 3 using the decoder 27 for the first arithmetic unit. This signal is a signal for operating an arithmetic unit (any one of the multiplier 71, the ALU 72, and the shifter 73) in the first arithmetic unit 7, which is necessary for performing the arithmetic specified by the instruction code.

On the other hand, the control signal 19 for the second arithmetic unit 8 is as follows. The instruction code read from instruction RAM 3 is applied to decoder 28 for second operation unit 8. Referring to FIG. 4, decoder 28 selects NOP instruction fixed code 201 and gives it to decoder 210 as instruction code 203 because WM bit 120 in CR / PSW 21 is “0”. The decoder 210 decodes this instruction code, but since the instruction code is a NOP instruction, the second operation unit 8 does not perform the operation as a result. That is, the second arithmetic unit 8
All the arithmetic units (multiplier 81, ALU 82, shifter 8
3) does not work.

As described above, when the WM bit 120 in the CR / PSW 21 is "0", the first arithmetic unit 7
Only the second operation unit 8 does not operate.

The decode 26 for the general purpose register group 6 operates as follows. Referring to FIG. 5, if WM bit 120 is "0", AND circuit 340 outputs all "0". Therefore, regardless of the decoding result of the decoder 310, all bits of the 32-bit control signal 18 for selecting a register used by the second operation unit 8 are always "0". None of the registers becomes active, and none of the registers included in the general-purpose register group 6 are used by the second arithmetic unit 8.

On the other hand, WM bit 1 in CR / PSW 21
Since 20 is “0”, the output of the AND circuit 304 is GPR
It has the same value as the most significant bit 302 of the selection code 300. That is, the output 303 of the AND circuit 304 and the GPR
The lower 5 bits 301 of the selection code 300 are input to the GPR decoder 320 for the first arithmetic unit. As a result of the decoding, a 64-bit control signal 16 for selecting a register used in the first arithmetic unit 7 from the 64 registers R0 to R63 is generated. The registers in the general-purpose register group 6 designated by the control signal 16 are used in the operation in the first operation unit 7.

As described above, when the WM bit 120 in the CR / PSW 21 is "0", the first arithmetic unit 7
Is used in the general register group 6
It is selected from four registers R0 to R63 and used. On the other hand, no registers are used for the second arithmetic unit 8. Thus, by setting the value of the WM bit 120 to 0, it is possible to operate in the operation mode in which the first arithmetic unit is used alone. Moreover, when only the first operation unit is used, all 64 registers can be used in the first operation unit 7.

Further, referring to FIG.
If 0 is “0”, the second output from the AND circuit 92
Is always a fixed signal of "0". Therefore, each operation unit of the second operation unit 8 does not operate at all, and power consumption can be reduced.

As described above, the WM in the CR / PSW 21
When the bit is “0”, the first operation unit 7 actually performs the operation, but the second operation unit 8 does not perform the operation. Moreover, the first arithmetic unit can use all 64 registers. On the other hand, since the clock 91 is not supplied to the second arithmetic unit, its internal circuit does not operate at all.

[When the second arithmetic unit 8 is used]
When the second arithmetic unit 8 is used, CR / PS
The WM bit 120 in W21 is set to “1”.

Also in this case, the control signal 17 (see FIG. 1) applied to the first arithmetic unit 7 includes the instruction RA
This is a result of decoding the instruction code read from M3 using the decoder 27. Therefore, this signal is necessary to perform the operation specified by the instruction code.
The arithmetic unit (multiplier 71, ALU) in the first arithmetic unit 7
72 or one of the shifters 73).

On the other hand, the control signal 19 (see FIG. 1) for the second arithmetic unit 8 is as follows. Instruction RAM3
Is supplied to the decoder 28 for the second arithmetic unit 8. Referring to FIG. 4, selector 202 of decoder 28 determines that WM bit 120 is “1”.
Therefore, the input instruction code 200 is selected and given to the decoder 210 as the instruction code 203. The decoder 210 decodes the instruction code 203 and outputs the control signal 19. The decoder 210 has exactly the same configuration as the decoder 27 for the first arithmetic unit 7 as described above. Therefore, since the input instruction code 203 is exactly the same as that supplied to the decoder 27 for the first arithmetic unit 7, the control signal 19 output from the decoder 210 becomes the control signal 17 output from the decoder 27. Will be the same as As a result, the second operation unit 8 performs exactly the same operation as the first operation unit 7.

On the other hand, referring to FIG.
Operates as follows. CR / PSW
When the WM bit 120 in 21 is “1”, the output 303 of the AND circuit 304 is always “0”. That is, the first
The GPR decoder 320 for the arithmetic unit 7 of
“0” + the lower 5 bits 301 of the GPR selection code are input. In this case, among the control signals 16 (64 bits) output from the decoder 320, the signals can select only the 32 registers R0 to R31 in the general-purpose register group 6. The lower 32 bits of the control signal 16 [3
2:63] will not be active. The register in the general-purpose register group 6 selected by the control signal 16 is used for the operation in the first operation unit 7.

On the other hand, referring to FIG. 5, the lower 5 bits 301 of GPR selection code 300 are applied to GPR decoder 310 for the second arithmetic unit, as in the case where WM bit 120 is “0”. . As a result, the decoder 310
Output from the general-purpose register group 6
It is a 32-bit signal for selecting a register to be used from the two registers R32 to R63. Thus, the control signal 330 given to each AND circuit 340 is
Since the WM bit 120 is “1”, it is output as the control signal 18 as it is. Therefore, in this case, the register corresponding to the 32-bit control signal 18 in the general-purpose register group 6 is used for the operation in the second operation unit 8.

Thus, when the WM bit 120 in the CR / PSW 21 is “1”, the first operation unit 7 performs the operation using the 32 registers R 0 in the general-purpose register group 6.
To R31, the register specified by the control signal 16 is selected and used. On the other hand, the operation of the second arithmetic unit 8 includes 32 registers R32 to R32 in the general-purpose register group 6.
The register specified by the control signal 18 is selected and used from R63.

In this case, referring to FIG. 6, since WM bit 120 is "1", AND circuit 92 outputs clock 90 as it is as clock 91 of the second arithmetic unit. That is, the same clock as the clock 90 is also supplied to the second arithmetic unit, and the second arithmetic unit operates in the same manner as the first arithmetic unit.

Thus, when the WM bit 120 in the CR / PSW 21 is "1", the first arithmetic unit 7 selects a register selected from the 32 registers R0 to R31 in the general register group 6. On the other hand, the second operation unit 8 performs the same operation on each of the registers selected from the 32 registers R32 to R63 in the general-purpose register group 6.

As described above, in the microprocessor of this embodiment, if the WM bit in the CR / PSW 21 is set to "0", the operation can be performed using only the first operation unit 7. Moreover, in this case, all of the 64 general-purpose register groups 6 are transferred to the first arithmetic unit 7.
Can be used for the calculation in On the other hand, when the WM bit is set to “1”, the first operation unit 7 and the second operation unit 8 can execute exactly the same operation. Further, in this case, the first arithmetic unit 7 and the second arithmetic unit 8 are provided with two registers of the general-purpose register group 6.
Each can be allocated and made available. In this case, as the second arithmetic unit 8, the same unit as the first arithmetic unit 7 can be used. Therefore, for example, if the second arithmetic unit 8 is set to be inactive, a program that can be executed in a conventional device having only the first arithmetic unit 7 can be executed without any change. Also, when operating two execution units, the register file is automatically handled as if it were apparently divided, so that it is not necessary to change the fields in the instruction code, etc. Can be maintained to the maximum.

As described above, it is possible to add an arithmetic unit having the same configuration to the microprocessor and control the operation and non-operation of the added arithmetic unit using the value of the control register. To perform the same operation,
A plurality of operation units can be operated in parallel, and higher operation performance than before can be realized.
On the other hand, if only a single arithmetic unit is operated, it is possible to execute the same program as before without any change.

By stopping the clock supply to the inoperative arithmetic unit, not only the operation of the arithmetic unit can be stopped, but also the power consumption can be reduced since all the circuits in the arithmetic unit do not operate. it can.

Further, the instruction code is switched to the NOP instruction for the operation unit which does not operate.
Use a selector controlled by M bits. Therefore, the operation of the arithmetic unit can be controlled by a very simple mechanism.

In the apparatus of the above-described embodiment, an example is shown in which only one set of arithmetic units is added and two sets of arithmetic units are used. However, the present invention is not limited to this embodiment. By increasing the number of bits of the WM field in the CR / PSW 21, it is possible to easily add and control a plurality of sets of arithmetic units in the same manner.

It should be understood that the embodiments disclosed this time are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0053]

As described above, according to the first aspect of the present invention, only the first arithmetic unit can be brought into the operating state. In this case, the microprocessor having only a single arithmetic unit can be used. Exactly the same operation is possible. On the other hand, when the operation units other than the first operation unit are made operable, the operation performance can be improved. Therefore,
It is possible to provide a microprocessor having improved arithmetic performance while maintaining compatibility with a conventional microprocessor as much as possible.

According to the invention described in claim 2, according to claim 1
In addition to the effects of the invention described in (1), the supply of the clock signal to the arithmetic unit controlled to the non-operating state is stopped. Since the operation units included in these operation units do not operate at all, power consumption can be reduced. As a result, it is possible to provide a microprocessor in which the arithmetic performance is improved using a plurality of operation units and the increase in power consumption is reduced while maintaining compatibility with the conventional microprocessor as much as possible.

According to the third aspect of the present invention, there is provided a microprocessor which has a simple configuration and has improved arithmetic performance using a plurality of arithmetic units while maintaining compatibility with a conventional microprocessor as much as possible. Can be provided.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a microprocessor according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a general-purpose register group 6;

FIG. 3 is a diagram illustrating a state after a control register / processor state of the microprocessor according to the embodiment of the present invention;

FIG. 4 is a diagram illustrating a decoder for a second arithmetic unit of the microprocessor according to the embodiment of the present invention;

FIG. 5 is a diagram illustrating a configuration of a decoder for a general-purpose register group in the microprocessor according to the embodiment of the present invention;

FIG. 6 is a diagram illustrating a clock control unit 9 for a second arithmetic unit in the microprocessor according to the embodiment of the present invention.

[Explanation of symbols]

1 microprocessor, 2 instruction decoding unit,
3 instruction RAM, 4 data RAM, 5 memory units, 6 general-purpose register group, 7 first operation unit, 8
Second arithmetic unit, 9 clock controller, 21 control register / processor status word (CR / PSW).

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 9/34 330 G06F 15/78 510P 15/78 510 9/30 340A

Claims (3)

[Claims] A plurality of operation units including a first operation unit; a register group connectable to the plurality of operation units; and a plurality of operation units other than the first operation unit. Control information storage means capable of setting a value designating each of the operation units as an operation state or a non-operation state; and an operation unit other than the first operation unit with reference to the value set in the control information storage means An operation unit control unit for controlling each of the operation units to an operation state or a non-operation state; and a first operation unit and an operation unit operated by the operation unit control unit with reference to a value set in the control information storage unit. A register allocation means for distributing and allocating registers included in the register group to the operation unit controlled to the state. Support. 2. A supply of a clock signal to an arithmetic unit controlled to be in an inactive state by the arithmetic unit control means is stopped, and an operation state is controlled by the first arithmetic unit and the arithmetic unit control means. 2. The microprocessor according to claim 1, further comprising: clock control means for controlling supply of a clock signal so as to supply the clock signal to the arithmetic unit controlled to be controlled. 3. The arithmetic unit control means stores one of an instruction code given to each of the plurality of arithmetic units and a NOP instruction code in a value set in the control information storage means. And selecting means for making a selection with reference to the corresponding arithmetic unit and providing the selected arithmetic unit to the corresponding arithmetic unit.
Or a microprocessor according to claim 2.