JP2007058331A - Processor system and multithread processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stabilize processing performance even when cycles of processing are very short or when the clock frequency of a processor is lowered in order to reduce the power consumption of the processor. <P>SOLUTION: A multithread processor which outputs a clock frequency control signal to a clock generating circuit and inputs a processor operating frequency generated in the clock generation circuit, schedules at least one thread in fixed cycles based upon the clock frequency control signal irrelevantly to the processor operating frequency. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a thread scheduling method in a multi-thread processor that makes processing performance constant for a specific thread even when the operating frequency of the processor changes.

  Conventionally, in a processor system, if a device connected to the system transmits and receives data at a constant cycle, it is necessary to guarantee that the processing performance of the system is constant in order to prevent data loss or supply shortage. (For example, refer to Patent Document 1).

  For example, if serial data communication is performed by software, it must be ensured that the processing speed of the processor system is constant so as not to cause a data transfer error due to a time axis shift during data transfer.

In order to guarantee that the processing performance is constant, a method of generating an interrupt with a constant period using a timer is generally used. In addition, in some processors, it is ensured that the processing performance is constant by eliminating from the processor a mechanism that varies the processing performance of the processor such as a cache or a branch prediction mechanism. For example, Ubicom's IP3023 processor guarantees constant processing performance by not including a cache or branch prediction mechanism. This is because the mechanism for changing the processing performance of the processor increases the performance of the processor in many cases, but sometimes reduces the performance of the processor.
Japanese Unexamined Patent Publication No. 07-114517

  However, in these processor systems, it is possible to make the processing performance constant, but there are limitations. For example, a method of generating an interrupt with a fixed period using a timer cannot be used for an application with a very short processing period due to an overhead caused by a cycle for starting and ending interrupts. Further, in the method of eliminating the mechanism for changing the processing performance from the processor, the processing performance changes depending on the clock frequency of the processor. Therefore, the power consumption cannot be reduced by lowering the clock frequency of the processor.

  The present invention has been made in order to solve the above-described problems. Even when the processing cycle is very short or when the clock frequency of the processor is lowered in order to reduce the power consumption of the processor, the processing performance is kept constant. The purpose is to do.

  The present invention is a processor system including a clock generation circuit and a multi-thread processor, wherein the clock generation circuit inputs a clock frequency control signal from the multi-thread processor, and based on the clock frequency control signal A scheduling unit configured to generate one or more threads at a constant period regardless of the processor operating frequency based on the clock frequency control signal; It has the means.

  The present invention is also a multi-thread processor that outputs a clock frequency control signal to a clock generation circuit and inputs a processor operating frequency generated by the clock generation circuit, based on the clock frequency control signal. There is provided a scheduling means for scheduling one thread at a constant cycle regardless of the processor operating frequency.

  According to the present invention, by inputting the operating frequency of the processor to the thread scheduler, it is possible to make constant the period in which threads that require constant processing performance are scheduled. As a result, the processing performance can be made constant even when the processing cycle is very short or when the clock frequency of the processor is lowered in order to reduce the power consumption of the processor.

  The best mode for carrying out the invention will be described below in detail with reference to the drawings.

  FIG. 1 is a diagram illustrating an example of the configuration of a multi-thread processor system according to the present embodiment. As shown in FIG. 1, the multithread processor system includes a clock generation circuit (CLKGEN) 100 and a multithread processor 101. The clock generation circuit 100 and the multi-thread processor 101 are connected by at least a processor clock (CLK) 120 and a frequency control signal (FREQCTRL) 121.

  Further, since the multi-thread processor 101 operates in synchronization with the processor clock 120, the operating frequency of the multi-thread processor 101 is proportional to the frequency of the processor clock 120. Here, the frequency control signal 121 is a signal for changing the frequency of the processor clock 120. In the following description, it is assumed that the frequency of the processor clock 120 is 100 MHz when the frequency control signal 121 is “0”, and that the frequency of the processor clock 120 is 200 MHz when the frequency control signal 121 is “1”. .

  The multi-thread processor 101 includes a thread scheduler (SCHED) 110, a data path 116, and a control circuit (CTRL) 115. The data path 116 includes at least two program counters, a register file (RF) 112, a numerical operation unit (ALU) 113, and a memory (MEM) 114. In FIG. 1, there are four program counters, PC # 0 (111a) to PC # 3 (111d).

  Next, the operation of each block in the multi-thread processor 101 and the typical signal connection relationship will be described with reference to FIG.

  In FIG. 2, the thread scheduler 110 selects a thread number (thread #) 201 to be executed based on the frequency control signal 121 output from the control circuit 115, and outputs it to the data path 116. Thereby, the data path 116 first selects the program counter corresponding to the thread number 201 to be executed from the program counters 111a to 111d. The data bus 116 uses the selected program counter and the thread number 201 to be executed, and uses the register file 112, the numerical operation unit 113, and the memory 114 for instruction fetch, instruction decode, execution, operand fetch, and result storage. Do it.

  The result of the instruction execution described above is stored in the register file 112 and the memory 114, and a flag for performing conditional branching and a result of writing to the control register are output to the control circuit 115 using the signal 204. Based on this signal 204, the control circuit 115 receives the output result of the data path, and generates various control signals to the thread scheduler 110 and the data path 116. The generated control signal is output as a control signal 202 to the thread scheduler 110 and a control signal 203 to the data path 116.

  Next, the configuration and operation of the thread scheduler 110 that can keep the processing performance of a specific thread constant even when the operating frequency of the multi-thread processor 101 changes will be described with reference to FIG. In FIG. 3, the operating frequency of the processor is two stages of 200 MHz and 100 MHz in order to simplify the description.

  FIG. 3 is a diagram illustrating an example of the configuration of the thread scheduler 110 in the multi-thread processor 101. As shown in FIG. 3, the thread scheduler 110 includes two hard real-time thread tables 220a and 220b in order to control the processing performance of a specific thread constant for each operating frequency of the processor. The hard real-time thread tables 220a and 220b hold threads (hard real-time threads) that need to be scheduled for each predetermined number of cycles.

  On the other hand, the non-real-time thread table 221 holds threads that do not need to be scheduled every predetermined number of cycles (threads that do not need to guarantee performance).

  Here, the thread scheduler 110 selects a thread recorded in either the hard real-time thread table 220a or 220b or the non-real-time thread table 221 based on the operating frequency of the processor. Specifically, according to the frequency control signal 121 output from the control circuit 115, the multiplexer 147 selects either the thread 223a or 223b stored in the hard real-time thread table 220a or 220b. At the same time, the multiplexer 148 selects either the thread schedule information 224a or 224b stored in the hard real-time thread table 220a or 220b. Then, based on the selected thread schedule information, the multiplexer 244 outputs the thread recorded in either the hard real-time thread table 220a, 220b or the non-real-time thread table 221 as the thread number 201.

[Constant operating frequency]
First, a thread scheduling method executed by the thread scheduler 110 when the operating frequency is fixed at 200 MHz, that is, when the frequency control signal 121 is always “1” will be described. In this case, the operation is the same as that of a conventional multi-thread processor that can guarantee real-time performance. That is, since the frequency control signal 121 is always “1”, only the hard real-time thread table 220b is referred to by the multiplexers 147 and 148, and the hard real-time thread table 220a is not referred to. Therefore, the hard real-time thread table 220a and the multiplexers 147 and 148 can be omitted in a multi-thread processor that can guarantee real-time performance.

  Here, the hard real-time thread table pointer (HRTP) 242 is incremented by “1” by the incrementer 247 every cycle, and the elements of the hard real-time thread table 220b are sequentially read from the top every cycle. In the example shown in FIG. 3, the hard real-time thread table 220b holds eight elements. That is, the thread schedule for 8 cycles is held.

  Each element of the hard real-time thread table 220b includes a hard real-time bit 224b and a thread ID 223b. Here, when the hard real-time bit 224b is “1”, it indicates that the thread indicated by the thread ID 223b is scheduled. On the other hand, when the hard real-time bit 224b is “0”, the threads recorded in the non-real-time thread table 221 are executed in order.

  That is, in this example, the thread 0 is executed in the first cycle, the thread 1 is executed in the second cycle, and the threads in the non-real-time thread table 221 are executed in the third to fifth cycles. Then, the thread 1 is executed in the sixth cycle, and the threads in the non-real-time thread table 221 are executed in the seventh and eighth cycles.

  Thus, since the hard real-time thread table 220b holds the thread schedule for 8 cycles, the 9th cycle is the same as the 1st cycle. Thereafter, the elements of the hard real-time thread table 220b in the first to eighth cycles are read in order of repetition.

  The threads recorded in the non-real-time thread table 221 are executed in order only when the hard real-time bit 224b is “0”. That is, the hard real-time bit 224b is “0”, and the thread ID pointed to by the non-real-time thread table pointer 243 is selected by the multiplexer 244 and output as the thread number 201. At the same time, the non-real time thread table pointer 243 is incremented by the incrementer 248 selected by the multiplexer 249.

  On the other hand, when the hard real-time bit 224b is “1”, the thread ID output from the hard real-time thread table 220b is selected by the multiplexer 244 and output as the thread number 201. Note that the non-real time thread table pointer 243 is not updated.

  In this way, when the operating frequency of the processor is constant, the hard real-time thread is scheduled for each determined cycle, so that the processing performance of a specific thread can be kept constant.

[Change in operating frequency]
Next, a thread scheduling method executed by the thread scheduler 110 in the multi-thread processor 101 when the operating frequency of the processor changes to 1/2 (100 MHz) will be described.

  A thread whose processing performance needs to be constant regardless of the operating frequency is assumed to be thread 0. In this case, the frequency control signal 121 becomes “0”, and the hard real-time thread table 220 a is referred to by the multiplexers 147 and 148.

  Further, since the operating frequency of the processor is ½, the ratio of the thread 0 included in the hard real-time thread table 220a is doubled that of the hard real-time thread table 220b.

  In addition to the first cycle originally scheduled, 5 cycles including the number of elements 8 × (1/2) = 4 cycles so that the phase in which thread 0 is scheduled is the same regardless of the operating frequency of the processor. Let thread 0 be scheduled for the eye.

  Here, since the operating frequency of the processor has changed to ½, the cycle for reading the hard real-time thread table 220a is doubled. However, since the thread 0 that is required to have a constant processing performance is included twice in the hard real-time thread table 220a, the thread 0 is eventually scheduled at the same cycle.

  As described above, in this embodiment, by switching the hard real-time thread table together with switching of the processor operating frequency, the processing performance of a specific thread can be kept constant even when the processor operating frequency changes. As a result, as shown in FIG. 4, when the operating frequency of the processor is switched between 200 MHz and 100 MHz, the scheduled period of the thread 0 is changed in the conventional example, but in this embodiment, the thread 0 is always set to 40 ns. Can be scheduled in cycles. That is, a certain performance can be maintained.

[Other Embodiments]
Next, another embodiment according to the present invention will be described in detail with reference to the drawings.

  In another embodiment, if the operating frequency of the processor is n times the reference frequency, the selection signal is enabled once out of n times, but the selection signal is applied n-1 out of n times. A circuit for disabling is provided.

  A thread that needs to have a constant processing performance even if the operating frequency of the processor changes is scheduled only when the selection signal is “1”. As a result, the processing performance of a specific thread can be made constant. In order to simplify the description, an example will be described in which the operating frequency of the processor is two stages and the maximum processor operating frequency is twice the operating frequency of the reference processor.

  The configuration of the multi-thread processor system in the other embodiments is the same as the configuration of the present embodiment described with reference to FIG.

  FIG. 5 is a diagram illustrating an example of a configuration of a thread scheduler according to another embodiment. In addition, the same code | symbol is attached | subjected to what has the same function as the structure shown in FIG.

  As shown in FIG. 5, the thread scheduler includes at least a hard real-time thread table 222, a non-real-time thread table 221, and a thread selection signal generation circuit 240. Here, the thread selection signal generation circuit 240 is a circuit that generates a signal (TSEL OUT) 141 that enables the selection signal for a fixed number of cycles regardless of the operating frequency of the processor, and will be described in further detail with reference to FIG. The hard real-time thread table 222 holds a thread ID 223 and information about two threads 224 and 225. The two threads are a thread that needs to be scheduled every predetermined number of processor cycles (hard real-time thread) and a thread that requires constant processing performance regardless of the clock frequency of the processor (real-time thread).

  FIG. 6 is a diagram illustrating an example of the configuration of the thread selection signal generation circuit 240. The thread selection signal generation circuit 240 includes a counter 262 that counts the number of cycles when the frequency control signal 121 is “1”, and a gate 263 and an inverter 264 that output “1” when the frequency control signal 121 is “0”. It consists of and.

  In the example shown in FIG. 6, when the frequency control signal 121 is “0”, “1” indicating “valid” is output as the selection signal 141 for eight cycles, and “invalid” is selected as the selection signal 141 for the next eight cycles. “0” is output. Therefore, the counter 262 is used to count the number of cycles using a 4-bit binary counter, and Q3 is used as an output signal.

  First, a thread scheduling method executed by the thread scheduler when the frequency control signal 121 is “0” (the operating frequency of the reference processor) will be described. In this case, “1” is always output as the selection signal 141 by the inverter 264 and the gate 263 of the thread selection signal generation circuit 240.

  Here, the hard real-time thread table pointer (HRTP) 242 is incremented by “1” by the incrementer 247 every cycle, and the elements of the hard real-time thread table 222 are read sequentially from the top every cycle. In the example shown in FIG. 5, the hard real-time thread table 222 holds a schedule of threads for 8 cycles, and thus holds 8 elements.

  The elements of the hard real-time thread table 222 include a hard real-time bit 224, a real-time bit 225, and a thread ID 223. Here, the hard real-time bit 224 indicates that the thread needs to be scheduled every predetermined number of processor cycles. The real-time bit 225 indicates that the thread requires a certain processing performance regardless of the processor clock frequency.

  In this example, since the thread selection signal generation circuit 240 always outputs “1”, when either the hard real-time bit 224 or the real-time bit 225 is “1”, the thread in the hard real-time thread table 222 is selected. The That is, when the selection signal 146 to the multiplexer 244 is “1”, the thread 144 indicated by the thread ID of the hard real-time thread table 222 pointed to by the pointer 242 is selected and output as the thread number 201. At the same time, the pointer 242 is incremented by the incrementer 247.

  In other cases (when both the hard real-time bit 224 and the real-time bit 225 are “0”), the thread in the non-real-time thread table 221 is selected. That is, when the selection signal 146 to the multiplexer 244 is “0”, the thread 145 indicated by the thread ID of the non-real-time thread table 221 pointed to by the pointer 243 is selected and output as the thread number 201. At the same time, the pointer 243 is incremented by the incrementer 248.

  Next, a thread scheduling method executed by the thread scheduler when the frequency control signal 121 is “1” (maximum processor operating frequency) will be described. In this case, since the maximum processor operating frequency is twice the reference processor operating frequency, the thread selection signal generation circuit 240 validates the selection signal for one cycle every two cycles.

  In this example, since the number of elements in the hard real-time thread table 222 is 8, eight cycles are output as “1” indicating validity, and the next eight cycles are invalid as selection signal 141. “0” is output. As a result, the selection signal 141 can be validated for 8 cycles out of 16 cycles.

  Further, when the selection signal 141 is “1”, it is the same as the case where the frequency control signal 121 is “0” (reference processor operating frequency), so the thread scheduling method when the selection signal 141 is “0” will be described. To do.

  First, since the thread selection signal generation circuit 240 outputs “0” as the selection signal 141, a thread in the hard real-time thread table 222 is selected only when the hard real-time bit 224 is “1”. That is, when the selection signal 146 to the multiplexer 244 is “1”, the thread 144 indicated by the thread ID of the hard real-time thread table 222 pointed to by the pointer 242 is selected and output as the thread number 201. At the same time, the pointer 242 is incremented by the incrementer 247.

  In other cases (when the hard real-time bit 224 is “0”), a thread in the non-real-time thread table 221 is selected. That is, when the selection signal 146 to the multiplexer 244 is “0”, the thread 145 indicated by the thread ID of the non-real-time thread table 221 pointed to by the pointer 243 is selected and output as the thread number 201. At the same time, the pointer 243 is incremented by the incrementer 248.

  FIG. 7 is a diagram illustrating a timing chart of a thread schedule in another embodiment. When the frequency control signal (FREQCTRL) 121 is “1”, a real-time thread in the table 222 pointed to by the pointer (HRTP) 242 is scheduled for the first eight cycles. However, in the next 8 cycles, the non-real time thread is scheduled instead of the real time thread (0 → N) in order to make the period at which the real time thread is scheduled constant. When the frequency control signal (FREQCTRL) 121 is “0”, a real-time thread in the table 222 is always scheduled.

  As described above, when the operating frequency of the processor becomes n times the reference frequency, the selection signal is validated once out of n times. However, by providing a circuit that disables the selection signal n-1 out of n times, the processing performance of a specific thread is kept constant even when the operating frequency of the processor changes. As a result, as shown in FIG. 7, the thread 0 can be scheduled at a constant period regardless of the operating frequency of the processor. That is, a certain performance can be maintained.

  Even if the present invention is applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), it is applied to an apparatus (for example, a copier, a facsimile machine, etc.) composed of a single device. It may be applied.

  In addition, a recording medium in which a program code of software for realizing the functions of the above-described embodiments is recorded is supplied to the system or apparatus, and the computer (CPU or MPU) of the system or apparatus stores the program code stored in the recording medium. Read and execute. It goes without saying that the object of the present invention can also be achieved by this.

  In this case, the program code itself read from the recording medium realizes the functions of the above-described embodiment, and the recording medium storing the program code constitutes the present invention.

  As a recording medium for supplying the program code, for example, a floppy (registered trademark) disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like is used. be able to.

  In addition, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also the following cases are included. That is, when the OS (operating system) running on the computer performs part or all of the actual processing based on the instruction of the program code, and the functions of the above-described embodiments are realized by the processing.

  Further, the program code read from the recording medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer. After that, based on the instruction of the program code, the CPU of the function expansion board or function expansion unit performs part or all of the actual processing, and the function of the above-described embodiment is realized by the processing. Needless to say.

It is a figure which shows an example of a structure of the multithread processor system in this embodiment. FIG. 6 is a diagram for explaining the operation of each block and a typical signal connection relationship in the multi-thread processor 101. 2 is a diagram illustrating an example of a configuration of a thread scheduler 110 in a multi-thread processor 101. FIG. It is a figure which shows the result of the thread | schedule in this embodiment. It is a figure which shows an example of a structure of the thread scheduler in other embodiment. 3 is a diagram illustrating an example of a configuration of a thread selection signal generation circuit 240. FIG. It is a figure which shows the result of the thread schedule in other embodiment.

Explanation of symbols

100 Clock generation circuit (CLKGEN)
101 Multi-thread processor 110 Thread scheduler (SCHED)
115 Control circuit (CTRL)
116 Data path 120 Processor clock (CLK)
121 Frequency control signal (FREQCTRL)
220 Hard real-time thread table 221 Non-real-time thread table 222 Hard real-time thread table 223 Thread 224 Thread schedule information

Claims (6)

A processor system including a clock generation circuit and a multi-thread processor,
The clock generation circuit includes a generation unit that receives a clock frequency control signal from the multi-thread processor and generates a processor operating frequency whose frequency changes based on the clock frequency control signal.
2. The processor system according to claim 1, wherein the multi-thread processor has scheduling means for scheduling one or more threads at a constant period regardless of the processor operating frequency based on the clock frequency control signal. The scheduling means has two or more thread schedule tables that hold schedule timings of threads to be scheduled at a constant period,
2. The processor system according to claim 1, wherein each thread schedule table is switched by the clock frequency control signal to schedule one or more threads at a constant period regardless of the processor operating frequency.   The scheduling means schedules a thread to be scheduled once every n times when the processor operating frequency becomes n times the reference, and schedules n-1 times every n times. 2. The processor system according to claim 1, wherein no scheduling of power threads is performed. A multi-thread processor that outputs a clock frequency control signal to a clock generation circuit and inputs a processor operating frequency generated by the clock generation circuit;
A multi-thread processor comprising scheduling means for scheduling at least one thread at a constant period regardless of the processor operating frequency based on the clock frequency control signal. The scheduling means has two or more thread schedule tables that hold schedule timings of threads to be scheduled at a constant period,
5. The multi-thread processor according to claim 4, wherein each thread schedule table is switched by the clock frequency control signal to schedule one or more threads at a constant period regardless of the processor operating frequency.   The scheduling means schedules a thread to be scheduled once every n times when the processor operating frequency becomes n times the reference, and schedules n-1 times every n times. 5. The multi-thread processor according to claim 4, wherein scheduling of power threads is not performed.

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