JP2003233496A - Microprocessor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a versatile microprocessor in which an executing mode of an instruction code can be selected corresponding to an application. <P>SOLUTION: In an F/F circuit 400, a fetched instruction code is retained. When in a full instruction code execution mode, a specified bit of the full instruction code is referred to, the content of an execution mode setting register 424 is changed and the execution mode is changed to a reduced instruction execution mode. Furthermore, the execution mode change instruction is detected by an execution mode change instruction detecting circuit 422 in the reduced instruction execution mode, the content of the execution mode setting register 424 is changed and the execution mode is changed to the full instruction code execution mode. Therefore, the execution mode can be selected according to the application and the versatility of the microprocessor is improved. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a processor for fetching an instruction code having a bit length smaller than the bit length of an instruction to be executed from an instruction memory and performing processing.

[0002]

2. Description of the Related Art In recent years, microprocessors have been widely used, and there is an increasing demand for more versatile microprocessors. One method for increasing the versatility of the microprocessor is to increase the types of instruction codes so that one instruction code can execute complicated processing.

FIG. 7 is a block diagram showing an example of a schematic configuration of a general microprocessor. The microprocessor 1 includes an instruction decoding unit 2 that decodes an instruction code fetched from an instruction memory 41, and a program control unit (PCU) 31 that controls a PC (program counter) according to the decoding result of the instruction decoding unit 2.
A data operation unit (DAU) 32 that performs data operation according to the instruction decode result by the instruction decode unit 2, and an address operation unit (AAU) 33 that performs address operation according to the instruction decode result by the instruction decode unit 2, A register operation control unit 34 that controls the operation of the internal register according to the instruction decoding result by the instruction decoding unit 2 and a memory control unit (MCU) 35 that controls the data memory 51 according to the decoding result by the instruction decoding unit 2. Including.

In addition, the data operation unit 32 includes a multiplier (MP
Y) 321 and ALU (Arithmetic and Logic Unit) 3
22 and a shifter (SFT) 323.

The operation of the microprocessor shown in FIG. 7 will be described below. For simplicity, the instruction fetch,
The description will be made assuming that the processing is performed by a three-stage pipeline of instruction decoding and instruction execution. It should be noted that the notation method of values in this specification follows the grammar of the Verilog-HDL language widely used as a hardware description language.

First, in the instruction fetch stage, the instruction decoding unit 2 fetches an instruction code from the instruction memory 41 via the data bus 42. At this time, the program control unit 31 determines the address where the instruction code to be fetched via the address bus 43 is stored in the instruction memory 4
1 and also outputs an I-MEM signal 44 for controlling the instruction memory 41.

Next, in the instruction decoding stage, by decoding the instruction code fetched by the instruction decoding unit 2, a control signal P21 for controlling the program control unit 31 and a control for controlling the data operation unit 32. A signal D22, a control signal A23 for controlling the address operation unit 33, a control signal R24 for controlling the register operation control unit 34, and a control signal M25 for controlling the memory control unit 35 are generated.

Finally, in the instruction execution stage, the program control unit 31, the data operation unit 32, the address operation unit 33, the register operation control unit 34, and the memory control unit 35.
However, the operation is performed according to the decoding result by the instruction decoding unit 2, and the data is processed. At this time, the program control unit 31 calculates and generates an address necessary for fetching an instruction code from the instruction memory 41, and at the same time issues an I-MEM signal 44 for controlling the fetching of the instruction code from the instruction memory 41. Output to the memory 41.

Further, the address calculation unit 33 calculates an address necessary for storing and reading a value in the middle of calculation used in the data calculation process by the data calculation unit 32 and a calculation result, and stores it in the data memory 51. Output. The memory control unit 35 also generates and outputs a D-MEM signal 54 that controls access to the data memory 51. Further, the register operation control unit 34 controls a register (not shown) that temporarily holds the value written in or read out from the data memory 51 via the data bus 52.

FIG. 8 is a block diagram for explaining the structure of the instruction decoding unit 2 shown in FIG. 7 in more detail. The instruction decoding unit 2 holds a m-bit flip-flop (hereinafter abbreviated as F / F circuit) 10 that holds a m-bit instruction code fetched from the instruction memory 41.
0, a decode circuit P121 for decoding the instruction code P111 for controlling the program control unit 31, a decode circuit D122 for decoding the instruction code D112 for controlling the data operation unit 32, and an address operation unit 33. For decoding the instruction code A113 for decoding, the decoding circuit R124 for decoding the instruction code R114 for controlling the register operation control unit 34, and the decoding for decoding the instruction code M115 for controlling the memory control unit 35. Circuit M1
25, an F / F circuit 141 that holds the decode signal P131 output from the decode circuit P121, an F / F circuit 142 that holds the decode signal D132 output from the decode circuit D122, and an output from the decode circuit A123. An F / F circuit 143 holding the decode signal A133, an F / F circuit 144 holding the decode signal R134 output from the decode circuit R124, and an F / F circuit holding the decode signal M135 output from the decode circuit M125. 145 and. The instruction code length m is an arbitrary positive integer.

The m-bit instruction code has an instruction field 101 for controlling the program control section 31 and an instruction field 102 for controlling the data operation section 32.
An instruction field 103 for controlling the address operation unit 33, an instruction field 104 for controlling the register operation control unit 34, and an instruction field 105 for controlling the memory control unit 35. The values of the instruction fields 101 to 105 are the instruction codes P111 to
The M115 is output to the decoding circuits P121 to M125.

When the F / F circuit 100 fetches the m-bit instruction code fetched from the instruction memory 41, the F / F circuit 100 holds this instruction code for the next one cycle (instruction decode stage). The instruction codes P111 to M115 included in this instruction code are respectively decoded by the decode circuit P121.
~ Output to M125.

Decode circuits P121 to M125 decode the instruction codes P111 to M115, respectively, and decode the decoded signals P131 to M135 from the F / F circuits 141 to 141.
Output to 145. The F / F circuits 141 to 145 respectively hold the decode signals P131 to M135, and as the control signals P21 to M25, the program control unit 31, the data operation unit 32, the address operation unit 33, the register operation control unit 34, and the memory control unit 35. Output to.

[0014]

For example, when an attempt is made to realize a microprocessor having an instruction code length of 16 bits, the instruction length of 16 bits causes various instruction sets to be determined. Restrictions will be added. That is, even if the arithmetic operation can be executed in terms of hardware, the microprocessor cannot execute the arithmetic operation unless the arithmetic operation is defined in the instruction set. for that reason,
Depending on the application program, the original performance of the microprocessor cannot be fully exerted.

On the contrary, the instruction code length is, for example, 32.
If the number of bits is set, the size of the required instruction memory will be doubled, and in addition, instructions that are almost unnecessary will be defined in the instruction set.

As one method for solving such a problem, an instruction code having an instruction code length reduced from the original instruction code for a part of the implemented instructions (hereinafter referred to as a reduced instruction code). , A reduced instruction code execution mode capable of executing the reduced instruction code and a full instruction code execution mode capable of executing the original non-reduced instruction code have been developed. ing.

However, since the instructions that this microprocessor can execute in the reduced instruction code execution mode are fixed in hardware, many instruction codes must be executed in the full instruction code execution mode depending on the application. There was a problem that almost no effect was obtained.

The present invention has been made to solve the above problems, and a first object thereof is to provide a microprocessor capable of reducing the size of an instruction memory.

A second object is to provide a versatile microprocessor capable of selecting an instruction code execution mode according to an application.

A third object is to provide a microprocessor capable of changing the execution mode of the instruction code at high speed.

[0021]

According to a first aspect of the present invention, a microprocessor has a holding circuit for holding a fetched instruction code, and a full instruction code execution mode for executing an instruction held by the holding circuit. Mode and reduced instruction code execution mode, an execution mode changing circuit, an instruction set sub-table that stores an arbitrary full instruction code corresponding to the reduced instruction code in the reduced instruction code execution mode, and a holding circuit And an instruction execution circuit for selectively executing one of the full instruction code stored in the instruction set sub-table and the full instruction code stored in the instruction set sub-table.

Since any full instruction code corresponding to the reduced instruction code is stored in the instruction set sub-table, the instruction execution circuit can execute the full instruction code according to the reduced instruction code fetched from the instruction memory. It is possible to reduce the size of the instruction memory. Also,
The execution mode change circuit changes the execution mode to either the full instruction code execution mode or the reduced instruction code execution mode, so the execution mode can be selected according to the application and the versatility of the microprocessor can be improved. Becomes

A microprocessor according to claim 2 is
2. The microprocessor according to claim 1, wherein the execution mode changing circuit is in the full instruction code execution mode,
The execution mode is changed to the reduced instruction code execution mode by referring to the predetermined bit of the full instruction code held in the holding circuit, and the reduced instruction code held in the holding circuit is set to the predetermined instruction in the reduced instruction code execution mode. In this case, the execution mode is changed to the full instruction code execution mode.

Therefore, the execution mode can be changed according to the characteristics of the full instruction code having a long instruction code length and the reduced instruction code having a short instruction code length.

A microprocessor according to claim 3 is
3. The microprocessor according to claim 2, wherein the execution mode change circuit is in the reduced instruction code execution mode,
Whether or not the reduced instruction code on the lower side of the plurality of reduced instruction codes held in the holding circuit is a predetermined instruction is determined by the decode stage of the reduced instruction code on the lower side to change the execution mode.

Therefore, the reduced instruction code on the lower side of the plurality of reduced instruction codes is not executed, the apparent execution cycle becomes 0, and the processing speed can be improved.

The microprocessor according to claim 4 is
The microprocessor according to any one of claims 1 to 3, wherein the microprocessor includes a plurality of instruction set sub-tables and further stores information on which of the plurality of instruction set sub-tables is selected. When,
A selector for switching the outputs of the plurality of instruction set sub-tables according to the information stored in the register.

Therefore, an arbitrary instruction set sub-table can be selected from a plurality of instruction set sub-tables, and a microprocessor with high versatility can be provided.

A microprocessor according to claim 5 is
A microprocessor for executing an instruction code including a plurality of fields indicating the processing content to be executed, each of a holding circuit for holding a fetched instruction code, and a plurality of fields included in an instruction held in the holding circuit And a plurality of instruction set sub-tables for storing arbitrary full instruction codes corresponding to the reduced instruction codes and a plurality of decoding circuits for decoding the full instruction codes output from the plurality of instruction set sub-tables. When,
A plurality of instruction execution circuits that execute a full instruction code according to the decoding results of the plurality of decoding circuits.

Since the plurality of instruction set sub-tables are provided corresponding to each of the plurality of fields included in the instruction held in the holding circuit, the instruction set sub-table corresponds to the reduced instruction code according to the function of the field. You will be able to set the full instruction code.

A microprocessor according to claim 6 is
A microprocessor that executes an instruction code that includes a plurality of fields that indicate the processing content to be executed, and that includes a holding circuit that holds the fetched instruction code and a plurality of fields that are included in the instruction held in the holding circuit. One or more instruction set sub-tables provided corresponding to one or more fields of the above and storing arbitrary full instruction codes corresponding to reduced instruction codes, and instruction set sub-tables provided corresponding to one or more fields A first decoding circuit for decoding the full instruction code output from the table;
A second decoding circuit for directly decoding the full instruction code corresponding to fields other than the above fields;
A plurality of instruction execution circuits that execute a full instruction code according to the decoding results by the first and second decoding circuits.

Therefore, even when one instruction includes an instruction code with many types of processing and an instruction code with few types of processing, it is possible to configure a microprocessor suitable for it.

A microprocessor according to claim 7 is
The microprocessor according to any one of claims 1 to 6, wherein the contents of the instruction set sub-table are changed by an immediate load instruction.

Therefore, it is possible to dynamically change the contents of the instruction set sub-table even when the microprocessor is executing the instruction code.

The microprocessor according to claim 8 is
8. The microprocessor according to claim 7, wherein the immediate load instruction is set in any of the instruction set sub-tables immediately after the reset of the microprocessor.

Therefore, the contents of the instruction set sub-table can be easily set immediately after the reset of the microprocessor.

[0037]

(First Embodiment) A schematic configuration of a microprocessor according to a first embodiment of the present invention is shown in FIG.
Compared with the general configuration of the general microprocessor shown in FIG. 1, the only difference is the configuration and function of the instruction decoding unit. Therefore, detailed description of overlapping configurations and functions will not be repeated. The reference numeral of the instruction decoding unit in this embodiment will be described as 3.

FIG. 1 is a diagram for explaining an instruction set and an instruction set sub-table of the microprocessor according to the first embodiment of the present invention. Instruction set 210
Is a full instruction set composed of all the instruction codes that can be executed by the microprocessor in the present embodiment, and each instruction code has an instruction code length of m bits. Therefore, the instruction (0) to the instruction (2 ^m −
It is composed of 2 ^m kinds of instruction codes of 1). Note that m is an arbitrary positive integer.

The instruction set sub-table 200 stores an n-bit index 201 that designates an instruction code arbitrarily selected by the user from the instruction set 210, and an m-bit instruction code designated by the index 201. Region 202. The index 201 of the instruction set sub-table 200 is stored in the instruction memory 41 as a reduced instruction code to be fetched by the microprocessor. The address of the instruction set sub-table 200 directly represents the index. Note that n
Is any positive integer less than m.

When the user creates a program using all the instruction codes included in the instruction set 210, the program is subjected to static analysis and dynamic analysis using a simulator or the like. Then, the user selects an instruction that is dynamically and / or statically determined to be frequently used and useful for executing the program.

Some or all of the selected full instruction codes are set in the area 202 of the instruction set sub-table 200. Since the full instruction code set in this area 202 has a one-to-one correspondence with the index 201, by designating the index 201, the m-bit full instruction code desired by the user is set to n.
It can be specified by a bit instruction code. For example, if "3" is specified as the reduced instruction code, the instruction (37) corresponding to the index is selected, and this instruction (37) can be fetched from the instruction set sub-table 200. As described above, m bits have been conventionally required to specify a full instruction code, but it is possible to specify a full instruction code with n bits which are smaller than m bits.

The instruction set sub-table 200 is composed of registers and can write a desired full instruction code by using an immediate load instruction. Note that it is not necessary to set the immediate load instruction in the instruction set sub-table 200, and it is assumed that the immediate load instruction is set in any of the instruction set sub-tables 200 and can be used immediately after the microprocessor is reset.

FIG. 2 is a diagram for explaining a reduced instruction code in the horizontal microinstruction architecture.
The full instruction code 220 is an m-bit instruction code that constitutes the instruction set 210 of FIG. 1, and includes an m1-bit field (221) and an m2-bit field (2
22) and. The field (221) and the field (222) are fields for designating a predetermined function. It should be noted that although only two fields are shown in FIG. 2, three or more fields may be included.

The instruction reduction code 230 is an n-bit reduction instruction code obtained by reducing the full instruction code 220 of the horizontal microinstruction architecture, and corresponds to the index 201 of the instruction set sub-table 200 of FIG. The reduced instruction code 230 includes an n1 bit reduced field (231) corresponding to the field (221) of the full instruction code 220 and an n2 bit reduced field (232) corresponding to the field (222) of the full instruction code 220. including.

FIG. 3 is a block diagram showing a schematic structure of the instruction decoding unit in the first embodiment of the present invention. The instruction decoding unit 3 includes an n-bit F / F circuit 300 that holds a reduced instruction code having an instruction code length of n bits fetched from the instruction memory 341, and a program control unit 31.
Instruction set sub-tables P-1 and P-2 (51 provided with reduced instruction code P'510 for controlling
1, 512) and the output of the instruction set sub-tables P-1 and P-2 (511, 512).
02 and a sub-table selection control register Creg-PCU50 holding information for switching the selector 502.
0, and an instruction set sub-table D- to which a reduced instruction code D'530 for controlling the data operation unit 32 is given.
1 to D-4 (531 to 534), a selector 522 that switches the output of the instruction set subtables D-1 to D-4 (531 to 534), and a subtable selection control that holds information for switching the selector 522. Register Creg
-DAU 520 and instruction set sub-tables A-1 and A-2 (551, 552) to which a reduced instruction code A'550 for controlling the address calculation unit 33 is given,
Instruction set sub-tables A-1 and A-2 (551,
552) the selector 542 for switching the output, the sub-table selection control register Creg-AAU 540 for holding the information for switching the selector 542, and the reduced instruction code R′57 for controlling the register operation control unit 34.
Instruction set sub-tables R-1 and R given 0
-2 (571, 572) and instruction set subtable R
-1 and R-2 (571, 572) outputs the selector 562 and a sub-table selection control register Creg- that holds information for switching the selector 562.
RCU 560, instruction set sub-tables M-1 to M-3 (591 to 593) to which reduced instruction code M'590 for controlling the memory control unit 35 is given, and instruction set sub-tables M-1 to M-3 A selector 582 for switching the output of (591 to 593), a sub-table selection control register Creg-MCU 580 for holding information for switching the selector 582, and a decoding circuit for decoding an instruction code P for controlling the program control unit 31. P121 and a decoding circuit D122 for decoding an instruction code D112 for controlling the data operation unit 32.
And an instruction code A for controlling the address calculation unit 33
A decode circuit A123 for decoding 113 and an instruction code R114 for controlling the register operation control unit 34
A decoding circuit R124 for decoding the memory controller 35, a decoding circuit M125 for decoding an instruction code M115 for controlling the memory control unit 35, an F / F circuit 141 for holding a decoding signal P131 output from the decoding circuit P121, and a decoding circuit. An F / F circuit 142 that holds the decode signal D132 output from D122, an F / F circuit 143 that holds the decode signal A133 output from the decode circuit A123, and a decode signal R134 output from the decode circuit R124 And an F / F circuit 145 for holding the decode signal M135 output from the decode circuit M125.

The n-bit reduced instruction code is a reduced instruction field 301 for controlling the program control unit 31.
A reduced instruction field 302 for controlling the data operation unit 32, a reduced instruction field 303 for controlling the address operation unit 33, a reduced instruction field 304 for controlling the register operation control unit 34, and a memory control. A reduced instruction field 305 for controlling the section 35.

The value of the reduction instruction field 301 is output to the instruction set sub-tables P-1 and P-2 (511, 512) as the reduction instruction code P '. The value of the reduction instruction field 302 is the reduction instruction code D ′, and the instruction set sub-tables D-1 to D-4 (531 to 534)
Is output to. The value of the reduction instruction field 303 is output as the reduction instruction code A ′ to the instruction set subtables A-1 and A-2 (551, 552). The value of the reduction instruction field 304 is the reduction instruction code R ′, and the instruction set sub-tables R-1 and R-2 (571, 5
72). The value of the reduction instruction field 305 is the reduction instruction code M ′, and the instruction set sub-table M
It is output to -1 to M-3 (591 to 593).

Instruction set sub-tables P-1 and P-
2 (511, 512) and D-1 to D-4 (531 to 5)
34) and A-1 and A-2 (551, 552),
R-1 and R-2 (571, 572) and M-1 to M
-3 (591 to 593) has the same configuration as the instruction set sub-table 200 shown in FIG.
When a reduced instruction code (index) is given, a full instruction code corresponding to it is output.

Instruction set sub-tables P-1 and P-
2 (511, 512) outputs the full instruction code P corresponding to the reduced instruction code P ′. The value held in the sub table selection control register Creg-PCU500 is 1 '.
If it is b0, the selector 502 selects the output of the instruction set sub-table P-1 (511). If the value held in the sub table selection control register Creg-PCU 500 is 1'b1, the selector 502 selects the output of the instruction set sub table P-2 (512). There are multiple instruction set sub-tables because the full instruction code used depends on the application.
This is because the user can select any instruction set sub-table.

Instruction set sub-tables D-1 to D-4
(531 to 534) output the full instruction code D corresponding to the reduced instruction code D ′. The value held in the sub table selection control register Creg-DAU520 is 2'b.
If it is 00, the selector 522 selects the output of the instruction set sub-table D-1 (531). If the value held in the sub table selection control register Creg-DAU 520 is 2′b01, the selector 522 selects the output of the instruction set sub table D-2 (532). If the value held in the sub table selection control register Creg-DAU 520 is 2′b10, the selector 522 selects the output of the instruction set sub table D-3 (533). Sub-table selection control register Creg-DAU5
If the value held in 20 is 2'b11, the selector 5
22 selects the output of the instruction set sub-table D-4 (534).

Instruction set sub-tables A-1 and A-
2 (551, 552) outputs the full instruction code A corresponding to the reduced instruction code A ′. The value held in the sub table selection control register Creg-AAU540 is 1 '.
If it is b0, the selector 542 selects the output of the instruction set sub-table A-1 (551). If the value held in the sub table selection control register Creg-AAU 540 is 1'b1, the selector 542 selects the output of the instruction set sub table A-2 (552).

Instruction set sub-tables R-1 and R-
2 (571, 572) outputs the full instruction code R corresponding to the reduced instruction code R ′. The value held in the sub table selection control register Creg-RCU 560 is 1 '.
If it is b0, the selector 562 selects the output of the instruction set sub-table R-1 (571). If the value held in the sub table selection control register Creg-RCU 560 is 1′b1, the selector 562 selects the output of the instruction set sub table R-2 (572).

Instruction set sub-tables M-1 to M-3
(591-593) outputs the full instruction code M corresponding to the reduced instruction code M ′. The value held in the sub table selection control register Creg-MCU 580 is 2'b.
If it is 00, the selector 582 selects the output of the instruction set sub-table M-1 (591). If the value held in the sub table selection control register Creg-MCU 580 is 2′b01, the selector 582 selects the output of the instruction set sub table M-2 (592). If the value held in the sub table selection control register Creg-MCU 580 is 2'b10, the selector 582 selects the output of the instruction set sub table M-3 (593).

The instruction code length of the instruction code P111 is m1, the instruction code length of the instruction code D112 is m2, the instruction code length of the instruction code A113 is m3, and the instruction code R.
When the instruction code length of 114 is m4 and the instruction code length of the instruction code M115 is m5, m = m1 + m2 + m3 + m
It becomes 4 + m5.

Subtable selection control register Creg-
PCU500, Creg-DAU520, Creg-A
AU540, Creg-RCU560 and Creg-
The MCU 580 is a register that can be set during program execution.

Decode circuits P121 to M125 decode instruction codes P111 to M115, respectively, and decode their decode signals P131 to M135 in F / F circuits 141 to 141.
Output to 145. The F / F circuits 141 to 145 respectively hold the decode signals P131 to M135, and as the control signals P21 to M25, the program control unit 31, the data operation unit 32, the address operation unit 33, the register operation control unit 34, and the memory control unit 35. Output to.

As described above, according to the microprocessor of the present embodiment, the instruction set sub-table 200 converts the reduced instruction code into the full instruction code and outputs the full instruction code. The full instruction code can be specified by the instruction code length which is smaller than the instruction code length of the instruction code, and the size of the instruction memory 341 can be reduced. Further, the number of bits of the data bus between the microprocessor and the instruction memory can be reduced, and the mounting area can be reduced and the number of wiring patterns can be reduced.

Further, since the user can select any full instruction code and set it in the instruction set sub-table 200, the full instruction code corresponding to the application can be selected, and a microprocessor with high versatility can be provided. Became possible. Further, since one of the plurality of instruction set sub-tables can be selected by the sub-table selection control register, the instruction set sub-table corresponding to the application can be selected, and a microprocessor with high versatility can be realized. It is now possible to provide.

Furthermore, since an instruction set sub-table is provided corresponding to each of a plurality of fields included in the instruction stored in the F / F circuit 300, one instruction stored in the F / F circuit 300 is stored. Compared with the case where one instruction set sub-table is provided correspondingly, it becomes possible to reduce the total capacity of the instruction set sub-table. For example, if one 32-bit instruction is reduced to 16 bits, the capacity of the table is 2 ¹⁶ × 32 bits. On the other hand, when 32 bits are divided into two fields of 16 bits each and the 16-bit instruction code is reduced to 8 bits as in the present embodiment, the capacity of the table is 2 ⁸ × 16 + 2 ⁸ × 16 = 2 ⁸ ×
It will be 32 bits.

(Second Embodiment) FIG. 4 is a block diagram showing a schematic structure of an instruction decoding unit of a microprocessor according to a second embodiment of the present invention. This instruction decoding unit is different from the instruction decoding unit according to the first embodiment shown in FIG. 3 in instruction set sub-tables P-1, P-2, R.
-1, R-2, M-1, M-2 and M-3 (511,
512, 571, 572, 591 to 593) and the sub-table selection control registers Creg-PCU, Creg-
RCU and Creg-MCU (500, 560, 58
0) and the selectors 502, 562 and 582 are deleted. Therefore, detailed description of overlapping configurations and functions will not be repeated.

The n-bit F / F circuit 300 includes five fields 301 to 305, but some instruction codes corresponding to these fields do not have many kinds of processing. In the present embodiment, the values of the fields (instruction codes P ′, R ′, M ′) corresponding to the instruction codes that do not need to be reduced are used as they are in the decoding circuit 12.
1, 124 and 125, and only the instruction codes D and A are reduced.

Similar to the first embodiment, the instruction set sub-tables 531 to 534, 551 and 552 are composed of registers, and a desired full instruction code can be written by using an immediate load instruction. Note that it is not necessary to set the immediate load instruction in the instruction set sub-table 200, and it is assumed that the immediate load instruction is set in any of the instruction set sub-tables 200 and can be used immediately after the microprocessor is reset.

Although FIG. 4 shows the case where there are two fields in which the reduced instruction code is stored, the number of fields in which the reduced instruction code is stored may be one or three or more. It may be. Further, although a plurality of instruction set sub-tables are provided corresponding to each reduced instruction code, it goes without saying that only one instruction set sub-table may be provided for each.

As described above, according to the microprocessor of the present embodiment, the reduced instruction code and the instruction code that is not reduced are stored in the fields 301 to 305 included in the F / F circuit 300. The reduced instruction code is converted into a full instruction code by the instruction set sub-table and then decoded, and the instruction code that is not reduced is decoded as it is. Therefore, even when one instruction fetched from the instruction memory 341 includes an instruction code with many types of processing and an instruction code with few types of processing, a microprocessor suitable for it is configured. It has become possible.

(Third Embodiment) A schematic configuration of a microprocessor according to a third embodiment of the present invention is different from that of a general microprocessor shown in FIG. 7 in the configuration and function of an instruction decoding unit. Only the points differ.
Therefore, detailed description of overlapping configurations and functions will not be repeated. The reference numeral of the instruction decoding unit in the present embodiment will be described as 4.

The microprocessor according to the third embodiment of the present invention operates while switching the execution mode between the reduced instruction code execution mode and the full instruction code execution mode. In this embodiment, the case where the microprocessor is not the horizontal microinstruction architecture will be described, but the present invention can be applied to the horizontal microinstruction architecture shown in FIG. 3 or 4.

FIG. 5 is a block diagram showing a schematic configuration of a microprocessor according to the third embodiment of the present invention.
The microprocessor 1 includes an instruction decoding unit 4 that decodes the instruction fetched from the instruction memory 441, and an instruction execution unit 5 that executes the instruction according to the decoding result of the instruction decoding unit 4.

Further, the instruction decoding unit 4 includes the instruction memory 4
A full instruction code with an instruction code length of m bits fetched from 41 or two reduced instruction codes (sub instruction code) with an instruction code length of n (m = 2n) bits are held in m
Bit F / F circuit 400 and two reduced instruction codes A
A selector 413 for selecting and outputting any one of 411 and B412; an instruction set sub-table 416 to which the reduced instruction code 415 selected by the selector 413 is given; a full instruction code 420 held in the F / F circuit 400; A selector 421 that selects and outputs any one of the full instruction codes 417 output from the instruction set sub-table 416, an execution mode change instruction detection circuit 422 that detects an execution mode change instruction, and an execution mode in which the execution mode is set. The setting register 424, the decode circuit 431 that decodes the full instruction code 430 output from the selector 421, and the F / F circuit 43 that holds the decode signal 432 output from the decode circuit 431.
Including 3 and.

The instruction decoding unit 4 further receives the signal 423 output from the execution mode change instruction detection circuit 422 and the F /
Predetermined 1 of the control signal 434 output from the F circuit 433
OR gate 453 that calculates the logical sum with bit 452
And a selector 451. The selector 451 performs an OR when the value of the execution mode setting register 424 is 1′b0.
When the output 454 of the gate 453 is selected and the value of the execution mode setting register 424 is 1′b1, the F / F circuit 400
The predetermined bit 450 is output.

The instruction decoding unit 4 fetches the m-bit instruction code from the instruction memory 441 and fetches it from the F / F circuit 40.
Hold at 0. In the reduced instruction code execution mode, F
Of the m-bit instruction codes held in the / F circuit 400, the instruction code stored in the upper n-bit area 401 is processed as an n-bit reduced instruction code A411, and the lower n-bit area 402 is processed. The instruction code stored in is processed as an n-bit reduced instruction code B412. Therefore, in the reduced instruction code execution mode, the instruction decoding unit 4 divides two reduced instruction codes into one instruction.
It will be fetched every time.

In the full instruction code execution mode, the m-bit instruction code held in the F / F circuit 400 is processed as an m-bit full instruction code. Full instruction code is always aligned in instruction memory 4
In the full instruction code execution mode, the instruction decoding unit 4 allocates one instruction of the full instruction code to one.
It will be fetched in cycles.

A predetermined 1 bit 450 of the full instruction code held in the F / F circuit 400 corresponds to a bit indicating whether to change from the full instruction code execution mode to the reduced instruction code execution mode. Further, the control signal 452, which is one bit in the control signal 434 composed of a plurality of bits output from the F / F circuit 433, is a reduced instruction code stored in the upper area 401 as a result of decoding Is a signal indicating that.

Program counter 414 of the processor
Counts the address of the instruction to be executed. The predetermined one bit in the address can identify the reduced instruction code on the upper side and the reduced instruction code on the lower side of the instruction. For example, if one address is assigned to 8-bit data and m = 32, the identification can be made by the second least significant bit of the address.

Here, assuming that m = 32, the program counter 414 increments by 2 in the reduced instruction code execution mode and increments by 4 in the full instruction code execution mode.

The selector 413 has the program counter 4
According to the value of bit 30 of 14 (the second least significant bit), one of the reduced instruction codes A411 and B412 is selected and output. When the bit 30 is "0", the reduced instruction code A411 is selected, and when the bit 30 is "1", the reduced instruction code B412 is selected.

In the reduced instruction code execution mode, the reduced instruction code A held in the upper area 401 is executed before the reduced instruction code B held in the lower area 402. That is, the reduced instruction code A held in the upper area 401 of the F / F circuit 400 is converted into a full instruction code by the instruction set sub-table 416 in one cycle, and decoded by the decoding circuit 431 (decoding stage), Decode signal 43 in the next 1 cycle
Based on 2, the operation or processing designated by the instruction in the upper area 401 is executed by the instruction execution unit 3 (execution stage).

Further, while the reduced instruction code A is held in the upper area 401, at the same time as the lower field 402.
The reduced instruction code B held in the
The same cycle (1
Cycle), it is converted into a full instruction code by the instruction set sub-table 416, and is decoded by the decode circuit 431 (decode stage). In the next cycle, the operation specified by the instruction in the lower area 402 based on the decode signal 432 or The processing is executed by the instruction execution unit 3 (execution stage).

The instruction set sub-table 416 receives the reduced instruction code (index) 415 from the selector 413 and outputs a full instruction code corresponding to the reduced instruction code. This instruction set sub-table 416 is shown in FIG.
The instruction set sub-table 200 shown in FIG.

In the reduced instruction code execution mode, 1'b0 is set in the execution mode setting register 424, and the selector 421 selects and outputs the full instruction code 417 output from the instruction set sub-table 416. The decoding circuit 431 decodes the full instruction code 430 output from the selector 421. The F / F circuit 433 holds the decode signal 432 output from the decode circuit 431 and outputs it as a control signal 434.

In the full instruction code execution mode, 1'b1 is set in the execution mode setting register 424, and the selector 421 selects and outputs the full instruction code 420 output from the F / F circuit 400. The decoding circuit 431 decodes the full instruction code 430 output from the selector 421. The F / F circuit 433 holds the decode signal 432 output from the decode circuit 431 and outputs it as a control signal 434.

A case where the execution mode is changed from the full instruction code execution mode to the reduced instruction code execution mode will be described. Since the instruction code length of the full instruction code is long and has a margin, whether the execution mode of the next instruction is the full instruction code execution mode or the reduced instruction code execution mode along with a field for designating a predetermined operation or processing. 1 bit 450 indicating is provided.

The full instruction code held in F / F circuit 400 is decoded by decode circuit 431 in the decode stage, and instruction execution unit 5 performs the operation or processing designated by the full instruction code in the execution stage.

The setting change of the execution mode setting register 424 is decided at the decode stage of the full instruction code.
When the bit 450 of the full instruction code is "1", it is specified that the next instruction is executed with the reduced instruction code, and the setting change of the execution mode setting register 424 is determined at the execution stage of the full instruction code. When the cycle of the full instruction code execution stage is started, the value of the execution mode setting register 424 is changed to 1′b0, and F
The contents of the / F circuit 400 are updated to the next instruction.

Since the selector 421 selects the output 417 of the instruction set sub-table 416, the next instruction is processed as a reduced instruction code, and the reduced instruction code of the upper area 401 is processed in the same cycle as the execution stage of the full instruction code. A is decoded. In this way, the F / F circuit 4
Since the setting change of the execution mode setting register 424 is instructed in the decode stage of the full instruction code using the bit 450 of the full instruction code held in 00, the disturbance of the pipeline when changing to the reduced instruction code execution mode is performed. It can be prevented and the processing can be improved.

Next, the case of changing the execution mode from the reduced instruction code execution mode to the full instruction code execution mode will be described. The execution mode change instruction is set in at least one of the instructions that can be executed in the reduced instruction code execution mode, that is, in any of the instruction set sub-tables 416. At this time, the execution mode change instruction may be held in the upper area 401 of the F / F circuit 400 or may be held in the lower area 402.

When the execution mode change instruction is held in the upper area 401 of the F / F circuit 400, the setting change of the execution mode setting register 424 is decided at the execution stage of the execution mode change instruction. The execution mode change instruction is converted into a full instruction code by the instruction set sub-table 416 and then decoded by the decode circuit 431, and "1" is output to the control signal 452. In the execution stage, the setting change of the execution mode setting register 424 is decided based on the control signal 452. A so-called no-operation (hereinafter referred to as NOP) in which an operation or processing is not performed by a control signal 434 other than the control signal 452 obtained by decoding the execution mode change instruction.
Is instructed to the instruction execution unit 5.

On the other hand, the next cycle of the execution stage of the execution mode change instruction (the same cycle as the decoding stage of the lower side reduced instruction code) is started, the value of the register 424 is changed to 1'b1, and F / F circuit 40
The contents of 0 are updated to the next instruction. The selector 421 is
Since the output signal 420 from the F / F circuit 400 is selected, the next instruction is decoded as a full instruction code.

The reduced instruction code held in the lower area 402 at the same time as the execution mode change instruction may be an operation instruction designating a particular operation or process, but it is preferable to use a normal NOP instruction.

On the other hand, the execution mode change instruction is the F / F circuit 4
If it is held in the lower area 402 of 00, the execution mode is changed to the full instruction code execution mode after the next instruction is decoded as the reduced instruction code execution mode, which may cause a malfunction. . Therefore, in order to determine the setting change of the execution mode setting register 424 in the decode stage of the reduced instruction code B412, the execution mode change instruction detection circuit 422 detects that the reduced instruction code is the execution mode change instruction in the decode stage. .

The execution mode change instruction detection circuit 422 is composed of a comparator, and when the reduced instruction code B412 matches the execution mode change instruction, its output 423 is set to "1". Therefore, in the decode stage of the reduced instruction code B412. Based on the output 423, the setting change of the execution mode setting register 424 is determined. The execution stage of the execution mode change instruction is started, the value of the execution mode setting register 424 is changed to 1′b1, and the F / F circuit 400 is updated to the next instruction. Selector 421 is F
Since the output 420 of the / F circuit 400 is selected, the next instruction is decoded as a full instruction code.

When the reduced instruction code B412 does not match the execution mode change instruction, the execution mode change instruction detection circuit 422 sets the output 423 to "0" and does not change the execution mode setting register 424. Therefore, the next instruction is continuously executed as the reduced instruction code. As described above, by providing the execution mode change instruction detection circuit 422, the setting change to the execution mode setting register 424 by the execution mode change instruction is instructed at the decode stage, so that the execution mode held in the lower area 402 is executed. The apparent execution stage of the change instruction can be eliminated, and the processing speed can be improved.

As described above, according to the microprocessor of the present embodiment, the instruction decoding unit 4 performs the processing while changing the execution mode to the reduced instruction code execution mode or the full instruction code execution mode. As a result, even a full instruction code that cannot be set in the instruction set sub-table 416 can be processed, and the versatility of the microprocessor can be further enhanced.

Also, the execution mode change instruction detection circuit 422
However, since the execution mode change instruction held in the lower area 402 of the F / F circuit 400 is detected at the time of instruction decoding, the execution mode change instruction is not executed,
The apparent execution cycle becomes 0, and the processing speed can be improved.

(Fourth Embodiment) FIG. 6 is a block diagram showing a schematic configuration of a microprocessor according to a fourth embodiment of the present invention. This microprocessor has two instruction set sub-tables 461 and 462, a sub-table selection control register 463, and a selector 417 as compared with the microprocessor in the third embodiment shown in FIG. The difference is that they are replaced. Therefore, detailed description of overlapping configurations and functions will not be repeated.

Instruction set sub-tables 461 and 46
2 is the reduced instruction code 4 output from the selector 413.
The full instruction code corresponding to 15 is output. If the value held in the sub table selection control register 463 is 1′b0, the selector 464 determines that the instruction set sub table 46
The output of 1 is selected and output as the sub instruction code 417. If the value held in the sub table selection control register 463 is 1′b1, the selector 464 selects the output of the instruction set sub table 462 and selects the sub instruction code 41.
Output as 7. In the present embodiment, the case where there are two instruction set sub-tables has been described, but it goes without saying that the number of instruction set sub-tables may be three or more.

As described above, according to the microprocessor of this embodiment, one of the instruction set sub-tables 461 and 462 is selected as a sub-instruction code by the value held in the sub-table selection control register 463. Since the output is performed, in addition to the effect described in the third embodiment, it is possible to select the instruction set sub-table corresponding to the application, and it is possible to provide a microprocessor with high versatility. .

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[0098]

According to the microprocessor of the first aspect, an arbitrary full instruction code corresponding to the reduced instruction code is stored in the instruction set sub-table, so that the reduced instruction code fetched from the instruction memory can be used. The instruction execution circuit can execute the full instruction code, and the size of the instruction memory can be reduced. Further, since the execution mode change circuit changes the execution mode to either the full instruction code execution mode or the reduced instruction code execution mode, the execution mode can be selected according to the application, and the versatility of the microprocessor is enhanced. Became possible.

According to the microprocessor of the second aspect, the execution mode can be changed according to the characteristics of the full instruction code having a long instruction code length and the reduced instruction code having a short instruction code length.

According to the microprocessor of the third aspect, the reduced instruction code on the lower side of the plurality of reduced instruction codes is not executed, the apparent execution cycle becomes 0, and the processing speed can be improved. Became.

According to the microprocessor of the fourth aspect, an arbitrary instruction set sub-table can be selected from a plurality of instruction set sub-tables, and a highly versatile microprocessor can be provided. became.

According to the microprocessor of the fifth aspect, a plurality of instruction set sub-tables are provided corresponding to each of the plurality of fields included in the instruction held in the holding circuit. Accordingly, the full instruction code corresponding to the reduced instruction code can be set in the instruction set sub-table.

According to the microprocessor of the sixth aspect, even if one instruction includes an instruction code having a large number of processing types and an instruction code having a small number of processing types, a microprocessor suitable for the instruction code. It has become possible to configure

According to the microprocessor of the seventh aspect, since the contents of the instruction set sub-table are changed by the immediate load instruction, the instruction set sub-table can be dynamically changed even when the microprocessor is executing the instruction code. It became possible to change the content of.

According to the eighth aspect of the present invention, since the immediate load instruction is set in any of the instruction set sub-tables immediately after the reset of the microprocessor, the instruction set sub-table can be easily set immediately after the reset of the microprocessor. It is now possible to set the contents of the table.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an instruction set and an instruction set sub-table of a microprocessor according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a reduced instruction code in a horizontal microinstruction architecture.

FIG. 3 is a block diagram showing a schematic configuration of an instruction decoding unit according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a schematic configuration of an instruction decoding unit according to the second embodiment of the present invention.

FIG. 5 is a block diagram showing a schematic configuration of a microprocessor according to a third embodiment of the present invention.

FIG. 6 is a block diagram showing a schematic configuration of a microprocessor according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing an example of a schematic configuration of a general microprocessor.

8 is a block diagram for explaining the configuration of the instruction decoding unit 2 shown in FIG. 7 in more detail.

[Explanation of symbols]

1 microprocessor, 2, 3, 4 instruction decode unit, 31 program control unit, 32 data operation unit, 3
3 address operation unit, 34 register operation control unit, 35
Memory control unit, 41, 341, 441 instruction memory,
51 data memory, 100, 141 to 145, 30
0,400,433 F / F circuit, 121-125,4
31 decode circuit, 200, 416, 511, 51
2,531-534,551,552,571,57
2, 591-593 Instruction Set Subtable, 210
Instruction set, 321 multiplier, 322 ALU, 32
3 shifters, 413, 421, 502, 522, 54
2, 562, 582 selector, 422 execution mode change instruction detection circuit, 424 execution mode setting register, 5
00, 520, 540, 560, 580 Sub-table selection control register.

Claims (8)

[Claims] 1. A holding circuit for holding a fetched instruction code, and when executing an instruction held in the holding circuit, the execution mode is changed to either a full instruction code execution mode or a reduced instruction code execution mode. An execution mode changing circuit, an instruction set sub-table in which an arbitrary full instruction code corresponding to the reduced instruction code is stored in the reduced instruction code execution mode, a full instruction code held in the holding circuit and the instruction set An instruction execution circuit for selectively executing any of the full instruction codes stored in the sub-table. 2. The execution mode change circuit, in the full instruction code execution mode, changes the execution mode to a reduced instruction code execution mode by referring to a predetermined bit of the full instruction code held in the holding circuit. The microprocessor according to claim 1, wherein, in the reduced instruction code execution mode, when the reduced instruction code held in the holding circuit is a predetermined instruction, the execution mode is changed to the full instruction code execution mode. 3. The execution mode changing circuit, in the reduced instruction code execution mode, determines whether a reduced instruction code on a lower side of a plurality of reduced instruction codes held in the holding circuit is the predetermined instruction. 3. The microprocessor according to claim 2, wherein the execution mode is changed by making a determination at the decoding stage of the reduced instruction code on the lower side. 4. The microprocessor includes a plurality of the instruction set sub-tables, the microprocessor further stores a register for storing information on which of the plurality of instruction set sub-tables to select, and the register. The microprocessor according to any one of claims 1 to 3, further comprising: a selector that switches outputs of the plurality of instruction set sub-tables according to information stored in. 5. A microprocessor for executing an instruction code including a plurality of fields indicating processing contents to be executed, the holding circuit holding a fetched instruction code, and the instruction held in the holding circuit. A plurality of instruction set sub-tables provided corresponding to each of a plurality of fields stored therein and storing arbitrary full instruction codes corresponding to reduced instruction codes, and full instruction codes output from the plurality of instruction set sub-tables A plurality of decoding circuits for decoding the
A plurality of instruction execution circuits that execute a full instruction code. 6. A microprocessor for executing an instruction code including a plurality of fields indicating processing contents to be executed, the holding circuit holding a fetched instruction code, and the instruction held in the holding circuit. One or more instruction set sub-tables that are provided corresponding to one or more fields of a plurality of fields stored therein and that store arbitrary full instruction codes corresponding to reduced instruction codes; and that correspond to the one or more fields. A first decoding circuit for decoding a full instruction code output from an instruction set sub-table provided by the above, and a second decoding circuit for directly decoding a full instruction code corresponding to a field other than the one or more fields, A plurality of executing a full instruction code according to a decoding result by the first and second decoding circuits. And a command execution circuit, a microprocessor. 7. The contents of the instruction set sub-table are:
The macro processor according to any one of claims 1 to 6, which is modified by an immediate load instruction. 8. The microprocessor according to claim 7, wherein the immediate load instruction is set in any of the instruction set sub-tables immediately after the reset of the microprocessor.