JP2915131B2 - Data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device such as a microprocessor, and more particularly, to a processing method for simultaneously executing a plurality of instructions in a parallel RISC processor.

[Conventional technology]

In the conventional device, as described in JP-A-63-49843, the input of the input register of the arithmetic unit is connected only to the output port of the register file, and the output of the arithmetic unit is only the output port specific to the arithmetic unit. Was connected to. As a prior application of the present application, Japanese Patent Application Laid-Open No. 3-245223 discloses a data dependence discriminating circuit for selectively inputting data to the first and second arithmetic units to either an input latch or an output latch. ing. However, Japanese Patent Application Laid-Open No. 3-245223 does not disclose or suggest priority order determining means for a plurality of bypass paths.

[Problems to be solved by the invention]

In the above conventional example, the instruction is (1) read from the register,
When a pipeline processing method is used in which execution is performed in three stages of (2) operation and (3) register write, the read register number of the instruction in the register read stage is changed to the write register number of the instruction in the operation stage. No consideration is given to the case of coincidence, and there has been a problem that the execution result of the instruction in the operation stage is not reflected in the operand data of the instruction in the register read stage, which is the subsequent instruction.

It is an object of the present invention to provide a means for enabling the execution result of an instruction in an operation stage to be correctly reflected in the next instruction (that is, register reading (instruction in a stage)) even if the register numbers match as in the above case. To provide.

Another object of the present invention is to provide means for correctly reflecting the execution result of an instruction in an operation stage to the next instruction without inserting a delay cycle even if the register numbers match as in the above case. It is in.

Still another object of the present invention is to correct the execution results of a plurality of instructions in the operation stage without inserting a delay cycle even if the register numbers match as in the above case, and to correctly execute the next plurality of instructions. It is to provide a means that can be reflected in the information.

[Means for solving the problem]

In order to achieve the above object, the input of the input register of the arithmetic unit is connected not only to the output port of the register file but also to the output of the arithmetic unit so that data can be selectively input.

Further, means for comparing the read register field of the instruction in the register read stage with the write register field of the instruction in the operation stage is provided, and when they match, instead of reading from the register file, A means for directly setting the output to the input register of the arithmetic unit is provided. Further, when the read register number of the instruction in the register read stage matches the write register number of a plurality of instructions in the operation stage, the instruction corresponding to the instruction indicating the latest operation result among the plurality of instructions. There is provided priority order determining means for preferentially setting input means from the arithmetic unit to the input register.

[Action]

The i-th instruction among the plurality (n) of instructions executed in parallel is assumed to be operated by the i-th arithmetic unit.

I-th instruction among a plurality of instructions in the register read stage
In the second instruction (first instruction), if the read register number of the first instruction does not match any of the write register numbers of the n instructions in the operation stage, the corresponding register number is read from the register file. The contents are read out and set in the input register of the i-th computing unit.
On the other hand, when the write register number of the j-th instruction (the second instruction) among the n instructions in the operation stage matches, the readout from the register file is performed instead of reading from the register file. The operation result is directly set in the input register of the i-th operation unit. Thereby, the first instruction can correctly reflect the execution result of the second instruction, and does not malfunction.

When the write register numbers of a plurality of instructions in the operation stage match, and when the read register number of the first instruction matches the register number, the instruction whose register number matches Of the instructions, the output of the arithmetic unit corresponding to the instruction that should be executed latest, that is, the instruction with the largest number (third instruction) is selected.
It is set in the input register of the ith arithmetic unit. Also,
In writing to the register file, only the operation result of the third instruction is written and the operation result of another instruction having the same write register number is written in the register so that the execution result of the third instruction becomes valid. Do not write to file. As a result, the contents of the register file and the first
, The execution result of the third instruction becomes valid,
There is no malfunction.

〔Example〕

 Hereinafter, an embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a block diagram of a processor 100 that executes two instructions in parallel according to an embodiment of the present invention.

The processor 100 mainly includes a register file 110, two operation units 120 and 130, instruction registers 140, 141, 150, 151, 160, and 161.
And an instruction buffer 180.

The register file 110 includes 32 registers R0 to R31.

Arithmetic units 120 and 130 are A-side input registers 121 and 13 respectively.
1 and B side input registers 122 and 132.

Selectors 124, 125, 134, and 135 are connected to input ports of the input registers 121, 122, 131, and 132, respectively.

The selector 124 is a register file read port 1
11 and one of the outputs 126 and 136 of the two arithmetic units are selected and input to the input register 121.

Selector 125 is the register file read port 1
12 and one of the outputs 126 and 136 of the two arithmetic units are selected and input to the input register 122.

The selector 134 is a register file read port 1
13 and one of the outputs 126 and 136 of the two arithmetic units are selected and input to the input register 131.

Selector 135 is a register file read port 1
14 and one of the outputs 126 and 136 of the two arithmetic units are selected and input to the input register 132.

The instruction registers 140, 150, 160 are connected in series,
The even-numbered instruction transferred from the instruction buffer 180 is sequentially sent to the instruction registers 140, 150, and 160.

The instruction registers 141, 151, 161 are connected in series,
The odd-numbered instruction transferred from the instruction buffer 180 is sequentially sent to the instruction registers 141, 151, and 161.

The instruction buffer 180 temporarily stores an instruction read from the main memory or the cache memory.

The instructions (for example, 140) handled by the processor of this embodiment are:
The first field includes an OP code section (140a) indicating the type of instruction (operation), a first source section (140b) indicating the first source operand (A-side input of the arithmetic unit), and a fourth field. A second source unit (140c) indicating the two source operands (B-side input of the arithmetic unit) and a destination unit (140d) indicating the destination operand (the output destination of the arithmetic unit).

The processor of this embodiment divides the execution of an instruction into three stages and processes the instruction in a pipeline.

The three stages are (1) a register read stage, (2) an operation execution stage, and (3) a register write stage.

The instruction registers 140 and 141 hold the instruction in the read stage of the register, the instruction registers 150 and 151 hold the instruction in the operation execution stage, and the instruction register 16
0,161 holds the instruction in the writing stage to the register.

Hereinafter, the execution of the instruction will be described for each cycle.

In the first cycle, the instruction read from the memory is first transferred from the instruction buffer 180 to the instruction registers 140 and 141.

The instructions set in the instruction registers 140 and 141 read the source operand from the register file 110 and set them in the input registers 121, 122, 131, and 132 of the arithmetic unit.

Here, the register file read port 111 reads the contents of the register having the register number indicated by the first source section 140b of the instruction register 140, and the register file read port 112 reads the second source section 140c of the instruction register 140.
Read the contents of the register with the register number indicated by
Register file read port 113 is instruction register 1
The contents of the register with the register number indicated by the first source section 141b of 41 are read, and the register file read port 114 reads the contents of the register with the register number indicated by the second source section 141c of the instruction register 141.

In the second cycle, the instructions set in the instruction registers 140 and 141 are transferred to the instruction registers 150 and 151, respectively.

The instructions set in the instruction registers 150 and 151 operate the operand data set in the input registers 121, 122, 131 and 132 of the operation units by using the operation units 120 and 130, and set the operation results in the output registers 123 and 133.

Here, the arithmetic unit 120 is controlled by an output signal of a decoder 152 that decodes the OP code section 150a of the instruction register 150, and the arithmetic unit 130 is controlled by the OP code section 151a of the instruction register 151.
Is controlled by the output signal of the decoder 153 that decodes

In the third cycle, the instructions set in the instruction registers 150 and 151 are transferred to the instruction registers 160 and 161 respectively. The instruction set in the instruction registers 160 and 161 writes the execution result of the instruction (the contents of the output registers 123 and 133) to the destination operand of the register file. Here, the register file write port 115 writes to the register of the register number indicated by the destination section 160d of the instruction register 160, and the register file write port 116 is the register indicated by the destination section 161d of the instruction register 161. Write to the number register.

Next, the comparators 171, 172, 173, 174, 17 which are features of the present invention.
5,176,177,178 will be described.

The comparator 171 compares the first source part 140b of the instruction register 140 with the destination part 151d of the instruction register 151, and when the register numbers match, the selector 124
By selecting the output 136 of the arithmetic unit 130 instead of the read port 111 of the register file
Enter 121.

The comparator 172 compares the first source part 140b of the instruction register 140 with the destination part 150d of the instruction register 150, and when the register numbers match, the selector 124
By selecting the output 126 of the computing unit 120 instead of the read port 111 of the register file
Enter 121.

If both the comparators 171 and 172 detect coincidence, the control of the comparator 171 is prioritized. The priority circuit 190 is a circuit for performing the above processing.

The comparator 173 compares the second source section 140c of the instruction register 140 with the destination section 151d of the instruction register 151. If the register numbers match, the selector 125
To select the output 136 of the arithmetic unit 130 instead of the read port 112 of the register file,
Enter 122.

The comparator 174 compares the second source section 140c of the instruction register 140 with the destination section 150d of the instruction register 150. If the register numbers match, the selector 125
To select the output 126 of the computing unit 120 instead of the register file read port 112, and
Enter 122.

If both the comparators 173 and 174 detect coincidence, the control of the comparator 173 is prioritized. The priority circuit 191 is a circuit for performing the above processing.

The comparator 175 compares the first source part 141b of the instruction register 141 with the destination part 151d of the instruction register 151, and when the register numbers match, the selector 134
To select the output 136 of the arithmetic unit 130 instead of the read port 113 of the register file,
Enter 131.

The comparator 176 compares the first source part 141b of the instruction register 141 with the destination part 150d of the instruction register 150, and when the register numbers match, the selector 134
To select the output 126 of the arithmetic unit 120 instead of the read port 113 of the register file, and
Enter 131.

If both of the comparators 175 and 176 detect a match, the control of the comparator 175 is prioritized. The priority circuit 192 is a circuit for performing the above processing.

The comparator 177 compares the second source part 141c of the instruction register 141 with the destination part 151d of the instruction register 151, and when the register numbers match, the selector 135
To select the output 136 of the computing unit 130 instead of the register file read port 114
Enter in 132.

The comparator 178 compares the second source part 141c of the instruction register 141 with the destination part 150d of the instruction register 150, and when the register numbers match, the selector 135
By selecting the output 126 of the computing unit 120 instead of the register file read port 114, and
Enter in 132.

If both the comparators 177 and 178 detect a match, the control of the comparator 177 is prioritized. The priority circuit 193 is a circuit for performing the above processing.

In the register file 110 of the present embodiment, data written to a certain register from the write ports 115 and 116 is
In the read of the cycle, the read port 111,
Reflected on 112,113,114. That is, write port 1
When data is written to the R2 register at 15 and the contents of the R2 register are read from the read port 111 in the same cycle, the data written from the write port 115 is correct and can be read from the read port 111. This can be achieved by providing a bypass path in the register file.However, in one cycle, writing to the register file is performed in the first half cycle, and reading of the register file is performed in the second half cycle. For example, it can be easily realized.

As described above, according to the present embodiment, two instructions can be executed in parallel in the cycle time in which one instruction was conventionally executed.

〔The invention's effect〕

As described above, according to the present invention, the bypass means for directly setting the outputs of the plurality of arithmetic units to the input registers of the arithmetic units is provided. In a pipeline processor as a stage, the operation result of the instruction in the operation execution stage can also be used for the execution of the operation in the next cycle, so that the instruction can be processed at high speed.

In addition, since there is a means for comparing the read register number of the instruction in the register read stage with the write register number of the instruction in the operation execution stage, if the register numbers match, the above bypass means is used. Since the operation result can be controlled so as to be directly set in the input register of the operation unit, it is possible to prevent reading out the old value in the register and to execute the instruction at high speed.

Furthermore, since there is a plurality of priority determining means for the bypass paths, even if the numbers of the write registers and the numbers of the read registers of the plurality of instructions in the operation execution stage match, the latest operation output is selected. Thus, reading of an old value can be prevented, and furthermore, high-speed execution of an instruction becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data processing apparatus according to one embodiment of the present invention. 124,125,134,135 …… Bypass input selector, 126,136…
… Bypass path for operation unit output, 171,172,173,174,175,17
6,177,178 …… Register number comparator, 190,191,192,193…
... A bypass route priority determining circuit.

Continued on the front page (56) References Morihiro Kuga (three outsiders), "Register File with Dependency Analysis Function of" Shinpu "Processor", Proc. Of the 40th IPSJ Annual Conference , March 14, 1990, p. 1269-1270 (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 9/38

Claims (3)

(57) [Claims] 1. A data processing apparatus comprising: a register file holding information managed by register numbers; and a plurality of arithmetic units for executing a plurality of instructions in parallel, wherein a plurality of instructions executed by the data processing apparatus are provided. Each instruction of the above is a read stage for reading information corresponding to a read register number from the register file, an operation execution stage for executing an operation, and information on an execution result of the arithmetic unit associated with the write register number in the register file. And a write stage for writing to the plurality of arithmetic units. Each of the plurality of arithmetic units is connected to the register file, and any one of an output of the register file and an execution result of the plurality of arithmetic units is selected. Selector means for inputting the instructions to the arithmetic unit, and a plurality of instructions in the arithmetic execution stage. Means for comparing the write register number with the read register number of a plurality of instructions in the read stage; and the comparing means in the read register number of the instruction in the read stage and the operation execution stage. When detecting a match of any one of the plurality of instructions with the write register number, the latest execution result among the execution results corresponding to the matched instruction in the operation execution stage is stored in the read stage. A data processing device comprising: a priority order determining unit that controls the selecting unit so as to input the matched instruction to an arithmetic unit that executes the instruction. 2. A data processing apparatus comprising: a register file for holding information managed by register numbers; and a plurality of arithmetic units for executing a plurality of instructions in parallel, wherein a plurality of instructions executed by the data processing apparatus are provided. Each instruction of the above is a read stage for reading information corresponding to a read register number from the register file, an operation execution stage for executing an operation, and information on an execution result of the arithmetic unit associated with the write register number in the register file. And a write stage for writing to the plurality of arithmetic units. Each of the plurality of arithmetic units is connected to the register file, and any one of an output of the register file and an execution result of the plurality of arithmetic units is selected. Selector means for inputting the instructions to the arithmetic unit, and a plurality of instructions in the arithmetic execution stage. Means for comparing the write register number with the read register number of a plurality of instructions in the read stage; and the comparing means in the read register number of the instruction in the read stage and the operation execution stage. When detecting a match of any one of the plurality of instructions with the write register number, the latest execution result among the execution results corresponding to the matched instruction in the operation execution stage is stored in the read stage. A data processing apparatus comprising: a priority determining unit that bypasses the register file by controlling the selecting unit so as to directly input the matched instruction to an arithmetic unit that executes the matched instruction. 3. An arithmetic unit of the plurality of arithmetic units is connected to an input register and an output register, respectively, and an output of the arithmetic unit is connected to an input of the output register and the selector. An output of the output register is connected to an input port of the register file, an output of the input register is connected to an input of the arithmetic unit, and an input of the input register is connected to the selector. The data processing device according to claim 1 or 2, wherein: