JP2004220377A - Reconfigurable circuit, and integrated circuit device and data conversion device capable of using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a circuit area of a reconfigurable circuit, and to smooth processing speed. <P>SOLUTION: This reconfigurable circuit comprises an ALU array, and is not mounted with a multiplier. A multiplication is replaced with a shift operation, and a data flow graph is produced. A shift number is fixed, and mounting of a large circuit such as a barrel shifter is avoided. The multiplication notated by the shift operation is expressed by the data flow graph, and a corresponding operation and its flow are loaded to the reconfigurable circuit. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

図３は上記プログラムに対応するデータフローグラフを示す。図中、定数、変数および演算子は丸で囲まれ、ｍｕｌは乗算、ａｄｄは加算を示す。これをそのままリコンフィギュラブル回路１２へマッピングすると、図４の状態になる。しかし、本実施の形態では乗算器がないため、乗算をシフタで実現する。
【００２７】
ｘ＝２×ａ、ｙ＝５×ｂは、それぞれビットシフトを用いると、
ｘ＝ａ＜＜１、ｙ＝ｂ＋（ｂ＜＜２）
と表記できる。ここで、「＜＜」は左ビットシフトである。図５はこの表記に対応するデータフローグラフ、図６は図５をもとにマッピングされたリコンフィギュラブル回路１２を示す。同図において、ｍｏｖは前述のＮＯＰ演算である。データフローグラフから実際に回路をマッピングする方法は以下のとおりである。
【００２８】
１．データフローグラフの入力端に存在する変数および定数はデータ入力部４０へアサインする。
２．データフローグラフで入力端から数えてｉ番目の→の先にある演算は、第ｉ＋１段目のＡＬＵにアサインする。
３．２．の例外として、ある演算に到達する複数のパスにおける→の数がｉ、ｊのごとく違う場合、多いほうに合わせる。いま、ｉ＜ｊのとき、当該演算を第ｊ＋１段目にアサインする。
４．３．のとき、段数を合わせるために、ｉの側のパスに、ＮＯＰに相当するｍｏｖ演算を（ｊ−ｉ）個挿入する。
【００２９】
このように、本実施の形態では、まず定数×変数の形の乗算をビットシフトと加算へ変換し、これをデータフローグラフへ変換してリコンフィギュラブル回路１２へマッピングする。これにより、乗算器が存在しなくても処理時間の短いシフタで乗算が実行できる。以下、データフローグラフから回路をマッピングする方法は同様なので、以降、データフローグラフだけで説明をする。
【００３０】
つぎに、以下のプログラムの実行を考える。

８×ａ＝ａ＜＜３であるから、これをデータフローグラフに表すと図７となる。しかし、３ビットシフトは本実施の形態ではひとつのＡＬＵでは実行できないため、図７のデータフローグラフを図８のごとく変換し、２ビット以下のシフト演算へ分解する。この配慮により、ＡＬＵに実装すべき命令数が減る意味でも回路規模の縮小効果がある。
【００３１】
つづいて、以下のプログラムの実行を考える。

１０×ａ＝（ａ＜＜１）＋（ａ＜＜１＜＜２）であり、そのデータフローグラフは図９となる。ここで、太線で囲んだふたつの演算５０は、入力ａに対して同じ回数だけ左シフトを行うことを示しているので、図１０のようにマージし、処理を簡素化する。
【００３２】
つづいて、以下のプログラムの実行を考える。

１５×ａ＝（ａ＜＜３）＋（ａ＜＜２）＋（ａ＜＜１）＋ａであり、そのデータフローグラフは図１１となる。しかしここで、二進数表現をしたときに最もゼロが多くなる、いわゆるミニマル表現をすると、１５は以下のようになる。
１５＝（１１１１）_２＝（１０００Ｎ１）_２
ただし、「Ｎ１」は−１を表す。したがって、上記プログラムをビットシフトで示すと、以下のとおりである。
１５×ａ＝（ａ＜＜４）−ａ
図１２はこの式に対応するデータフローグラフであり、ｓｕｂは減算を示す。このように、ミニマル表現と必要に応じて減算器を利用することにより、処理をさらに簡素化することができ、利用すべきＡＬＵを減らすことができる。
【００３３】
図１３は、以上の処理を一般化し、定数×変数の乗算をシフタによるミニマル表現の処理へ変換する手順を示す。処理は４つの段階に大別され、図１３は主に第１段階の処理を示す。
【００３４】
［第１段階］ 乗算→１ビットシフタ変換
乗算ノードを１ビットシフタ、加算および符号逆転ノードへ変換する。符号逆転ノードは一時的に使用するが、第４段階で減算ノードへ変換される。一般に整数はＡ＝ｓ・Σ^Ｎ _ｋ−１ａ_ｋ・２^ｋと表される。ただし、ｓ＝１または−１、ａ_ｋ＝０のたは１である。ここでは、初期値としてＡ≠０とする。以下の手順において、とくに指示がなければ直下のステップへ進む。図１３では、ＳｔｅｐをＳと略記している。
【００３５】
Ｓｔｅｐ１ 以下の変数に初期値を設定する。
ｃ←０、ｃｎｔ←０、ｎ←０、ｆｌａｇ←０、ノード配列：ＮＬ←空
ｃは処理中利用するキャリービット、ｃｎｔはカウンタ、ＮＬはノードに演算を割り当てるための配列、ｎはＮＬへのポインタ、ｆｌａｇは状態フラグである。
【００３６】
Ｓｔｅｐ２ Ａ＝０かつｃ＝０ならば、処理を終了する。
Ｓｔｅｐ３ ａ_０＝ｃならば、Ｓｔｅｐ１１へ進む。
Ｓｔｅｐ４ ｃｎｔ≠０ならばＳｔｅｐ６へ進む。
Ｓｔｅｐ５ ＮＬ［ｎ］に入力が変数のｍｏｖノードを作成する。また、ｎ←ｎ＋１としてＳｔｅｐ７へ進む。
【００３７】
Ｓｔｅｐ６ ＮＬ［ｎ］〜ＮＬ［ｎ＋ｃｎｔ−１］にｃｎｔ個の連続した１ビットシフタノードを作成する。ＮＬ［ｎ］の入力は変数、それ以外のノードの入力は、前のシフタノードの出力とする。また、ｎ←ｎ＋ｃｎｔとする。
Ｓｔｅｐ７ ａ_１＝０かつＳ＝−１、または、ａ_１≠０かつＳ＝１ならば、ＮＬ［ｎ］に符号逆転ノードを作成し、ｎ←ｎ＋１とする。
Ｓｔｅｐ８ ｆｌａｇ＝０ならばｆｌａｇ←１とし、Ｓｔｅｐ１０へ進む。
Ｓｔｅｐ９ ＮＬ［ｎ］に、ＮＬ［ｎ_ｏｌｄ−１］の出力とＮＬ［ｎ−１］の出力を入力とする加算ノードを作成する。また、ｎ←ｎ＋１とする。
【００３８】
Ｓｔｅｐ１０ ｎ_ｏｌｄ←ｎとする。
Ｓｔｅｐ１１ ａ_０＋ａ_１＋ｃ≧２ならばｃ←１とし、そうでなければ、ｃ←０とする。
Ｓｔｅｐ１２ ａ_０←ａ_１、ａ_１←ａ_２、・・・、ａ_Ｎ−１←ａ_Ｎ、ａ_Ｎ←０とし、ｃｎｔ←ｃｎｔ＋１とする。
Ｓｔｅｐ１３ Ｓｔｅｐ２へ戻る。
【００３９】
［第２段階］ 同入力、同命令ノードのマージ
ｎ個のノード配列ＮＬに対して、入力が同じ値でかつ、命令が同じノードが２つ以上あれば、１つにまとめる。
【００４０】
［第３段階］ ビットシフタのマージ
連続する１ビットシフタを固定長ｎビットシフタ（ｎ≧２）へまとめる。
【００４１】
［第４段階］ 減算ノードへのマージ
符号逆転ノードから加算ノードへ接続する処理を減算ノードへまとめる。加算式を式（１）のように表す。
【００４２】
ｏｕｔｐｕｔ ＝ ｉｎｐｕｔ１ ＋ ｉｎｐｕｔ２ （１）
ｉ）加算ノードへの入力のうちの１つが符号逆転ノードの場合
ｉｎｐｕｔ１ ＝ −ｉｎｐｕｔ１’
ここで、式（１）は

式（２）より、減算ノードへ変換を行う。
ｉｉ）加算ノードへの入力が共に符号逆転ノードの場合
ｉｎｐｕｔ１ ＝ −ｉｎｐｕｔ１’
ｉｎｐｕｔ２ ＝ −ｉｎｐｕｔ２’
ここで、式（１）は

式（３）より、加算ノードと符号逆転ノードへ変換を行う。
【００４３】
以下に、上記の手順による乗算からシフタへの変換の実例を示す。ここでは、ａ×２３を想定する。２３は２進数表現で（１０１１１）_２である。以下、煩瑣を避け、ｎの値に応じた配列ＮＬの状態を示すに留める。
【００４４】
［第１段階］ 乗算→１ビットシフタ変換
ｎ＝０でスタートし、ｍｏｖノードが作成される（Ｓ５）。図１４はＮＬ［０］を示す。この後、ｎがインクリメントされる。
ｎ←１の後、符号逆転（ｎｅｇ）ノードが作成される（Ｓ７）。図１５はＮＬ［１］が追加された状態を示す。この後、
ｎ←２、ｆｌａｇ←１、Ｎ_ｏｌｄ←２、ｃ←１、Ａ←（１０１１）_２、ｃｎｔ←１
となり、シフタノードが作成される（Ｓ６）。つぎのループで、
ｎ←３、ｃ←１、Ａ←（１０１）_２、ｃｎｔ←２
となり、同様にシフタノードが作成される（Ｓ６）。さらにつぎのループで、
ｎ←４、ｃ←１、Ａ←（１０）_２、ｃｎｔ←３
となり、同様にシフタノードが作成される（Ｓ６）。シフタは１ビットシフタである。この時点で配列は図１６の状態になる。
【００４５】
ｎ←５とされた後、符号逆転（ｎｅｇ）ノードが作成される（Ｓ７）。この時点で、配列は図１７の状態になる。
ｎ←６の後、ａｄｄノードが作成される（Ｓ９）。配列は図１８になる。
ｎ←７の後、Ｎ_ｏｌｄ←７、ｃ←１、Ａ←（１）_２、ｃｎｔ←４となり、シフタノードが作成される（Ｓ６）。
ｎ←８の後、ｃ←１、Ａ←（０）_２、ｃｎｔ←５となり、シフタノードが作成される（Ｓ６）。以下、ｎ＝９，１０，１１でも同様にシフタノードが作成される（Ｓ６）。これで配列は図１９の状態になる。
【００４６】
ｎ←１２の後、ａｄｄノードが作成される（Ｓ９）。これで配列は図２０の状態になる。この後、ｎ←１３、Ｎ_ｏｌｄ←１３、ｃ←０、Ａ←（０）_２、ｃｎｔ←６となり、処理を終える。
【００４７】
［第２段階］ 同入力、同命令ノードのマージ
図２０において、ＮＬ［２］とＮＬ［７］、すなわち、ｎ＝２と７の行が同入力で同命令である。この状態を検出し、マージすると、図２１となる。さらに図２１においてＮＬ［３］とＮＬ［８］が同入力で同命令であるのでマージすると図２２が得られる。同様に繰り返しマージすると図２３の状態が得られる。以上のマージ処理もコンパイル部２０でなされる。
【００４８】
［第３段階］ ビットシフタのマージ
図２３より、連続する１ビットシフタを検出し、２ビットシフタへ置き換える。但し、シフタ２は２ビットシフタを表す。この結果、図２４の状態になる。
【００４９】
［第４段階］ 減算ノードへのマージ
図２４において、ＮＬ［６］＝ＮＬ［１］＋ＮＬ［５］ ＝−ＮＬ［０］−ＮＬ［４］＝−（ＮＬ［０］＋ＮＬ［４］）であるから、ａｄｄ命令→ｎｅｇ命令へ変換すると図２５の状態となる。ここでは、ｎｅｇ命令のあるｎ＝１と５の行、すなわちＮＬ［１］とＮＬ［５］を消去するために、これらを入力とする行、すなわちＮＬ［６］を検出し、つづいてＮＬ［１］とＮＬ［５］をそれぞれそれらの入力へさかのぼり、ｎｅｇ命令を消す。
【００５０】
この後、まだｎｅｇ命令がＮＬ［７］にあるため、それを入力とするＮＬ［１２］を検出し、ＮＬ［７］を同様に入力へたどってＮＬ［６］で表す。すなわち、ＮＬ［１２］＝ＮＬ［７］＋ＮＬ［１０］＝−ＮＬ［６］＋ＮＬ［１０］＝ＮＬ［１０］−ＮＬ［６］であるから、ｎｅｇ命令は結果として減算（ｓｕｂ）命令に変換でき、図２６の状態になる。以上で処理を完了し、結果として、ａ×２３は図２７に示すデータフローグラフとなる。あとは、このデータフローグラフを回路へマッピングすればよい。
【００５１】
以上述べたリコンフィギュラブル回路１２では、基本セルとして高性能の演算能力のあるＡＬＵを用いることができ、その際コンフィグレーションは１クロックの設定動作で可能であり、設定データ１７のロードにより、瞬時に回路を再構成することができる。
【００５２】
本実施の形態では、ＡＬＵは乗算器を持たないとしたが、当然、乗算器を備えたＡＬＵと混在させてリコンフィギュラブル回路１２を構成してもよい。その場合、変数×変数タイプの乗算は乗算器で実行し、定数×変数タイプの乗算をシフト演算で実行すればよい。
【００５３】
以上、本発明を実施の形態をもとに説明した。実施の形態は例示であり、それらの各構成要素や各処理プロセスの組み合わせにいろいろな変形例が可能なこと、またそうした変形例も本発明の範囲にあることは当業者に理解されるところである。
【００５４】
【発明の効果】
本発明によれば、性能面で改善されたリコンフィギュラブル回路とそれを搭載する集積回路装置、およびリコンフィギュラブル回路にデータを設定するためのデータ変換装置を提供できる。
【図面の簡単な説明】
【図１】実施の形態に係る集積回路装置および外部制御装置の構成図である。
【図２】図１のリコンフィギュラブル回路の構成図である。
【図３】あるプログラムの処理を表したデータフローグラフを示す図である。
【図４】図３のデータフローグラフに対応してマッピングされたリコンフィギュラブル回路の構成図である。
【図５】別のプログラムの処理を表したデータフローグラフを示す図である。
【図６】図５のデータフローグラフに対応してマッピングされたリコンフィギュラブル回路の構成図である。
【図７】さらに別のプログラムの処理を表したデータフローグラフを示す図である。
【図８】図７のデータフローグラフを一部書き換えたデータフローグラフを示す図である。
【図９】さらに別のプログラムの処理を表したデータフローグラフを示す図である。
【図１０】図９のデータフローグラフの重複処理を統合して得られるデータフローグラフを示す図である。
【図１１】さらに別のプログラムの処理を表したデータフローグラフを示す図である。
【図１２】図１１のデータフローグラフをミニマル表現に変更して得られるデータフローグラフを示す図である。
【図１３】データフローグラフをミニマル表現に変換するための処理を示すフローチャートである。
【図１４】図１３のフローチャートによって、ＡＬＵに割り当てるべき演算を示す配列が形成される途中状態を示す図である。
【図１５】図１３のフローチャートによって、ＡＬＵに割り当てるべき演算を示す配列が形成される途中状態を示す図である。
【図１６】図１３のフローチャートによって、ＡＬＵに割り当てるべき演算を示す配列が形成される途中状態を示す図である。
【図１７】図１３のフローチャートによって、ＡＬＵに割り当てるべき演算を示す配列が形成される途中状態を示す図である。
【図１８】図１３のフローチャートによって、ＡＬＵに割り当てるべき演算を示す配列が形成される途中状態を示す図である。
【図１９】図１３のフローチャートによって、ＡＬＵに割り当てるべき演算を示す配列が形成される途中状態を示す図である。
【図２０】図１３のフローチャートによって、ＡＬＵに割り当てるべき演算を示す配列が形成される途中状態を示す図である。
【図２１】図２０において、同入力、同命令ノードをマージして得られる配列を示す図である。
【図２２】図２１において、同入力、同命令ノードをマージして得られる配列を示す図である。
【図２３】図２２において、同入力、同命令ノードをマージして得られる配列を示す図である。
【図２４】図２３において、ビットシフタのマージをマージして得られる配列を示す図である。
【図２５】図２４において、ｎｅｇノードを消去する途上の配列を示す図である。
【図２６】図２５において、ｎｅｇノードを消去した結果得られた配列を示す図である。
【図２７】ａ×２３をミニマル表現するデータフローグラフを示す図である。
【符号の説明】
１０ 集積回路装置、 １２ リコンフィギュラブル回路、 １４ 設定部、１６ 設定データ記憶部、 １７ 設定データ、 １８ 制御部、 １９ プログラム、 ２０ コンパイル部、 ２１ データフローグラフ、 ２２ プログラム記憶部、２４ 外部制御装置、３０ 接続結線、 ４０ データ入力部、４２ ＡＬＵアレイ、 ４４ 接続スイッチ。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an integrated circuit technology, and particularly to a reconfigurable circuit, and an integrated circuit device and a data conversion device that can use the same.
[0002]
[Prior art]
Recently, wireless communications such as mobile phones, GPS, and VICS have become widespread, and the types of wireless devices have been increasing. If all of these radios or their functions are implemented by hardware, the cost and the mounting area increase. Therefore, there is a concept of a "software radio" in which a circuit having general-purpose capability is mounted as hardware, and various functions are realized by switching software to be loaded on the circuit.
[0003]
As a circuit for realizing the software defined radio, there are an FPGA (Field Programmable Gate Array) and a DSP (Digital Signal Processor). Patent Document 1 proposes a method for reusing a circuit configuration by dynamically reconfiguring an FPGA. A type of circuit that can be dynamically changed is also referred to as a reconfigurable circuit.
[0004]
[Patent Document 1]
Japanese Patent Application Laid-Open No. H10-256383 (Full text, Fig. 1-4)
[0005]
[Problems to be solved by the invention]
Various logic can be realized by using a look-up table (LUT) for storing a truth table of a logic circuit based on an FPGA. However, in general, a unit of a logic element is small, and a desired function is realized. Requires many LUTs and wiring resources. As a result, as compared with a normal LSI, the mounting area is generally large and the cost is high. Also, the program time for rewriting the circuit is long to some extent, and is often not suitable for real-time function switching.
[0006]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a reconfigurable circuit which is advantageous in terms of cost, rewriting speed, and the like, and an integrated circuit device using the same.
[0007]
[Means for Solving the Problems]
One embodiment of the present invention relates to a reconfigurable circuit. This circuit comprises an array of ALUs and other logic circuits, each of which can selectively execute a plurality of arithmetic logic functions, and a connection unit that holds a connection relationship between the logic circuits, and includes one of the logic circuits. , A bit shifter is mounted in place of the multiplier. For this reason, the circuit part required for the multiplier can be reduced, and the processing time can be reduced. The multiplication itself is replaced by a bit shift operation. The connection unit may have a switch and a connection for connecting an output of the logic circuit to an input of another logic circuit, and in that case, it is possible to enable a connection having a specific connection relationship by setting. it can.
[0008]
In this configuration, the number of shifts by the bit shifter may be fixed. If the number of shifts is made variable like a barrel shifter, the circuit scale becomes large.
[0009]
Further, a subtractor may be implemented in any of the logic circuits. In this case, the multiplication can be realized by using not only the bit shift but also the subtractor, and the circuit scale required for realizing the desired function can be reduced.
[0010]
Further, a desired multiplication may be expressed in a minimal manner, and an operation corresponding to the multiplication may be configured in the array by using the above-described bit shifter. Since it is a minimal expression, it is of course possible to reduce the circuit scale for realizing it, specifically, the number of necessary logic circuits.
[0011]
Another embodiment of the present invention relates to an integrated circuit device. The apparatus includes a reconfigurable circuit including an array of logic circuits each capable of selectively executing a plurality of arithmetic logic functions, and a connection unit for maintaining a connection relationship between the logic circuits, and a reconfigurable circuit. Storage unit for storing setting data for setting the function of each logic circuit in the reconfigurable circuit and the input / output connection relationship between the logic circuits, and a setting unit for reading the configuration data from the storage unit and loading the reconfigurable circuit In the reconfigurable circuit, a bit shifter is mounted instead of the multiplier in any of the logic circuits. With this configuration, the advantage of the above-described reconfigurable circuit can be enjoyed in the entire integrated circuit device, and the cost and circuit size of the device can be reduced.
[0012]
Note that the setting data described above may be data corresponding to an expression using a bit shift instead of a graph representing a data flow of a multiplication to be performed. In this case, the multiplication can be realized by a bit shift.
[0013]
Still another aspect of the present invention is an apparatus for generating setting data for causing a reconfigurable circuit to execute a desired process, wherein the multiplication to be performed in the reconfigurable circuit does not include the multiplication, and performs bit shifting. And a compiling unit for converting to a format including. This data conversion device may be mounted on-board in a device in which a reconfigurable circuit is mounted, or conversely, may generate off-board setting data to be loaded into the reconfigurable circuit. Good. Note that the compiling unit may generate the setting data so as to have a minimal expression. This data converter may include a setting unit or a control unit for loading the generated setting data into the reconfigurable circuit.
[0014]
In any of the above cases, the array of logic circuits is an array in which a plurality of rows of logic circuits arranged in the horizontal direction are combined in the vertical direction, and there is no connection for connection between the logic circuits in the horizontal direction. May be provided with a connection for connection between the output of the logic circuit row of (1) and the input of the logic circuit row of the next stage.
[0015]
In addition, any combination of the above-described components, and the expression of the present invention expressed as a method, an apparatus, a system, or a computer program are also effective as embodiments of the present invention.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
The embodiment relates to a reconfigurable circuit having an ALU (Arithmetic Logic Unit) array as a basic element. In this type of circuit, one ALU constitutes one logical unit, and the logical unit can selectively execute a plurality of arithmetic operations. Configuration time is saved because mapping is possible. Mapping refers to loading and setting an instruction set of a program to be executed by the reconfigurable circuit and a connection data set required in the reconfigurable circuit to implement the instruction set in the ALU array.
[0017]
A characteristic of the embodiment is that the multiplier is intentionally removed from the arithmetic operation circuit to be built in the ALU, and the multiplication is replaced by a shift operation. Generally, the area occupied by the multiplier in the ALU is very large, and if the multiplier is built in every ALU, the area of the entire reconfigurable circuit becomes very large, which is not advantageous in terms of cost and function. Also, when a program is loaded, there will be many multipliers that are not used, so there is room for improvement in terms of circuit utilization efficiency. Further, the multiplication takes a long processing time, the processing is rate-limited by a path passing through the multiplier, and the overall circuit design becomes difficult. The shift operation is also advantageous in terms of smoothing the processing load. However, even in the shift operation, if a variable length bit is used as in a barrel shifter, the circuit scale tends to be large. Therefore, in the embodiment, the number of shifts is limited to one or two.
[0018]
To be able to substitute multiplication with shift, at least one of the multiplier or the multiplicand must be a constant. Therefore, in the embodiment, it is assumed that such a multiplication is detected by a compiling unit described later and is assigned to an ALU without a multiplier. Multiplication by variables may be assigned to an ALU having a multiplier, and two types of ALUs may be appropriately combined. Hereinafter, an ALU without a multiplier and a program load for the ALU will be mainly described.
[0019]
FIG. 1 is a configuration diagram of an integrated circuit device 10 and an external control device 24 according to the embodiment. The external control device 24 creates data for setting the circuit configuration of the integrated circuit device 10 and supplies the data to the integrated circuit device 10. In particular, the compiling unit 20 or the entire external control device 24 including the compiling unit 20 , Can be understood as a data conversion device that creates setting data.
[0020]
The integrated circuit device 10 includes a reconfigurable circuit 12, a setting data storage unit 16 for storing setting data 17 for reconfiguring the reconfigurable circuit 12, and a setting for loading the setting data 17 into the reconfigurable circuit 12. Unit 14. The external control device 24 includes a control unit 18, a compiling unit 20, and a program storage unit 22.
[0021]
The program storage unit 22 of the external control device 24 holds various programs 19 to be executed by the integrated circuit device 10. The compiling unit 20 compiles the program 19 stored in the program storage unit 22, converts it into a data flow graph 21, and stores it in the program storage unit 22. As will be described later, the data flow graph 21 shows the flow of calculation of input variables and constants in a graph structure.
[0022]
The data flow graph 21 is converted into setting data 17 for mapping to the circuit configuration of the reconfigurable circuit 12, supplied to the setting unit 14 of the integrated circuit device 10 via the control unit 18, and stored in the setting data storage unit 16. Is stored in A plurality of setting data 17 are stored in the setting data storage unit 16 in advance corresponding to the data flow graph 21 of the operation to be processed. The setting section 14 reconfigures the reconfigurable circuit 12 by reading the setting data 17 from the setting data storage section 16 as appropriate and loading the setting data 17 into the reconfigurable circuit 12. The reconfigured reconfigurable circuit 12 performs an operation based on the loaded setting data 17.
[0023]
FIG. 2 is a configuration diagram of the reconfigurable circuit 12. The reconfigurable circuit 12 includes a data input unit 40 for loading setting data, an ALU array 42 in which a plurality of ALU columns are arranged in a plurality of stages, and a connection switch 44 provided in each stage of the array. By the connection connection 30, the output of the preceding ALU row and the input of the following ALU row can be arbitrarily connected by setting. Although the connection connection 30 is selected by the connection switch 44, hereinafter, it is abbreviated as "setting by the connection connection 30". As described above, each ALU includes at least an adder, a subtractor, and a shifter, but does not include a multiplier. The shifter has a configuration limited to one-bit or two-bit shift, thereby reducing the circuit scale.
[0024]
As shown in the figure, Y ALUs are arranged in the horizontal direction and X ALUs are arranged in the vertical direction, and input variables and constants are input to the first stage ALU11, ALU12, ..., ALU1Y. , A predetermined calculation is performed by the setting. The output of the calculation result is input to the second-stage ALU 21, ALU22,..., ALU2Y according to the connection set in the first-stage connection connection 30. The first-stage connection connection 30 is configured such that an arbitrary connection relationship between an output of the first-stage ALU array and an input of the second-stage ALU array can be realized, and a specific connection is determined by setting. Becomes effective. Hereinafter, the configuration is the same up to the connection connection 30 of the (X-1) th stage, and the ALU column of the Xth stage which is the final stage outputs the final result of the operation. Each ALU has a path (not shown) for directly outputting an input in order to execute a mov operation described later.
[0025]
The setting data 17 for mapping the data flow graph 21 to the reconfigurable circuit 12 includes information for selecting the operation of each ALU, information for selecting the connection connection between the ALU columns, and input to the first-stage ALU column. Variables and constant values.
[0026]
Now, consider the following program to be executed.

FIG. 3 shows a data flow graph corresponding to the above program. In the figure, constants, variables and operators are circled, mul indicates multiplication, and add indicates addition. If this is directly mapped to the reconfigurable circuit 12, the state shown in FIG. 4 is obtained. However, in the present embodiment, since there is no multiplier, multiplication is realized by a shifter.
[0027]
x = 2 × a and y = 5 × b are obtained by using a bit shift.
x = a << 1, y = b + (b << 2)
Can be written as Here, “<<” is a left bit shift. FIG. 5 shows a data flow graph corresponding to this notation, and FIG. 6 shows a reconfigurable circuit 12 mapped based on FIG. In the figure, mov is the NOP operation described above. The method of actually mapping the circuit from the data flow graph is as follows.
[0028]
1. Variables and constants existing at the input end of the data flow graph are assigned to the data input unit 40.
2. In the data flow graph, the operation preceding the i-th → from the input end is assigned to the (i + 1) -th stage ALU.
3.2. As an exception to the above, when the numbers of → in a plurality of paths reaching a certain operation are different, such as i and j, the number is set to the larger one. Now, when i <j, the operation is assigned to the (j + 1) th stage.
4.3. In order to match the number of stages, (ji) mov operations equivalent to NOP are inserted into the path on the side of i.
[0029]
As described above, in the present embodiment, multiplication in the form of a constant × variable is first converted into a bit shift and an addition, which is converted into a data flow graph and mapped to the reconfigurable circuit 12. As a result, multiplication can be performed by a shifter with a short processing time even if no multiplier is present. Hereinafter, since the method of mapping a circuit from the data flow graph is the same, the following description will be made only with the data flow graph.
[0030]
Next, consider the execution of the following program.

Since 8 × a = a << 3, FIG. 7 shows this in a data flow graph. However, since the 3-bit shift cannot be executed by one ALU in the present embodiment, the data flow graph of FIG. 7 is converted as shown in FIG. 8 and decomposed into a shift operation of 2 bits or less. This consideration has the effect of reducing the circuit scale in the sense that the number of instructions to be implemented in the ALU is reduced.
[0031]
Next, consider the execution of the following program.

10 × a = (a << 1) + (a << 1 << 2), and the data flow graph is as shown in FIG. Here, the two operations 50 surrounded by a bold line indicate that the left shift is performed the same number of times with respect to the input “a”. Therefore, the merge is performed as shown in FIG. 10 to simplify the processing.
[0032]
Next, consider the execution of the following program.

15 × a = (a << 3) + (a << 2) + (a << 1) + a, and the data flow graph is shown in FIG. However, here, when a so-called minimal expression in which the number of zeros is the largest when expressed in a binary number, 15 is as follows.
15 = (1111)₂= (1000N1)₂
However, "N1" represents -1. Therefore, the above program is represented by the following bit shift.
15 × a = (a << 4) −a
FIG. 12 is a data flow graph corresponding to this equation, where sub indicates subtraction. As described above, by using the minimal expression and the subtractor as necessary, the processing can be further simplified, and the ALU to be used can be reduced.
[0033]
FIG. 13 shows a procedure for generalizing the above processing and converting multiplication of a constant × variable into processing of a minimal expression by a shifter. The processing is roughly divided into four stages, and FIG. 13 mainly shows the first stage processing.
[0034]
[First stage] Multiplication → 1-bit shifter conversion
Convert the multiplication node to a 1-bit shifter, addition and sign reversal node. The sign inversion node is used temporarily, but is converted to a subtraction node in the fourth stage. In general, the integer is A = sΣ^N _k-1a_k・ 2^kIt is expressed as Where s = 1 or -1, a_kThe value of = 0 is 1. Here, it is assumed that A ≠ 0 as an initial value. In the following procedure, the process proceeds to the step immediately below unless otherwise specified. In FIG. 13, Step is abbreviated as S.
[0035]
Set initial values to the variables below Step1.
c ← 0, cnt ← 0, n ← 0, flag ← 0, node array: NL ← empty
c is a carry bit used during processing, cnt is a counter, NL is an array for assigning operations to nodes, n is a pointer to NL, and flag is a status flag.
[0036]
Step 2 If A = 0 and c = 0, the process ends.
Step3 a₀If = c, the process proceeds to Step 11.
Step4 If cnt ≠ 0, proceed to Step6.
Step 5 Create a mov node whose input is a variable in NL [n]. Further, the process proceeds to Step 7 with n ← n + 1.
[0037]
Step 6 cnt consecutive 1-bit shifter nodes are created in NL [n] to NL [n + cnt-1]. The input of NL [n] is a variable, and the input of the other nodes is the output of the previous shifter node. It is assumed that n ← n + cnt.
Step7 a₁= 0 and S = -1 or a₁If ≠ 0 and S = 1, a sign inversion node is created in NL [n], and n ← n + 1.
Step 8 If flag = 0, set flag ← 1 and proceed to Step 10.
In Step 9 NL [n], NL [n_old-1] and an output of NL [n-1] as inputs. It is assumed that n ← n + 1.
[0038]
Step10 n_old← n.
Step11 a₀+ A₁If + c ≧ 2, c ← 1; otherwise, c ← 0.
Step12 a₀← a₁, A₁← a₂, ..., a_N-1← a_N, A_N← 0 and cnt ← cnt + 1.
Return to Step13 Step2.
[0039]
[2nd stage] Merge of same input and same instruction node
If two or more nodes have the same input value and the same instruction for n node arrays NL, they are combined into one.
[0040]
[Third stage] Merging bit shifters
Continuous 1-bit shifters are combined into fixed-length n-bit shifters (n ≧ 2).
[0041]
[Phase 4] Merge into subtraction node
The process of connecting the sign inversion node to the addition node is summarized in the subtraction node. The addition equation is represented as in equation (1).
[0042]
output = input1 + input2 (1)
i) When one of the inputs to the addition node is a sign reversal node
input1 = -input1 '
Here, equation (1) is

According to equation (2), conversion to a subtraction node is performed.
ii) When both inputs to the addition node are sign inversion nodes
input1 = -input1 '
input2 = -input2 '
Here, equation (1) is

From Expression (3), conversion is performed to an addition node and a sign inversion node.
[0043]
The following is an example of the conversion from multiplication to shifter by the above procedure. Here, a × 23 is assumed. 23 is a binary number (10111)₂It is. Hereinafter, the state of the array NL according to the value of n will be described only for simplicity.
[0044]
[First stage] Multiplication → 1-bit shifter conversion
Starting with n = 0, a mov node is created (S5). FIG. 14 shows NL [0]. Thereafter, n is incremented.
After n ← 1, a sign reversal (neg) node is created (S7). FIG. 15 shows a state in which NL [1] has been added. After this,
n ← 2, flag ← 1, N_old← 2, c ← 1, A ← (1011)₂, Cnt ← 1
And a shifter node is created (S6). In the next loop,
n ← 3, c ← 1, A ← (101)₂, Cnt ← 2
And a shifter node is similarly created (S6). In the next loop,
n ← 4, c ← 1, A ← (10)₂, Cnt ← 3
And a shifter node is similarly created (S6). The shifter is a one-bit shifter. At this point, the array is in the state of FIG.
[0045]
After n ← 5, a sign reversal (neg) node is created (S7). At this point, the array is in the state of FIG.
After n ← 6, an add node is created (S9). The arrangement is shown in FIG.
After n ← 7, N_old← 7, c ← 1, A ← (1)₂, Cnt ← 4, and a shifter node is created (S6).
After n ← 8, c ← 1, A ← (0)₂, Cnt ← 5, and a shifter node is created (S6). Hereinafter, a shifter node is similarly created for n = 9, 10, and 11 (S6). The arrangement is now in the state of FIG.
[0046]
After n ← 12, an add node is created (S9). The arrangement is now in the state of FIG. After this, n ← 13, N_old← 13, c ← 0, A ← (0)₂, Cnt ← 6, and the process ends.
[0047]
[2nd stage] Merge of same input and same instruction node
In FIG. 20, NL [2] and NL [7], that is, the rows of n = 2 and 7 have the same input and the same instruction. FIG. 21 is obtained by detecting and merging this state. Further, in FIG. 21, since NL [3] and NL [8] are the same input and the same instruction, merging results in FIG. Similarly, by repeatedly merging, the state shown in FIG. 23 is obtained. The above merging process is also performed by the compiling unit 20.
[0048]
[Third stage] Merging bit shifters
From FIG. 23, continuous 1-bit shifters are detected and replaced with 2-bit shifters. Here, the shifter 2 represents a 2-bit shifter. As a result, the state shown in FIG. 24 is obtained.
[0049]
[Phase 4] Merge into subtraction node
In FIG. 24, since NL [6] = NL [1] + NL [5] =-NL [0] -NL [4] =-(NL [0] + NL [4]), the order is changed from the add instruction to the neg instruction. After conversion, the state shown in FIG. 25 is obtained. Here, in order to erase the rows of n = 1 and 5 where the neg instruction is present, ie, NL [1] and NL [5], the rows that receive them, ie, NL [6] are detected, and then NL is detected. [1] and NL [5] are traced back to their inputs, and the neg instruction is erased.
[0050]
Thereafter, since the neg instruction is still in NL [7], NL [12] that receives the neg instruction is detected, and NL [7] is similarly traced to the input and represented by NL [6]. That is, since NL [12] = NL [7] + NL [10] =-NL [6] + NL [10] = NL [10] -NL [6], the neg instruction becomes a subtraction (sub) instruction as a result. Conversion is possible, and the state shown in FIG. 26 is obtained. The processing is completed as described above. As a result, a × 23 becomes a data flow graph shown in FIG. Then, the data flow graph may be mapped to the circuit.
[0051]
In the reconfigurable circuit 12 described above, an ALU having a high-performance computing capability can be used as a basic cell. At that time, the configuration can be performed by one clock setting operation. The circuit can be reconfigured.
[0052]
In the present embodiment, the ALU does not have a multiplier, but the reconfigurable circuit 12 may be configured by mixing with an ALU having a multiplier. In this case, the variable × variable type multiplication may be performed by a multiplier, and the constant × variable type multiplication may be performed by a shift operation.
[0053]
The present invention has been described based on the embodiments. It should be understood by those skilled in the art that the embodiments are exemplifications, and that various modifications can be made to the combination of each component and each processing process, and that such modifications are also within the scope of the present invention. .
[0054]
【The invention's effect】
According to the present invention, it is possible to provide a reconfigurable circuit with improved performance, an integrated circuit device equipped with the reconfigurable circuit, and a data conversion device for setting data in the reconfigurable circuit.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an integrated circuit device and an external control device according to an embodiment.
FIG. 2 is a configuration diagram of the reconfigurable circuit of FIG. 1;
FIG. 3 is a diagram showing a data flow graph representing a process of a certain program.
FIG. 4 is a configuration diagram of a reconfigurable circuit mapped according to the data flow graph of FIG. 3;
FIG. 5 is a diagram showing a data flow graph representing the processing of another program.
6 is a configuration diagram of a reconfigurable circuit mapped according to the data flow graph of FIG. 5;
FIG. 7 is a diagram showing a data flow graph representing the processing of yet another program.
FIG. 8 is a diagram showing a data flow graph obtained by partially rewriting the data flow graph of FIG. 7;
FIG. 9 is a diagram showing a data flow graph representing the processing of yet another program.
FIG. 10 is a diagram showing a data flow graph obtained by integrating overlapping processes of the data flow graph of FIG. 9;
FIG. 11 is a diagram showing a data flow graph representing the processing of yet another program.
12 is a diagram showing a data flow graph obtained by changing the data flow graph of FIG. 11 to a minimal expression.
FIG. 13 is a flowchart showing a process for converting a data flow graph into a minimal expression.
FIG. 14 is a diagram showing a state in which an array indicating an operation to be assigned to an ALU is being formed according to the flowchart of FIG. 13;
FIG. 15 is a diagram illustrating a state in which an array indicating an operation to be assigned to an ALU is being formed according to the flowchart of FIG. 13;
FIG. 16 is a diagram illustrating a state in which an array indicating an operation to be assigned to an ALU is being formed according to the flowchart of FIG. 13;
17 is a diagram illustrating a state in which an array indicating an operation to be assigned to an ALU is being formed according to the flowchart of FIG. 13;
FIG. 18 is a diagram illustrating a state in which an array indicating an operation to be assigned to an ALU is being formed according to the flowchart of FIG. 13;
19 is a diagram illustrating a state in which an array indicating an operation to be assigned to an ALU is being formed according to the flowchart of FIG. 13;
FIG. 20 is a diagram illustrating a state in which an array indicating an operation to be assigned to an ALU is being formed according to the flowchart of FIG. 13;
FIG. 21 is a diagram showing an array obtained by merging the same input and the same instruction node in FIG. 20;
FIG. 22 is a diagram showing an array obtained by merging the same input and the same instruction node in FIG. 21;
FIG. 23 is a diagram showing an array obtained by merging the same input and the same instruction node in FIG. 22;
FIG. 24 is a diagram showing an array obtained by merging bit shifters in FIG. 23;
FIG. 25 is a diagram showing an array in the process of erasing a neg node in FIG. 24;
FIG. 26 is a diagram showing an array obtained as a result of deleting a neg node in FIG.
FIG. 27 is a diagram showing a data flow graph that minimally expresses a × 23.
[Explanation of symbols]
Reference Signs List 10 integrated circuit device, 12 reconfigurable circuit, 14 setting unit, 16 setting data storage unit, 17 setting data, 18 control unit, 19 program, 20 compiling unit, 21 data flow graph, 22 program storage unit, 24 external control device , 30 connection wiring, 40 data input section, 42 ALU array, 44 connection switch.

Claims (7)

An array of logic circuits, each of which can selectively perform a plurality of arithmetic logic functions;
A connection unit that holds a connection relationship between the logic circuits,
Wherein a bit shifter is mounted in place of the multiplier in any of the logic circuits. 2. The reconfigurable circuit according to claim 1, wherein the number of shifts by said bit shifter is fixed. The reconfigurable circuit according to claim 1, wherein a subtractor is mounted on one of the logic circuits. 4. The reconfigurable circuit according to claim 1, wherein a desired multiplication is minimally expressed, and an operation corresponding to the multiplication is configured in the array by using the bit shifter. An array of logic circuits each capable of selectively executing a plurality of arithmetic logic functions, and a reconfigurable circuit including a connection unit that holds a connection relationship between the logic circuits,
A storage unit that stores setting data for setting a function of each logic circuit in the reconfigurable circuit and an input / output connection relationship between the logic circuits,
A setting unit that reads the setting data from the storage unit and loads the setting data into the reconfigurable circuit,
In the reconfigurable circuit, a bit shifter is mounted instead of a multiplier in any one of the logic circuits. 6. The integrated circuit device according to claim 5, wherein the setting data is data corresponding to an expression using a bit shift instead of multiplication in a graph representing a data flow of multiplication to be performed. An apparatus for generating setting data for causing a reconfigurable circuit to execute a desired process,
A data conversion device, comprising: a compiling unit that converts multiplication to be performed in the reconfigurable circuit into a format that does not include multiplication and includes bit shift.

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