JP2010134713A - Arithmetic processing apparatus and conversion device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently execute multiplication in an arithmetic processing apparatus with an arithmetic logical unit including a plurality of computing elements. <P>SOLUTION: The arithmetic processing apparatus includes an arithmetic logical unit 10 which is capable of changing a function in accordance with setting data supplied from the outside. The arithmetic logical unit 10 includes first computing elements 11 to 46 capable of selectively executing various arithmetic logical operations except multiplication and second computing elements 61 and 71 capable of executing multiplication independently. The first computing elements 11 to 46 may constitute a first computing element array of (x rows)×(y columns) wherein x is an integer equal to or larger than 2 and y is an integer equal to or larger than 2. The second computing elements 61 and 71 may constitute a second computing element column or a second computing element array of (m rows)×(n columns) wherein m is a natural number equal to or smaller than x and n is a natural number. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an arithmetic processing device having a plurality of arithmetic units and a conversion device that generates setting data to be set in the arithmetic processing device from a source program.

  In recent years, development of an arithmetic processing device including an arithmetic unit having a plurality of arithmetic units (hereinafter appropriately referred to as ALU (Arithmetic Logic Unit)) has been advanced. In such an arithmetic processing device, setting data is supplied from the control unit to the arithmetic unit, whereby the ALU and the connection unit in the arithmetic unit are controlled, and the arithmetic unit constitutes an intended circuit as a whole.

Conventionally, a configuration in which each ALU included in the arithmetic unit does not have a multiplication function is common (see, for example, Patent Documents 1 to 3 and Non-Patent Document 1). If the ALU has a multiplication function, the circuit scale and power consumption will be increased.
JP 2004-220377 A JP 2007-213594 A JP-A-2005-275698 Kazuhisa Iizuka, Katsunori Hirase, Makoto Kosone, Tatsuo Hiramatsu, “Realization of Broadcast Receiver Using ALU Array Architecture LSI”, IEICE Technical Report Vol.108, No.172, pp.43-47 (SR2008- 24), Jul. 2008

  In the above-described configuration, multiplication is performed by developing a multiplication formula. For example, the multiplication is performed by converting the multiplication expression into a combination expression of shift operation and addition / subtraction. However, such an approach has not been efficient for applications where multiplication is frequently used, such as filtering. In the above approach, multiplication cannot be executed unless a plurality of calculation steps are performed using a plurality of ALUs, which leads to a delay in processing time and a decrease in utilization efficiency of the ALU included in the calculation unit.

  The present invention has been made in view of such a situation, and an object of the present invention is to provide a technique capable of efficiently performing multiplication in an arithmetic processing device including an arithmetic unit including a plurality of arithmetic units.

  An arithmetic processing device according to an aspect of the present invention is an arithmetic processing device including an arithmetic unit that can change a function according to setting data supplied from the outside, and the arithmetic unit includes a plurality of types of arithmetic logic except for multiplication. A plurality of first computing units capable of selectively executing an operation, and at least one second computing unit capable of executing a multiplication alone.

  Another aspect of the present invention is a conversion device. This device is a conversion device that converts a source program into setting data to be processed by an arithmetic processing device, and executes a multiplication process included in the source program using a shift arithmetic function of the first arithmetic unit. And a determination unit that determines whether to execute using the multiplication function of the second arithmetic unit, and a setting data generation unit that converts the multiplication process into setting data according to the determination result by the determination unit.

  Yet another embodiment of the present invention is also a conversion device. This device is a conversion device that converts a source program into setting data to be processed by an arithmetic processing device, and executes a multiplication process included in the source program using a shift arithmetic function of the first arithmetic unit. And a determination unit that determines whether to execute using the multiplication function of the second arithmetic unit, and a setting data generation unit that converts the multiplication process into setting data according to the determination result by the determination unit. The determination unit executes the multiplication process with a small number of rows based on the number of rows of the first arithmetic unit array among the executions using the multiplication function of the second arithmetic unit, which is executed using the shift arithmetic function of the first arithmetic unit. Select the number that can be executed.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between a method, an apparatus, a system, a recording medium, a computer program, etc. are also effective as an aspect of the present invention.

  According to the present invention, multiplication can be efficiently executed in an arithmetic processing device including an arithmetic unit including a plurality of arithmetic units.

  FIG. 1 is a block diagram showing a configuration of an arithmetic processing apparatus 100 according to Embodiment 1 of the present invention. The arithmetic processing device 100 includes an arithmetic unit 10, a control unit 20, and a storage unit 30.

  The calculation unit 10 performs a predetermined calculation based on setting data (hereinafter, appropriately referred to as command data) supplied from the control unit 20. The arithmetic unit 10 constitutes a reconfigurable circuit whose function can be dynamically changed according to the command data. The detailed configuration of the calculation unit 10 will be described later.

  The control unit 20 holds command data input from the outside, and sequentially supplies the held command data to the calculation unit 10. The command data may be data converted from a source program by a conversion device 200 (see FIG. 9) described later.

  The storage unit 30 holds calculation data processed by the calculation unit 10. This calculation data is not limited to data indicating the final calculation result, but includes data in the middle of calculation. Further, the calculation data may be a variable or a constant.

  FIG. 2 is a diagram illustrating a first configuration example of the calculation unit 10 according to the related art. The arithmetic unit 10 according to the first configuration example includes a plurality of first arithmetic units (denoted as ALU in FIGS. 2 to 8) 11 to 46 and a plurality of connection units (denoted as SW in FIGS. 2, 4, and 6 to 8). ) 51-54. The first computing units 11 to 46 constitute a first computing unit array having x (x is an integer of 2 or more) rows × y (y is an integer of 2 or more) columns. In FIG. 2, a first computing element array of 4 rows × 6 columns is constructed. Hereinafter, one row of computing units including y first computing units will be referred to as a first computing unit column as appropriate. The configurations of the first computing units 11 to 46 and the connection units 51 to 54 are dynamically changed by the command data.

  Each of the connection portions 51 to 54 is provided between two adjacent first arithmetic unit rows. Each connection part 51-54 sets the connection relation of the output of the 1st computing unit contained in the 1st computing unit row | line | column of the front | former stage, and the input of the 1st computing unit contained in the 1st computing unit row | line | column of a back | latter stage. The lowermost first computing element row is connected to the uppermost first computing element row through the connection unit 51 in the same manner as the other stages.

  The processing in the first computing element array is performed for each stage, and the result processed in the first computing element row in the first stage is passed to the first computing element row in the second stage via the connection unit 52. After that, the processing is performed by the first computing element row in the second stage. Each stage of processing is performed every clock. When a four-stage ALU array is used, four independent processes (hereinafter referred to as threads) can operate. For example, after thread 1 is processed by the first stage of the first arithmetic unit, after the next clock, thread 1 is processed by the first stage of the second arithmetic unit and thread 2 is processed by the first stage. Processed by the first arithmetic unit array.

  Each first arithmetic unit is an arithmetic logic circuit capable of selectively executing a plurality of types of multi-bit operations, and includes a plurality of types such as addition / subtraction, comparison operation, logic operation, shift operation, selection operation, and auxiliary operation of multiplication operation. The multi-bit operation can be selectively executed by setting. Details of the auxiliary operation of the multiplication operation will be described later.

  The first arithmetic unit cannot execute a multiplication operation. The multiplication operation here means a decimal multiplication and does not include a binary multiplication. Since the first arithmetic unit has a shift operation function, when the multiplier described in decimal is a multiplier of 2, as a result, the multiplication operation can be completed alone, but the multiplier is not a multiplier of 2 The single unit cannot complete the multiplication operation. In this specification including this consideration, it is defined that the first arithmetic unit does not have a multiplication operation function.

  FIG. 3 is a diagram illustrating a second configuration example of the calculation unit 10 according to the related art. The calculation unit 10 according to the second configuration example includes a plurality of first calculation units 11 to 46 and a plurality of connection units (shown only by arrows in FIGS. 3 and 5) 51a to 54a. Also in FIG. 3, the first computing units 11 to 46 constitute a first computing unit array of 4 rows × 6 columns.

  The configuration of the calculation unit 10 according to the second configuration example of the prior art is basically the same as that of the calculation unit 10 according to the first configuration example of the conventional technology. However, in the second configuration example, the connection units 51a to 54a are the first ones. Connection between one arithmetic unit is limited. That is, the connection parts 51a to 54a according to the second configuration example limit the output destination of one first computing unit in the preceding stage to three directions, that is, the first computing unit immediately below the succeeding stage and the first computing unit on the left and right. . On the other hand, the connection parts 51-54 which concern on the said 1st structural example do not restrict | limit the output destination of one 1st arithmetic unit of a front | former stage. That is, the output of one first arithmetic unit at the front stage can be input to any first arithmetic unit at the rear stage. Thus, since the connection restriction is applied in the arithmetic unit 10 according to the second configuration example, the number of connections between the first arithmetic units is greatly increased as compared with the arithmetic unit 10 according to the first configuration example. Can be reduced.

  Hereinafter, the calculation unit 10 according to Embodiment 1 of the present invention will be described. The arithmetic unit 10 according to the first embodiment includes a plurality of first arithmetic units and at least one second arithmetic unit (referred to as a multiplier in FIGS. 3 to 8) in addition to the plurality of connection units. The second arithmetic unit constitutes a second arithmetic unit column or a second arithmetic unit array having m (m is a natural number equal to or less than x) rows × n (n is a natural number) columns. For example, one second arithmetic unit may be provided for each of a plurality of rows of the first arithmetic unit array.

  The second arithmetic unit is an arithmetic unit capable of executing a multiplication operation alone. The second arithmetic unit may be an arithmetic unit that exclusively executes multiplication operations, or may be an arithmetic unit that can selectively execute other types of operations in addition to multiplication operations. The multiplication operation here means a multiplication of decimal numbers.

  FIG. 4 is a diagram illustrating a first configuration example of the arithmetic unit 10 according to the first embodiment of the present invention. The computing unit 10 has a configuration in which second computing units 61 and 71 are added to the configuration of the computing unit 10 according to the first configuration example of the related art. In the first configuration example of the first embodiment, the first computing units 11 to 46 constitute a first computing unit array of 4 rows × 6 columns, and the second computing units 61 and 71 are second rows of 2 rows × 1 column. Construct an arithmetic operator string. Here, one second arithmetic unit is provided for every two rows of the first arithmetic unit array.

  FIG. 5 is a diagram illustrating a second configuration example of the arithmetic unit 10 according to the first embodiment of the present invention. This calculating part 10 is the structure which added the 2nd calculators 61 and 71 to the structure of the calculating part 10 which concerns on the 2nd structural example of a prior art. Also in the second configuration example of the first embodiment, the first arithmetic units 11 to 46 configure a first arithmetic unit array of 4 rows × 6 columns, and the second arithmetic units 61 and 71 are second units of 2 rows × 1 column. Construct an arithmetic operator string. Again, one second arithmetic unit is provided for every two rows of the first arithmetic unit array. In FIG. 5, the output destination of the second computing unit 61 is limited to the second computing unit 71 and the first computing unit 36, but in practice, any first computation included in the first stage computing unit row in the third stage. The devices 31 to 36 can also be connected.

  FIG. 6 is a diagram illustrating a third configuration example of the arithmetic unit 10 according to the first embodiment of the present invention. This calculating part 10 is the structure by which the 2nd calculator 61, 62, 71, 72 was added to the structure of the calculating part 10 which concerns on the 1st structural example of a prior art. In the third configuration example of the first embodiment, the first arithmetic units 11 to 46 constitute a first arithmetic unit array of 4 rows × 6 columns, and the second arithmetic units 61, 62, 71, 72 are 2 rows × 2 A second arithmetic unit array of columns is formed. Here, two second arithmetic units are provided for every two rows of the first arithmetic unit array.

  FIG. 7 is a diagram illustrating a fourth configuration example of the arithmetic unit 10 according to the first embodiment of the present invention. This calculating part 10 is the structure by which the 2nd calculator 61 was added to the structure of the calculating part 10 which concerns on the 1st structural example of a prior art. In the fourth configuration example of the first embodiment, the first computing units 11 to 46 constitute a first computing unit array of 4 rows × 6 columns, and one second computing unit is provided.

  FIG. 8 is a diagram illustrating a fifth configuration example of the arithmetic unit 10 according to the first embodiment of the present invention. The computing unit 10 has a configuration in which second computing units 61, 71, 81, and 91 are added to the configuration of the computing unit 10 according to the first configuration example of the related art. In the fifth configuration example of the first embodiment, the first arithmetic units 11 to 46 constitute a first arithmetic unit array of 4 rows × 6 columns, and the second arithmetic units 61, 71, 81, 91 are 4 rows × 1. A second arithmetic unit column of the column is configured. Here, one second arithmetic unit is provided for one row of the first arithmetic unit array.

  As shown in FIG. 3 to FIG. 7, one second arithmetic unit corresponds to a plurality of rows of the first arithmetic unit array because the multiplication arithmetic processing in the second arithmetic unit is the first arithmetic unit. This is because it takes more time than the arithmetic and logic operation processing in FIG. That is, if one second arithmetic unit is associated with one row of the first arithmetic unit array, it is necessary to match the operating speed of the first arithmetic unit with the operating speed of the second arithmetic unit. The speed will drop. In addition, since the circuit scale of the second arithmetic unit is larger than the circuit scale of the first arithmetic unit, there is a demand for not increasing the number of second arithmetic units. However, a reduction in the maximum operating speed of the entire arithmetic unit 10 may be allowed to some extent, and one second arithmetic unit may correspond to one row of the first arithmetic unit array as shown in FIG. In the case of an application having a large number of multiplication operations, the processing time of the entire application may be shortened with the configuration of FIG.

  FIG. 9 is a block diagram showing a configuration of conversion apparatus 200 according to Embodiment 2 of the present invention. The conversion device 200 converts a predetermined source program into command data to be processed by the arithmetic processing device 100 according to the first embodiment. That is, a predetermined source program is compiled into the command data.

  The conversion device 200 includes an extraction unit 210, a determination unit 220, a data flow graph generation unit 230, and a command data generation unit 240. These configurations can be realized in hardware by any computer's CPU, memory, and other LSIs, and in software, they are realized by programs loaded into the memory. Draw functional blocks. Therefore, those skilled in the art will understand that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof.

  The extraction unit 210 extracts a multiplication process from the source program to be compiled. More specifically, a program code describing a multiplication formula is extracted. The determination unit 220 executes the multiplication process extracted by the extraction unit 210 by using the shift operation function of the first arithmetic unit included in the arithmetic unit 10 of the arithmetic processing apparatus 100, or the determination unit 220 includes the first arithmetic unit included in the arithmetic unit 10. It is determined whether to use the multiplication function of two arithmetic units.

  The determination unit 220 executes using the shift operation function of the first arithmetic unit, and executes using the multiplication function of the second arithmetic unit, based on the number of rows of the first arithmetic unit array. Select the one that can execute multiplication with a small number of lines. The determination unit 220 causes the data flow graph generation unit 230 to compile the multiplication process and generate the data flow graph. At this time, the determination unit 220 generates a data flow graph when the multiplication process is executed using the former function and a data flow graph when the latter function is executed. The extraction unit 210 selects the smaller number of rows from the two data flow graphs. This is because the processing time of the multiplication process is shorter when the number of lines is smaller.

  Here, the data flow graph represents the dependency of the execution order between operations, and shows the flow of operations of input variables and constants in a graph structure. In the present specification, the operation after each operation is assigned to the first operation unit and the second operation unit included in the operation unit 10 is referred to as a data flow graph.

  In the above description, the method in which the determination unit 220 actually causes the data flow graph generation unit 230 to generate two data flow graphs and selects which function to use is described. Hereinafter, three methods will be described in which the determination unit 220 selects which function is used by specifying the nature of the multiplication process without causing the data flow graph generation unit 230 to generate a data flow graph. To do.

  First, the first method will be described. When the multiplication process is multiplication of a variable and a constant and the constant is a multiplier of 2, the determination unit 220 selects execution using the shift operation function of the first arithmetic unit, At this time, the execution function is selected using the multiplication function of the second arithmetic unit. The constant is 2, 4, 8, 16, 32,. . . In the case of, the multiplication operation is completed simply by shifting the above variable to the left by a predetermined number of digits, and the constant is. . . , 1/32, 1/16, 1/8, 1/4, 1/2, the multiplication operation is completed simply by shifting the variable to the right by a predetermined number of digits. Usually, since one second arithmetic unit is provided for a plurality of rows of the first arithmetic unit array (see FIGS. 3 to 7), when the multiplication process can be executed by the shift arithmetic function of one first arithmetic unit, This can be executed with a smaller number of rows than when the multiplication operation function of the second arithmetic unit is used.

  Note that in the case of multiplication of variables, the values of those variables depend on the execution result of the program, so the determination unit 220 selects execution using the multiplication function of the second arithmetic unit. The execution may be selected using the auxiliary calculation function of the multiplication operation that the first calculator has. Details of this function will be described later.

  Next, the second method will be described. When the multiplication process is a multiplication of a variable and a constant, and the constant is expressed by a binary number, when the number of 1 is equal to or less than a predetermined set value, the determination unit 220 performs the shift operation of the first arithmetic unit. Select to execute using the function, otherwise select to execute using the multiplication function of the second arithmetic unit. The set value can be set by the designer based on knowledge obtained from experimental results and simulation results.

Hereinafter, an example in which the set value is set to 3 will be described. Consider the case where the constants are “12”, “38”, and “8200”.
12 (binary notation, 1100) = (2 ^ 3 + 2 ^ 2)
38 (binary notation, 100110) = (2 ^ 5 + 2 ^ 2 + 2 ^ 1)
8200 (binary notation, 10000000001000) = (2 ^ 13 + 2 ^ 3)

  When both constants are expressed in binary numbers, since the number of bits in which 1 stands is 3 or less, the determination unit 220 selects to use the shift operation function of the first arithmetic unit. Multiplication operations using any constant can be executed with up to three shift operations and up to two additions / subtractions, and even with the first arithmetic unit array, it can be executed with a relatively small number of rows. it can.

  Next, the third method will be described. The determination unit 220 uses the shift operation function of the first arithmetic unit when the multiplication process is multiplication of a variable and a constant, and the constant can be expressed by a combination of shift operations equal to or less than a predetermined set value. In other cases, execute using the multiplication function of the second arithmetic unit is selected. That is, when the number of terms when the constant is expanded into a polynomial is equal to or less than the set value, the determination unit 220 selects to execute using the shift calculation function of the first calculator. The set value can also be set by the designer based on knowledge obtained from experimental results and simulation results.

Hereinafter, an example in which the set value is set to 2 will be described. Consider the case where the above constants are “252” and “8190”.
252 (binary notation, 11111100) = (2 ^ 8-2 ^ 2)
8190 (binary notation, 1111111111110) = (2 ^ 13-2 ^ 1)

  Since the number of terms when any constant is expanded into a polynomial is 2 or less, the determination unit 220 selects to use the shift operation function of the first operation unit. Any multiplication operation using any constant can be executed with up to two shift operations and one addition / subtraction, and even with the first arithmetic unit array, it can be executed with a relatively small number of rows. .

  In FIG. 9, the data flow graph generation unit 230 converts the extracted multiplication processing into a data flow graph according to the determination result by the determination unit 220. That is, the data flow graph generation unit 230 generates a data flow graph using the function selected by the determination unit 220. The command data generation unit 240 generates command data from the data flow graph.

  Hereinafter, the operation of the conversion apparatus 200 will be specifically described with reference to an actual source program example and a corresponding data flow graph example. The source program example shows an example written in C language.

FIG. 10 is a diagram showing a source program example 1. This source program describes the multiplication of the variable in1 and the variable in2.
FIG. 11 shows an example of a data flow graph when the source program example 1 is executed by the arithmetic unit 10 shown in FIG. 2 or FIG. A node drawn with a dotted line in the data flow graph of FIG. 11 indicates a first arithmetic unit included in the arithmetic unit 10. Here, an example in which an auxiliary operation function of multiplication operation mounted on the first arithmetic unit is used will be described.

  In FIG. 11, a “<<” command is a command for shifting the input data to the left bit. The “And” command is a command that takes a logical product of a plurality of input data. The “mov command” is a command for outputting input data as it is to the next node. The “neg” command is a command for inverting the sign of input data.

The “mul_t” command is a multiplication auxiliary command, and is a command for performing the following processing.
out = (a >> 1) + ((a & 1)? b: 0)
(A and b are input data)
The previous term on the right side of this expression indicates a value obtained by shifting a to the right by 1 bit, and the subsequent term indicates that the least significant bit of a is b when it is 1, and 0 when it is 0. Therefore, when the least significant bit of a is 0, out is a value obtained by shifting a by 1 bit, and when it is 1, out is a total value of a value obtained by shifting a by 1 bit and a value of b.

  The data flow graph of FIG. 11 shows an example in which the multiplication of the 8-bit variable in1 and the 8-bit variable in2 is executed using a writing algorithm. At one node in the first stage, the variable “in1” is shifted 7 bits to the left by the “<<” command. In another node in the first stage, even if data exists above the 9th bit of the variable in2 by the “And” command, the data is masked. In the second and subsequent nodes, the bitwise multiplication is executed from the least significant bit of the variable in2, and the process of adding them is sequentially executed.

  FIG. 12 shows an example of a data flow graph when the source program example 1 is executed by the arithmetic unit 10 shown in FIG. 4 or FIG. A node drawn with an ellipse in the data flow graph of FIG. 12 indicates a second computing unit included in the computing unit 10. The “x” command is a command for multiplying a plurality of input data. In the data flow graph of FIG. 12, the variable in1 and the variable in2 are multiplied by the “x” command at the first stage node of the second computing unit (corresponding to the first stage and the second stage of the first computing unit). Is done.

  The number of rows in the data flow graph is shorter when the multiplication of the variables is performed by using the multiplication operation function of the second arithmetic unit than by the multiplication operation auxiliary function of the first arithmetic unit. . Comparing the data flow graphs of FIG. 11 and FIG. 12, the former requires 9 lines, and the latter requires 2 lines. Note that the larger the bit width of the variable, the greater the number of rows required for the former, and the greater the effect of using the latter.

FIG. 13 is a diagram showing a source program example 2. This source program describes the multiplication of the variable in1 and the constant “8192”.
FIG. 14 shows a data flow graph example when the source program example 2 is executed by the arithmetic unit 10 shown in FIG. 2 or FIG. At the first stage node, the variable “in1” is shifted 13 bits to the left by the “<<” command. Since the constant “8192” is 2 13, the above multiplication can be realized by shifting the variable in1 to the left by 13 bits.

  FIG. 15 illustrates an example of a data flow graph when the source program example 2 is executed by the arithmetic unit 10 illustrated in FIG. 4 or 5. In the data flow graph of FIG. 15, the multiplication of the variable in1 and the constant “8192” is executed by the “x” command at one node corresponding to the second arithmetic unit.

  When the multiplication of the variable and the constant can be realized by one shift operation, it is better to execute the multiplication by using the shift operation function of the first arithmetic unit than by using the multiplication operation function of the second arithmetic unit. The number of rows in the data flow graph is shortened. Comparing the data flow graphs of FIG. 14 and FIG. 15, the former requires one line, and the latter requires two lines.

FIG. 16 is a diagram illustrating a source program example 3. This source program describes the multiplication of the variable in1 and the constant “12345”.
FIG. 17 shows a data flow graph example when the source program example 3 is executed by the arithmetic unit 10 shown in FIG. 2 or FIG. The “−” command is a command for subtracting two input data. The “+” command is a command for adding a plurality of input data. In the data flow graph of FIG. 17, the multiplication of the variable in1 and the constant “12345” is expanded into four left bit shifts, one subtraction, and three additions.

  At the second node in the first stage, the variable “in1” is shifted left by 3 bits by the “<<” command and multiplied by eight. At the first node of the second stage, the variable in1 is subtracted from the value input from the preceding node by the “−” command. At the same time, at the second node in the second stage, the value input from the preceding node by the “<<” command is shifted left by 3 bits and multiplied by eight. At the first node in the third stage, the values inputted from the two nodes in the previous stage are added by the “+” command. At the same time, at the second node in the third stage, the value input from the second node in the previous stage is shifted to the left by 6 bits and multiplied by 64 by the “<<” command. At the first node in the fourth stage, the values inputted from the two nodes in the previous stage are added by the “+” command. At the same time, at the second node in the third stage, the value input from the second node in the previous stage is shifted left by 1 bit and doubled by the “<<” command. At the first node in the fifth stage, the values input from the two nodes in the previous stage are added, and the multiplication is completed.

  FIG. 18 shows an example of a data flow graph when the source program example 3 is executed by the arithmetic unit 10 shown in FIG. 4 or FIG. In the data flow graph of FIG. 18, at the first stage node of the second computing unit (corresponding to the first and second stage of the first computing unit), the variable “in1” and the constant “12345” are set by the “x” command. Is multiplied.

  When the multiplication of the variable and the constant is expanded and converted into a combination of a large number of shift operations and a large number of additions and subtractions, the multiplication of the second arithmetic unit is performed rather than the multiplication using the shift operation function of the first arithmetic unit. The number of rows in the data flow graph is shorter when the multiplication operation function is used. Comparing the data flow graphs of FIG. 17 and FIG. 18, the former requires 5 lines, and the latter requires 2 lines.

  FIG. 19 is a diagram showing a source program example 4. This source program describes the addition of the multiplication result of the variable in1 and the constant “8208” and the multiplication result of the variable in1 and the constant “8200”. “8208” can be expanded as “2 ^ 13 + 2 ^ 4”, and “8200” can be expanded as “2 ^ 13 + 2 ^ 3”.

  FIG. 20 illustrates an example of a data flow graph when the source program example 4 is executed by the arithmetic unit 10 illustrated in FIG. 2 or FIG. In the data flow graph of FIG. 20, at the second node in the first row, the variable “in1” is shifted left by 4 bits by the “<<” command and multiplied by 16. At the same time, at the third node of the first stage, the variable “in1” is shifted left by 3 bits and multiplied by 8 by the “<<” command. At the first node of the second stage, the value input from the second node of the previous stage by the “<<” command is shifted left by 9 bits and multiplied by 512. The second node in the second stage passes through the value input from the second node in the previous stage by the “mov” command. At the same time, at the third node in the second stage, the value input from the third node in the previous stage is shifted 10 bits to the left by the “<<” command and multiplied by 1024. The fourth node in the second stage passes through the value input from the third node in the previous stage by the “mov” command.

  At the second node in the third stage, the values input from the first node and the second node in the previous stage are added by the “+” command. At the same time, at the third node in the third stage, the values inputted from the third and fourth nodes in the previous stage are added by the “+” command. At the third node in the fourth stage, the values input from the second and third nodes in the previous stage are added by the “+” command. Thus, the addition of the multiplication result of the variable in1 and the constant “8208” and the multiplication result of the variable in1 and the constant “8200” is completed.

  FIG. 21 shows a data flow graph example when the source program example 4 is executed by the arithmetic unit 10 shown in FIG. 4 or FIG. In the data flow graph of FIG. 21, at the first stage node of the second computing unit (corresponding to the first and second stage of the first computing unit), the variable “in1” and the constant “8208” by the “x” command. And are multiplied. At the second stage node of the second computing unit (corresponding to the third and fourth stages of the first computing unit), the variable in1 and the constant “8200” are multiplied by the “x” command. At the same time, the third stage node of the first arithmetic unit passes through the value input from the first stage node of the second arithmetic unit by the “mov” command, and the fourth stage node of the first arithmetic unit. Also, the value input from the third node of the first computing unit is passed through by the “mov” command.

  The value input from the third stage node of the first arithmetic unit and the value input from the second stage node of the second arithmetic unit are added at the fifth stage node of the first arithmetic unit. Thus, the addition of the multiplication result of the variable in1 and the constant “8208” and the multiplication result of the variable in1 and the constant “8200” is completed.

  If the expression includes a plurality of multiplications of variables and constants and the number of shift operations when each multiplication is expanded is less than the set value, the plurality of multiplications are executed using the multiplication operation function of the second arithmetic unit. In many cases, the number of rows in the data flow graph is shorter when the shift calculation function of the first calculator is used. This is because a plurality of multiplications can be executed in parallel using the shift calculation function of the first calculator. As shown in FIG. 6, when a plurality of second arithmetic units are provided in one stage, the number of rows in the data flow graph is often shortened by executing using the multiplication arithmetic function of the second arithmetic unit. Comparing the data flow graphs of FIG. 20 and FIG. 21, the former requires four lines, and the latter requires five lines.

  FIG. 22 is a diagram showing a source program example 5. This source program describes addition of a multiplication result of the variable in1 and the variable in2, a multiplication result of the variable in1 and the constant “8208”, and a multiplication result of the variable in2 and the constant “8200”.

  FIG. 23 illustrates a data flow graph example 1 when the source program example 5 is executed by the arithmetic unit 10 illustrated in FIG. 4 or 5. This data flow graph example 1 is an example in which the above three multiplications are executed using the multiplication operation functions of all the second arithmetic units. In the data flow graph of FIG. 23, at the first stage node of the second computing unit (corresponding to the first and second stage of the first computing unit), the variable in1 and the variable in2 are changed by the “x” command. Is multiplied. At the second stage node of the second computing unit (corresponding to the third and fourth stages of the first computing unit), the variable “in1” and the constant “8208” are multiplied by the “x” command. At the same time, the third stage node of the first arithmetic unit passes through the value input from the first stage node of the second arithmetic unit by the “mov” command, and the fourth stage node of the first arithmetic unit. Also, the value input from the third node of the first computing unit is passed through by the “mov” command.

  At the third stage node of the second arithmetic unit (corresponding to the fifth and sixth stages of the first arithmetic unit), the variable “in2” and the constant “8200” are multiplied by the “x” command. In parallel with this, the value of the fifth stage node of the first arithmetic unit is inputted from the fourth stage node of the first arithmetic unit and the first stage node of the second arithmetic unit by the “+” command. And the sixth stage node of the first arithmetic unit passes through the value input from the fifth stage node of the first arithmetic unit by the “mov” command. The value input from the sixth stage node of the first arithmetic unit and the value input from the third stage node of the second arithmetic unit are added at the seventh stage node of the first arithmetic unit. Thus, the addition of the multiplication result of the variable in1 and the variable in2, the multiplication result of the variable in1 and the constant “8208”, and the multiplication result of the variable in2 and the constant “8200” is completed.

  FIG. 24 shows a data flow graph example 2 when the source program example 5 is executed by the arithmetic unit 10 shown in FIG. 4 or FIG. This data flow graph example 2 is an example in which the above three multiplications are executed using both the shift operation function of the first arithmetic unit and the multiplication operation function of the second arithmetic unit. In the data flow graph of FIG. 24, at the fourth node in the first stage of the first computing unit, the variable in1 is shifted left by 4 bits by the “<<” command and multiplied by 16. In parallel with this, at the fifth node of the first stage of the first arithmetic unit, the variable “in2” is shifted left by 3 bits and multiplied by 8 by the “<<” command.

  At the third node of the second stage of the first arithmetic unit, the value input from the fourth node of the previous stage by the “<<” command is shifted left by 9 bits and multiplied by 512. The fourth node in the second stage of the first arithmetic unit passes through the value input from the fourth node in the previous stage by the “mov” command. At the same time, at the fifth node of the second stage of the first arithmetic unit, the value input from the fifth node of the previous stage by the “<<” command is shifted left by 10 bits and multiplied by 1024. The sixth node of the second stage of the first arithmetic unit passes through the value input from the fifth node of the previous stage by the “mov” command.

  At the fourth node in the third stage of the first arithmetic unit, the values inputted from the third node and the fourth node in the previous stage are added by the “+” command. In parallel, at the fourth node of the third stage of the first computing unit, the values input from the fifth and sixth nodes of the previous stage are added by the “+” command. At the same time, the variable in1 and the variable in2 are multiplied by the “x” command at the second node of the second calculator (corresponding to the third and fourth stages of the first calculator).

  The value input from the fifth node of the fourth stage of the first arithmetic unit by the “+” command at the sixth node of the fifth stage of the first arithmetic unit, and the second node of the second arithmetic unit Input values are added. Thus, the addition of the multiplication result of the variable in1 and the variable in2, the multiplication result of the variable in1 and the constant “8208”, and the multiplication result of the variable in2 and the constant “8200” is completed.

  As shown in source program example 5, in the case of an arithmetic expression in which multiplication of a variable and a variable and multiplication of a variable and a constant are mixed, the plurality of multiplications are executed by using only the multiplication operation function of the second arithmetic unit. In many cases, the number of rows in the data flow graph is shortened when the shift operation function of the first operation unit and the multiplication operation function of the second operation unit are used in combination. This is because when the shift operation function of the first arithmetic unit and the multiplication operation function of the second arithmetic unit are used in combination, a plurality of multiplications can be executed in parallel. Comparing the data flow graphs of FIG. 23 and FIG. 24, the former requires 7 lines, and the latter requires 5 lines.

  FIG. 25 is a diagram illustrating a source program example 6. The source program example 6 is similar to the source program example 5. This source program example 6 describes the addition of the multiplication result of the variable in1 and the variable in2, the multiplication result of the variable in1 and the constant “252”, and the multiplication result of the variable in2 and the constant “8190”. .

  FIG. 26 shows a data flow graph example 1 when the source program example 6 is executed by the arithmetic unit 10 shown in FIG. 4 or FIG. This data flow graph example 1 is an example in which the above three multiplications are executed using the multiplication operation functions of all the second arithmetic units. The data flow graph of FIG. 26 has basically the same structure as the data flow graph of FIG. 23, and is the second node of the second arithmetic unit (corresponding to the third and fourth stages of the first arithmetic unit). And the third stage node (corresponding to the fifth stage and the sixth stage of the first computing unit) are different only in that the constant multiplied by the “x” command is changed.

  FIG. 27 shows a data flow graph example 2 when the source program example 6 is executed by the arithmetic unit 10 shown in FIG. 4 or FIG. This data flow graph example 2 is an example in which the above three multiplications are executed using both the shift operation function of the first arithmetic unit and the multiplication operation function of the second arithmetic unit. The data flow graph of FIG. 27 has basically the same structure as the data flow graph of FIG. Hereinafter, differences will be described. At the fourth node of the first stage of the first arithmetic unit, the variable “in1” is shifted left by 2 bits by the “<<” command and multiplied by four. At the same time, at the fifth node of the first stage of the first arithmetic unit, the variable “in2” is shifted left by 1 bit and doubled by the “<<” command.

  At the third node of the second stage of the first computing unit, the value input from the fourth node of the previous stage by the “<<” command is shifted left by 6 bits and multiplied by 64. The sign of the value input from the preceding fourth node is inverted by the “neg” command at the fourth node in the second stage of the first computing unit. At the same time, at the fifth node of the second stage of the first arithmetic unit, the value input from the fifth node of the previous stage by the “<<” command is shifted left by 12 bits and multiplied by 4096. The sixth node of the second stage of the first arithmetic unit inverts the sign of the value input from the fifth node of the previous stage by the “neg” command. The following processing is the same as the data flow graph of FIG.

  Comparing the data flow graphs of FIG. 24 and FIG. 27, in the former, multiplication of a variable and a constant is expanded into two shift operations and one addition, and in the latter, it is expanded into two shift operations and one subtraction. Is done. In the source program example 6 as well, the shift operation function of the first arithmetic unit and the multiplication operation function of the second arithmetic unit are executed in combination rather than performing the plurality of multiplications using only the multiplication operation function of the second arithmetic unit. Doing so will reduce the number of rows in the data flow graph. Comparing the data flow graphs of FIG. 26 and FIG. 27, the former requires 7 lines, and the latter requires 5 lines.

  As described above, according to the present embodiment, in the arithmetic processing device including the arithmetic unit including a plurality of first arithmetic units, the second arithmetic unit capable of executing multiplication alone is mounted, thereby efficiently performing the multiplication. Can be executed automatically. By installing the second arithmetic unit, the scale of the arithmetic unit is increased correspondingly, but the processing time for the multiplication operation is shortened. For applications with many multiplications, it is possible to reduce the overall processing time by installing the second arithmetic unit, and it is possible to increase the utilization efficiency of the plurality of first arithmetic unit arrays included in the first arithmetic unit array. . In this case, the circuit scale of the first arithmetic unit array can be reduced, leading to a reduction in the circuit scale of the entire arithmetic unit.

  Further, when the conversion device compiles the source program, by appropriately determining whether to execute the multiplication using the shift operation function of the first arithmetic unit or the multiplication operation function of the second arithmetic unit The processing time required for the multiplication operation can be optimized. Thereby, power consumption can also be reduced. For example, in the case of multiplication of a variable and a constant, if the multiplication can be realized by a combination of shift operations with a small number of times, it is more processing time to use the shift operation of the first arithmetic unit than to use the multiplication operation function of the second arithmetic unit. Can often be shortened.

  The present invention has been described based on some embodiments. It is understood by those skilled in the art that these embodiments are exemplifications, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. By the way.

  In the above-described embodiment, the second arithmetic unit executes only the multiplication operation, but the second arithmetic unit may execute other arithmetic logic operations.

It is a block diagram which shows the structure of the arithmetic processing apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows the 1st structural example of the calculating part which concerns on a prior art. It is a figure which shows the 2nd structural example of the calculating part which concerns on a prior art. It is a figure which shows the 1st structural example of the calculating part which concerns on Embodiment 1 of this invention. It is a figure which shows the 2nd structural example of the calculating part which concerns on Embodiment 1 of this invention. It is a figure which shows the 3rd structural example of the calculating part which concerns on Embodiment 1 of this invention. It is a figure which shows the 4th structural example of the calculating part which concerns on Embodiment 1 of this invention. It is a figure which shows the 5th structural example of the calculating part which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the converter which concerns on Embodiment 2 of this invention. It is a figure which shows the source program example 1. FIG. It is a figure which shows the example of a data flow graph in the case of performing the source program example 1 in the calculating part shown in FIG. 2 or FIG. FIG. 6 is a diagram illustrating an example of a data flow graph when the source program example 1 is executed by the calculation unit illustrated in FIG. 4 or FIG. 5. It is a figure which shows the example 2 of a source program. It is a figure which shows the example of a data flow graph in the case of performing the source program example 2 in the calculating part shown in FIG. 2 or FIG. 6 is a diagram illustrating an example of a data flow graph when the source program example 2 is executed by the arithmetic unit illustrated in FIG. 4 or FIG. 5. FIG. It is a figure which shows the example 3 of a source program. It is a figure which shows the example of a data flow graph in the case of performing the source program example 3 in the calculating part shown in FIG. 2 or FIG. FIG. 6 is a diagram illustrating a data flow graph example when a source program example 3 is executed by the arithmetic unit illustrated in FIG. 4 or FIG. 5. It is a figure which shows the example 4 of a source program. It is a figure which shows the example of a data flow graph in the case of performing the source program example 4 in the calculating part shown in FIG. 2 or FIG. FIG. 6 is a diagram illustrating an example of a data flow graph when the source program example 4 is executed by the arithmetic unit illustrated in FIG. 4 or FIG. 5. It is a figure which shows the example 5 of a source program. FIG. 6 is a diagram illustrating a data flow graph example 1 when a source program example 5 is executed by the arithmetic unit illustrated in FIG. 4 or FIG. 5. FIG. 6 is a diagram illustrating a data flow graph example 2 when the source program example 5 is executed by the arithmetic unit illustrated in FIG. 4 or FIG. 5. It is a figure which shows the example 6 of a source program. FIG. 6 is a diagram illustrating a data flow graph example 1 when the source program example 6 is executed by the arithmetic unit illustrated in FIG. 4 or FIG. 5. FIG. 6 is a diagram illustrating a data flow graph example 2 in a case where the source program example 6 is executed by the arithmetic unit illustrated in FIG. 4 or FIG. 5.

Explanation of symbols

  10 arithmetic units, 11 first arithmetic unit, 20 control unit, 30 storage unit, 51 connection unit, 61 second arithmetic unit, 100 arithmetic processing unit, 200 conversion unit, 210 extraction unit, 220 determination unit, 230 data flow graph generation Part, 240 command data generation part.

Claims (7)

An arithmetic processing apparatus including an arithmetic unit capable of changing functions according to setting data supplied from the outside,
The computing unit is
A plurality of first arithmetic units capable of selectively executing a plurality of types of arithmetic logic operations excluding multiplication;
At least one second computing unit capable of performing multiplication alone;
An arithmetic processing device comprising: The first computing unit constitutes a first computing unit array of x (x is an integer of 2 or more) rows × y (y is an integer of 2 or more) columns,
2. The second arithmetic unit comprises a second arithmetic unit column or a second arithmetic unit array having m (m is a natural number equal to or less than x) rows × n (n is a natural number) columns. The arithmetic processing unit described. The first computing unit constitutes a first computing unit array of x (x is an integer of 2 or more) rows × y (y is an integer of 2 or more) columns,
The arithmetic processing apparatus according to claim 1, wherein the second arithmetic unit is provided for each of a plurality of rows of the first arithmetic unit array. A conversion device for converting a source program into setting data to be processed by the arithmetic processing device according to any one of claims 1 to 3,
A determination unit that determines whether the multiplication process included in the source program is executed using the shift operation function of the first arithmetic unit or the multiplication function of the second arithmetic unit;
A setting data generation unit that converts the multiplication processing into setting data according to a determination result by the determination unit;
A conversion device comprising:   The determination unit selects execution using the shift operation function of the first arithmetic unit when the multiplication process is multiplication of a variable and a constant, and the constant is a multiplier of 2, and the other 5. The conversion apparatus according to claim 4, wherein execution is selected using a multiplication function of the second arithmetic unit.   The determination unit performs the shift operation of the first arithmetic unit when the multiplication process is multiplication of a variable and a constant, and when the constant is expressed in binary, the number of 1 is equal to or less than a predetermined set value. 5. The conversion apparatus according to claim 4, wherein execution is selected using a function, and execution is performed using a multiplication function of the second arithmetic unit at other times. A conversion device for converting a source program into setting data to be processed by the arithmetic processing device according to claim 2,
A determination unit that determines whether the multiplication process included in the source program is executed using the shift operation function of the first arithmetic unit or the multiplication function of the second arithmetic unit;
A setting data generation unit that converts the multiplication processing into setting data according to a determination result by the determination unit;
The determination unit is executed using the shift operation function of the first arithmetic unit, and is executed using the multiplication function of the second arithmetic unit, based on the number of rows of the first arithmetic unit array. A conversion apparatus that selects one that can execute multiplication processing with a small number of rows.

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