JP4413052B2 - Data flow graph processing apparatus and processing apparatus - Google Patents

Description

  The present invention relates to a reconfigurable circuit whose function can be changed, and more particularly to a technique for processing a data flow graph necessary for setting the operation of the reconfigurable circuit.

  In recent years, development of reconfigurable processors capable of changing hardware operations in accordance with applications has been underway. As an architecture for realizing a reconfigurable processor, there are methods using a DSP (Digital Signal Processor) and an FPGA (Field Programmable Gate Array).

An FPGA (Field Programmable Gate Array) can design circuit configuration relatively freely by writing circuit data after the LSI is manufactured, and is used for designing dedicated hardware. The FPGA includes a lookup table (LUT) for storing a truth table of a logic circuit, a basic cell composed of an output flip-flop, and a programmable wiring resource connecting the basic cells. In the FPGA, a target logical operation can be realized by writing data stored in the LUT and wiring data. However, when an LSI is designed using an FPGA, the mounting area is very large and the cost is high as compared with an ASIC (Application Specific IC) design. Thus, a method has been proposed in which the circuit configuration is reused by dynamically reconfiguring the FPGA (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 10-256383

  For example, in satellite broadcasting, image quality may be adjusted by switching broadcast modes depending on the season. In the receiver, a plurality of circuits are built in hardware for each broadcast mode in advance, and the circuit is switched by a selector according to the broadcast mode for reception. Therefore, the other broadcast mode circuits of the receiver are idle during that time. When switching and using multiple dedicated circuits, such as mode switching, and the switching interval is relatively long, instead of creating multiple dedicated circuits, the LSI can be reconfigured instantaneously at the time of switching. The structure can be simplified to improve versatility, and at the same time the mounting cost can be reduced. In order to meet such needs, the manufacturing industry has attracted attention to dynamically reconfigurable LSIs. In particular, LSIs mounted on mobile terminals such as mobile phones and PDAs (Personal Data Assistance) must be downsized, and if LSIs can be dynamically reconfigured and functions can be switched appropriately according to the application, Mounting area can be reduced.

  The FPGA has a high degree of design freedom in circuit configuration and is general-purpose. On the other hand, to enable connection between all the basic cells, it is necessary to include a control circuit for controlling ON / OFF of the switches. This inevitably increases the mounting area of the control circuit. Further, since a complicated wiring pattern is used for the connection between the basic cells, the wiring tends to be long, and the delay increases because of the structure in which many switches are connected to one wiring. For this reason, FPGA based LSIs are often used only for trial manufacture and experiments, and are not suitable for mass production in view of mounting efficiency, performance, cost, and the like. Furthermore, in the FPGA, it is necessary to send configuration information to a large number of basic cells of the LUT method, so that it takes a considerable time to configure the circuit. For this reason, the FPGA is not suitable for applications that require instantaneous switching of the circuit configuration.

  In order to solve these problems, in recent years, an ALU array called ALU (Arithmetic Logic Unit) in which multi-functional elements having a plurality of basic arithmetic functions are arranged in multiple stages has been studied. In the ALU array, processing flows in one direction from the upper stage to the lower stage, so that wiring that connects the ALUs in the horizontal direction is basically unnecessary. Therefore, the circuit scale can be reduced as compared with the FPGA.

  In the ALU array, the arithmetic function configuration of the ALU circuit and the wiring of the connection part connecting the preceding and succeeding ALUs are controlled by command data, and the intended arithmetic processing can be executed. The command data is generally created based on the data flow graph (DFG: Data Flow Graph) created from a source program written in a high-level program language such as C language.

  The ALU includes a plurality of basic arithmetic elements that respectively perform arithmetic functions such as addition operation and shift operation. An ALU having many basic arithmetic elements can increase the arithmetic performance of the ALU array and increase the versatility of arithmetic processing. On the other hand, increasing the number of basic arithmetic elements of the ALU has a drawback that the circuit scale of the ALU increases accordingly.

  For example, when a basic arithmetic element that executes a multiplication operation function is built in an ALU, the circuit scale of the basic arithmetic element increases, and the circuit scale of the entire ALU array increases. On the other hand, when a multiplication operation is executed with an ALU array that does not have a multiplication operation element, a DFG combining an addition operation, a shift operation, and the like is created and mapped to the ALU array. In this case, the DFG becomes very large, the multiplication process takes time, the high-speed processing is impaired, and the power consumption of the ALU array increases.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a technique relating to a reconfigurable circuit and a processing apparatus that efficiently create a data flow graph and efficiently execute the data flow graph. .

An aspect of the present invention includes a multi-stage arrangement of logic circuits each capable of selectively executing a plurality of arithmetic functions, and a connection unit that sets a connection relationship between an output of a preceding logic circuit and an input of a succeeding logic circuit. A data flow graph processing apparatus for processing a data flow graph supplied to a reconfigurable circuit provided, and expressing a dependency of execution order between operations on the basis of an operation description describing the operation of the processing A means for generating a data flow graph, a means for replacing a group of data flows composed of basic operations in a reconfigurable circuit with one node, and a node included in the group of data flows to be replaced are located at the same stage Means for deleting a node located in the same stage when no operation is assigned to the node to be operated.

Another aspect of the present invention includes a multi-stage arrangement of logic circuits each capable of selectively executing a plurality of arithmetic functions, and a connection unit that sets a connection relationship between an output of the preceding logic circuit and an input of the succeeding logic circuit. And a data flow graph processing unit for processing a data flow graph supplied to the reconfigurable circuit, wherein the data flow graph processing unit describes an operation description describing a processing operation Based on the above, means for generating a data flow graph expressing the dependency of execution order between operations, means for replacing a group of data flows composed of basic operations in a reconfigurable circuit with one node, and A node located in the same stage when no operation is assigned to the node located in the same stage as the node included in the group of data flows to be replaced Characterized in that it comprises means for deleting, the.

  It should be noted that any combination of the above components and the expression of the present invention expressed as a method, apparatus, system, and computer program are also effective as an aspect of the present invention.

ADVANTAGE OF THE INVENTION According to this invention, the technique which processes efficiently the data flow graph required for the operation | movement setting of a reconfigurable circuit can be provided.

  FIG. 1 is a configuration diagram of a processing apparatus 10 according to the embodiment. The processing device 10 includes an integrated circuit device 26 having a function that allows the circuit configuration to be reconfigured. The integrated circuit device 26 is configured as one chip, and includes a reconfigurable circuit 12, a setting unit 14, a control unit 18, an internal state holding circuit 20, an output circuit 22, a first feedback path 24, a delay holding circuit 27, and a second feedback path. 29. The reconfigurable circuit 12 can change the function by changing the setting. The reconfigurable circuit 12 is configured as a logic circuit such as a combinational circuit or a sequential circuit. The first feedback path 24 and the second feedback path 29 function as a feedback path, and connect the output of the reconfigurable circuit 12 to the input of the reconfigurable circuit 12.

  The reconfigurable circuit 12 includes a multi-stage arrangement of logic circuits each capable of selectively executing a plurality of arithmetic functions, and a connection unit capable of setting a connection relationship between the output of the preceding logic circuit and the input of the succeeding logic circuit. Is provided. Structurally, a connection part for setting connection lines between logic circuit strings is provided between the plurality of logic circuit strings. The reconfigurable circuit 12 can change the function by arbitrarily setting the function of each logic circuit arranged in a plurality of stages and the connection between the logic circuits. The logic circuit in the present embodiment is configured to have a combination connection that connects a plurality of basic arithmetic elements that perform each of the arithmetic functions under a predetermined rule.

  The setting unit 14 supplies setting data 40 for configuring a desired circuit to the reconfigurable circuit 12. The setting unit 14 may be configured as a command memory that outputs stored data based on the count value of the program counter. In this case, the control unit 18 controls the output of the program counter. In this case, the setting data 40 may be command data output from the command memory.

  The internal state holding circuit 20 is configured as a sequential circuit such as a data flip-flop (DFF), for example, and receives the output of the reconfigurable circuit 12. The internal state holding circuit 20 is connected to the first feedback path 24 and feeds back the output of the reconfigurable circuit 12 directly to the input of the reconfigurable circuit 12. The internal state holding circuit 20 supplies the output of the reconfigurable circuit 12 to the delay holding circuit 27. The internal state holding circuit 20 includes a selector, and the selector selects data to be sent to the first feedback path 24 and data to be supplied to the delay holding circuit 27 based on a selection instruction from the control unit. The selector may send the same data to both the first feedback path 24 and the delay holding circuit 27.

  The delay holding circuit 27 is a memory and includes a plurality of RAMs for storing output data output from the reconfigurable circuit 12. The delay holding circuit 27 has a function of delaying the output data of the reconfigurable circuit 12 for an arbitrary time. In this example, the delay holding circuit 27 stores data output from the internal state holding circuit 20, but data output directly from the reconfigurable circuit 12 may be stored. The delay holding circuit 27 writes / reads data based on the W / R enable signal and address signal from the control unit 18. The delay holding circuit 27 is connected to the second feedback path 29 and feeds back data to the input of the reconfigurable circuit 12 at a predetermined timing based on a read instruction from the control unit 18. If the setting unit 14 is configured as a command memory, the data of the delay holding circuit 27 may be written / read using command data supplied from the command memory.

  The output circuit 22 is configured as a sequential circuit such as a data flip-flop (DFF), for example, and outputs data output from the reconfigurable circuit 12 to the outside. In this example, the output circuit 22 receives data output from the delay holding circuit 27, but it may receive data directly output from the reconfigurable circuit 12, and may be output from the internal state holding circuit 20. Data may be accepted.

  In the processing apparatus 10, there are two systems for feeding back the output of the reconfigurable circuit 12 to the input of the reconfigurable circuit 12, a first feedback path 24 and a second feedback path 29. Since the first feedback path 24 does not go through the delay holding circuit 27, the output data of the reconfigurable circuit 12 can be fed back at high speed. On the other hand, the second feedback path 29 can supply a data signal to the reconfigurable circuit 12 at an expected timing according to an instruction from the control unit 18. As described above, the first feedback path 24 or the second feedback path 29 is appropriately used depending on the circuit to be reconfigured on the reconfigurable circuit 12.

  The reconfigurable circuit 12 includes a logic circuit whose function can be changed. The plurality of logic circuits may have a structure arranged in a matrix. The function of each logic circuit and the connection relationship between the logic circuits are set based on setting data 40 supplied by the setting unit 14. In the logic circuit, the combination connection for connecting the basic arithmetic elements to each other is also set based on the setting data 40. The setting data 40 is generated by the following procedure.

  A program 36 to be realized by the integrated circuit device 26 is held in the storage unit 34. The program 36 shows an operation description describing the operation of processing in the circuit, and describes a signal processing circuit or a signal processing algorithm in a high-level language such as C language. The compiling unit 30 compiles the program 36 stored in the storage unit 34, converts it into a data flow graph (DFG) 38, and stores it in the storage unit 34. The data flow graph 38 expresses the dependency of execution order between operations in a circuit, and shows the flow of operations of input variables and constants in a graph structure. In general, the data flow graph 38 is created so that the calculation proceeds from top to bottom.

  In the present embodiment, the logic circuit has a plurality of basic arithmetic elements and executes respective arithmetic functions. As operations that are generally used, various operations such as addition operations and subtraction operations can be given, and one of them is a multiplication operation. From the viewpoint of versatility of the reconfigurable circuit 12, it is preferable that each logic circuit includes a basic arithmetic element that performs multiplication. In practice, however, the arithmetic element for multiplication is different from other arithmetic elements such as addition operations. In comparison, the circuit scale is very large. For this reason, the logic circuit is configured without a basic arithmetic element for multiplication, and the multiplication operation in the data flow graph 38 is developed into a form that can be calculated by addition, bit shift, or the like using a writing algorithm or Booth algorithm. There is a need. The expansion of the multiplication operation is executed by the compiling unit 30.

  The data flow graph processing unit 31 searches the data flow graph 38 generated by the compiling unit 30 for a group of data flows having a predetermined rule. A group of data flows is a set of nodes having a predetermined connection relationship between operation nodes, and is registered in the storage unit 34 in advance. The data flow graph processing unit 31 searches for a group of predetermined data flows and replaces them with a number of nodes smaller than the number of nodes constituting the group. At this time, it is preferable to replace with one node from the viewpoint of reducing the number of nodes.

  Note that the node replaced from the group of data flows needs to be a node that can be processed by the logic circuit of the reconfigurable circuit 12. Correspondingly, the logic circuit is configured to have a combination connection for combining a plurality of basic arithmetic elements of its own in a predetermined order in order to process the replaced node. As a result, the logic circuit can have a new arithmetic function executed by a plurality of basic arithmetic elements by having the combination connection without increasing the number of basic arithmetic elements. In other words, a group of data flows having a predetermined rule is registered in advance according to possible combinations of a plurality of basic arithmetic elements in the logic circuit, and the data flow graph processing unit 31 can execute data in one logic circuit. A group of flows can be searched and replaced with one node.

  The setting data generation unit 32 generates setting data 40 from the data flow graph 38. The setting data 40 is data for mapping the data flow graph 38 to the reconfigurable circuit 12 and determines the function of the logic circuit in the reconfigurable circuit 12 and the connection relationship between the logic circuits. The setting data generation unit 32 may generate setting data 40 for a plurality of circuits obtained by dividing one circuit to be generated.

  FIG. 2 is a diagram for explaining setting data 40 of a plurality of circuits formed by dividing one target circuit 42 to be generated. A circuit generated by dividing one target circuit 42 is referred to as a “divided circuit”. In this example, one target circuit 42 is divided into four divided circuits, that is, divided circuit A, divided circuit B, divided circuit C, and divided circuit D. The target circuit 42 is divided according to the calculation flow in the data flow graph 38. In the data flow graph 38, when the calculation flow is expressed in a direction from the top to the bottom, the data flow graph 38 is cut from the top at a predetermined interval, and the cut portion is set as a dividing circuit. The interval to be cut according to the flow is determined to be equal to or less than the number of logic circuit stages in the reconfigurable circuit 12. The target circuit 42 may be divided in the horizontal direction of the data flow graph 38. The width to be divided in the horizontal direction is determined to be equal to or less than the number of logic circuits in the reconfigurable circuit 12 per stage.

  In particular, when the target circuit 42 to be generated is larger than the reconfigurable circuit 12, the setting data generation unit 32 may divide the target circuit 42 so as to have a size that can be mapped to the reconfigurable circuit 12. preferable. The mapping to the reconfigurable circuit 12 can be executed at one time, for example, with one clock. Therefore, in this case, the four divided circuits can be generated with four clocks. The setting data generation unit 32 determines the division method of the target circuit 42 based on the arrangement structure of the logic circuits in the reconfigurable circuit 12 and the data flow graph 38. The arrangement structure of the reconfigurable circuit 12 may be transmitted from the control unit 18 to the setting data generation unit 32 or may be recorded in the storage unit 34 in advance. In addition, the control unit 18 may instruct the setting data generation unit 32 on how to divide the target circuit 42.

  By executing the above procedure, the storage unit 34 stores a plurality of setting data 40 for configuring the reconfigurable circuit 12 as a desired circuit. The plurality of setting data 40 constitute setting data 40a for configuring the dividing circuit A, setting data 40b for configuring the dividing circuit B, setting data 40c for configuring the dividing circuit C, and a dividing circuit D. This is setting data 40d. As described above, the plurality of setting data 40 represent a plurality of divided circuits obtained by dividing one target circuit 42, respectively. By supplying each setting data 40, the dividing circuit can be configured on the reconfigurable circuit 12 with one clock. As described above, by generating the setting data 40 of the target circuit 42 to be generated according to the circuit scale of the reconfigurable circuit 12, it is possible to realize the processing apparatus 10 with high versatility. From another point of view, according to the processing device 10 of the embodiment, it is possible to reconfigure a desired circuit using the reconfigurable circuit 12 having a small circuit scale.

  FIG. 3 shows a general configuration of the reconfigurable circuit 12. The reconfigurable circuit 12 has a multi-stage arrangement of logic circuits each capable of selectively executing a plurality of arithmetic functions, and a connection that can arbitrarily set the connection relationship between the output of the preceding logic circuit and the input of the succeeding logic circuit. Part 52. In the reconfigurable circuit 12, the operation proceeds from the upper stage to the lower stage due to the multistage arrangement structure of the logic circuits. In the present specification and claims, “multi-stage” means a plurality of stages.

  The reconfigurable circuit 12 has an ALU (Arithmetic Logic Unit) as a logic circuit. ALU is an arithmetic logic circuit that can selectively execute multiple types of multi-bit operations, and selectively execute multiple types of multi-bit operations such as logical sum, logical product, bit shift, addition, and subtraction. it can. Each ALU has a selector for setting a plurality of arithmetic functions. In the embodiment, the ALU does not have a function of executing multiplication. This is because the circuit scale of the operation element for multiplication is large. Therefore, the multiplication operation is processed by combining addition, bit shift, bit product operation, and the like. In the illustrated example, the ALU is configured to have two input terminals and one output terminal.

  The reconfigurable circuit 12 is configured as an ALU array of X stages and Y columns in which X ALUs in the vertical direction and Y ALUs in the horizontal direction are arranged. Here, a three-stage 6-column ALU array in which three ALUs in the vertical direction and six ALUs in the horizontal direction are arranged is shown. The reconfigurable circuit 12 includes a connection unit 52 and an ALU column 53. The ALU row 53 is provided in a plurality of stages, and the connection unit 52 is provided between the front and rear ALU rows 53 to set the connection relationship between the output of the previous ALU and the input of the rear ALU.

  In the example shown in FIG. 3, a connection section 52b constituting the second stage is provided between the first-stage ALU row 53a and the second-stage ALU row 53b, and the second-stage ALU row 53b and the third-stage ALU row 53b are provided. Between the two ALU rows 53c, a connecting portion 52c constituting the third stage is provided. In addition, the connection part 52a which comprises a 1st stage is provided above the ALU row | line | column 53a of a 1st stage.

  Input variables and constants are input to the first-stage ALU 11, ALU 12,..., ALU 16, and a set predetermined calculation is performed. The calculation result output is input to the second-stage ALU 21, ALU 22,..., ALU 26 according to the connection set in the second-stage connection unit 52b. In the second-stage connection unit 52b, an arbitrary connection relationship between the output of the first-stage ALU column 53a and the input of the second-stage ALU column 53b, or a combination of predetermined connection relationships is selected. The connection connection is configured so as to realize the established connection relationship, and the desired connection is made effective by setting. The second stage ALU 21, ALU 22,..., ALU 26 receives the output of the ALU column 53a and performs a predetermined calculation. The output of the calculation result is input to the third-stage ALU 31, ALU 32,..., ALU 36 according to the connection set in the connection connection of the third-stage connection section 52c.

  Output data from the third-stage ALU column 53c, which is the final stage, is output to the internal state holding circuit 20. The internal state holding circuit 20 and / or the delay holding circuit 27 inputs output data to the connection unit 52 a via the first feedback path 24 and / or the second feedback path 29. The connection unit 52a sets the connection for connection and supplies data to the first-stage ALU 11, ALU 12,.

  FIG. 4 is a diagram for explaining the structure of the data flow graph 38. In the data flow graph 38, the flow of operations of input variables and constants is expressed step by step in a graph structure. In the figure, operators are indicated by circles. “>>” indicates a bit shift to the right, “<<” indicates a bit shift to the left, “+” indicates addition, and “−” indicates subtraction. The setting data generation unit 32 generates setting data 40 for mapping the data flow graph 38 to the reconfigurable circuit 12. In particular, when the data flow graph 38 cannot be mapped to the reconfigurable circuit 12, the data flow graph 38 is divided into a plurality of regions, and setting data 40 for the divided circuit is generated. In order to realize the flow of calculation by the data flow graph 38 on the circuit, the setting data 40 specifies the logic circuit to which the calculation function is assigned, defines the connection relationship between the logic circuits, and further defines input variables, input constants, and the like. Data. Accordingly, the setting data 40 includes selection information supplied to a selector that selects the function of each logic circuit, connection information for setting the connection of the connection unit 52, necessary variable data, constant data, and the like.

  In this embodiment, since the logic circuit that can selectively execute a plurality of arithmetic functions does not have a basic arithmetic element for executing a multiplication operation, the multiplication operation is performed by the compiling unit 30. The setting data 40 is generated by being expanded into operations such as addition and bit shift that can be processed by the basic arithmetic elements of the logic circuit.

  Returning to FIG. 1, at the time of circuit configuration, the control unit 18 selects and reads a plurality of setting data 40 for configuring one target circuit 42 from the storage unit 34. Here, the control unit 18 sets the setting data 40 for configuring the target circuit 42 shown in FIG. 2, that is, the setting data 40a of the dividing circuit A, the setting data 40b of the dividing circuit B, the setting data 40c of the dividing circuit C, and the dividing circuit. The D setting data 40 d is read from the storage unit 34 and supplied to the setting unit 14. The setting unit 14 stores each setting data 40.

  When the setting unit 14 is configured as a command memory, the control unit 18 gives a program counter value to the setting unit 14, and the setting unit 14 reconfigures the setting data stored in accordance with the counter value as command data. Set to the configurable circuit 12. The setting unit 14 may include a cache memory and other types of memory. In this example, a configuration in which the control unit 18 receives the setting data 40 from the storage unit 34 and supplies the setting data to the setting unit 14 will be described. However, the setting unit 14 is not provided via the control unit 18 in advance. The setting data may be stored in the. In this case, the control unit 18 reads data from the setting unit 14 so that setting data corresponding to the target circuit 42 is supplied to the reconfigurable circuit 12 from among a plurality of setting data stored in advance in the setting unit 14. To control.

  The setting unit 14 sets the setting data 40 in the reconfigurable circuit 12 and causes the reconfigurable circuit 12 to sequentially reconfigure the circuit. As a result, the reconfigurable circuit 12 can execute a desired calculation. The reconfigurable circuit 12 uses an ALU having a high-performance computing capability as a basic cell, and the reconfigurable circuit 12 and the setting unit 14 are configured on one chip, so that the configuration can be performed at a high speed, for example, It can be realized with one clock. The control unit 18 has a clock function, and the clock signal is supplied to the output circuit 22 and the delay holding circuit 27. The control unit 18 may include a quaternary counter and supply a count signal to the setting unit 14.

<Description of operation of reconfigurable circuit>
Hereinafter, the basic operation of the circuit configuration function of the reconfigurable circuit 12 will be described with reference to FIGS. Based on the basic operation of the reconfigurable circuit 12 shown below, a data flow graph processing method necessary for setting the operation of the reconfigurable circuit 12 will be described with reference to FIG. 11 and subsequent drawings.

  FIG. 5 shows a 7-tap FIR filter circuit using front and rear 7 points. Hereinafter, a specific example in which the FIR (Finite Impulse Response) filter circuit is realized by the processing device 10 according to the embodiment will be described. The coefficients of the FIR filter circuit are set symmetrically in the example of FIG.

  FIG. 6 shows a circuit in which the FIR filter circuit shown in FIG. 5 is replaced. The circuit replacement uses the symmetry of the filter coefficient.

  FIG. 7 shows a circuit in which the FIR filter circuit shown in FIG. 6 is further replaced. Here, the replacement is performed focusing on the filter coefficient. Specifically, the coefficient 1/16 is 1/2 × 1/2 × 1/2 × 1/2, 2/16 is 1/2 × 1/2 × 1/2, 8/16 is 1 / Replaced with 2. The calculation of the coefficient 1/2 can be realized by shifting the data to the right by 1 bit. The 1-bit shifter can be formed in a very small space in the ALU compared to the multiple-bit shifter.

  FIG. 8 shows a data flow graph 38a created by compiling the FIR filter circuit shown in FIG. In the figure, “+” indicates addition, “>> 1” indicates 1-bit shift, and “MOV” indicates a through path. As shown, the data flow graph 38a is composed of seven stages of operators.

  FIG. 9 shows an example of the reconfigurable circuit 12. The reconfigurable circuit 12 includes an ALU having two stages and four columns.

  FIG. 10 shows an example in which the data flow graph 38a shown in FIG. 8 is realized by using the reconfigurable circuit 12 of FIG. Since the data flow graph 38a is composed of seven stages and four columns and the reconfigurable circuit 12 is composed of two stages, the data flow graph 38a is divided into four in the vertical direction. In the left-right direction, since the number of columns of the reconfigurable circuit 12 is equal to or less than the number of columns of the data flow graph 38a, there is no need for division. Here, a case where the number of columns of the reconfigurable circuit 12 and the number of columns of the data flow graph 38a are equal is shown. The divided data flow graph can be configured with one clock on the reconfigurable circuit 12.

  First, the setting unit 14 configures the contents of the first stage and the second stage of the data flow graph 38a on the reconfigurable circuit 12 with the setting data 40a. As a result, the first divided circuit is configured in the reconfigurable circuit 12. Subsequently, the setting unit 14 configures the contents of the third stage and the fourth stage of the data flow graph 38a on the reconfigurable circuit 12 with the setting data 40b. As a result, the second divided circuit is configured in the reconfigurable circuit 12. Subsequently, the setting unit 14 configures the contents of the fifth stage and the sixth stage of the data flow graph 38a on the reconfigurable circuit 12 with the setting data 40c. As a result, the third divided circuit is configured in the reconfigurable circuit 12. Finally, the setting unit 14 configures the contents of the seventh stage and the eighth stage (MOV) of the data flow graph 38a on the reconfigurable circuit 12 with the setting data 40d. Thereby, the fourth division circuit is configured in the reconfigurable circuit 12. An output result from the first divided circuit to the third divided circuit is fed back as an input of the next divided circuit.

  In this example, the ALU can be realized with only three types of “+”, “>> 1”, and “MOV”. Since the multi-bit shift is expressed by using the 1-bit shifter a plurality of times, the required ALU functions can be greatly reduced. Thereby, the circuit scale of the reconfigurable circuit 12 can be reduced. As a matter of course, the data flow graph shown in FIG. 7 can be configured on the reconfigurable circuit 12. The above is the basic operation of the reconfigurable circuit 12.

<Description of data flow graph processing function>
Below, the process of the processing apparatus 10 concerning embodiment at the time of performing a multiplication operation is demonstrated. As described above, in the processing apparatus 10 of the present embodiment, the ALU does not have a basic arithmetic element for multiplication, but the multiplication operation is performed as an addition operation or bit originally incorporated in the ALU as the basic arithmetic element. A data flow graph (DFG) for multiplication operation is executed by expanding to nodes such as shift operation. In this embodiment, by replacing a group of data flows composed of a plurality of nodes with one node, the size of the DFG can be reduced, and the arithmetic processing in the reconfigurable circuit 12 can be executed efficiently. Therefore, it is possible to reduce the circuit scale and reduce the power consumption.

  Typical examples of multiplication algorithms include a writing algorithm and a Booth algorithm. In the following, a case where the multiplication program 36 is created by a writing algorithm will be taken as an example.

  FIG. 11 shows a flowchart of a writing algorithm of an m-bit multiplicand x and an n-bit multiplier y. Here, it is assumed that the multiplier y is positive. In order to execute this arithmetic processing, an m-bit multiplicand register, an n-bit multiplier register, and an m + n-bit product register are present. The sign of the multiplier y is determined before the operation. If it is positive, the multiplier y is set for the right n bits of the product register, and 0 is set as the initial value for the left m bits. If the multiplier y is negative, the absolute value is taken as the multiplier y.

  The number of repetitions r is set to an initial value 0 (S10), and it is determined whether or not the LSB (Least Significant Bit) of the product register is 1 (S11). When the LSB of the product register is 1 (Y in S11), the multiplicand x is added to the left m bits of the product register, and the addition result is stored in the left m bits of the product register (S12). Shift right one bit (S13). As a result, the multiplication process for the LSB of the multiplier y is executed. If the LSB of the product register is 0 (N in S11), the product register is similarly shifted to the right by 1 bit (S13). When the LSB is 0, the multiplication result of the LSB of the multiplier y and the multiplicand is 0, so the product register need only be shifted right by 1 bit. At this time, the MSB (Most Significant Bit) of the product register is set to the same numerical value as the MSB before the right shift by 1 bit. The repeat count r is incremented by 1 (S14), and it is determined whether r is equal to n (S15). The case where r is equal to n is a case where writing for all the bits of the multiplier y is completed. When r is less than n (N in S15), the steps from S11 to S14 are repeated, and the LSB multiplication process of the product register is sequentially executed. Performing a 1-bit shift to the right (S13) is equivalent to sequentially performing multiplication from the lower bits while sequentially shifting the bits of the multiplier y from the LSB. When r becomes equal to n (Y in S15), the value stored in the product register becomes the multiplication result, and this flow ends. If the multiplier y is negative, this flow is repeated (n-1) times, that is, (the number of bits of the multiplier y-1) times, and finally the sign-inverted value of the multiplicand x is obtained for the left m bits of the product register. Add to. At this time, the overflow is rounded down and stored in the left m bits of the product register, and then the product register is shifted right by 1 bit.

  FIG. 12 shows an example of a specific processing operation of 4 bits × 4 bits expressed in binary. This processing operation is based on the flowchart shown in FIG. FIG. 12 shows a case where the multiplier y is positive. The multiplicand x is 1011 (−5 in decimal display) and the multiplier y is 0111 (7 in decimal display). When 00000111 is set in the product register ans as an initial setting, a multiplication result can be obtained by a writing algorithm as shown in FIG.

  FIG. 13 shows another example of a specific processing operation of 4 bits × 4 bits expressed in binary. This processing operation is based on the flowchart shown in FIG. FIG. 13 shows a case where the multiplier y is negative, and the multiplicand x is 1011 (−5 in decimal display) and the multiplier y is 1111 (−1 in decimal display). As an initial setting, when 00001111 is set in the product register ans, a multiplication result can be obtained by a writing algorithm as shown in FIG. Since the multiplier y is negative, the multiplication operation is completed by executing the predetermined negative sign process after repeating the processes of S11 to S13 three times.

  FIG. 14 shows a DFG that calculates a multiplicand of 24 bits × multiplier of 4 bits using a writing algorithm. This DFG is developed by the compiling unit 30 so that it can be executed by basic arithmetic elements (basic arithmetic nodes) included in the ALU. In FIG. 14, “1: _Ghissann_ver3_9_1_0_0.y” in the uppermost row indicates a 4-bit multiplier input (y system), and “2: _Ghissann_ver3_9_1_0_0.x” indicates a 24-bit multiplicand input (x system). Further, “_Ghissann_ver3_9_1_0_0.ans” in the last stage indicates a multiplication result. The “add” node in FIG. 14 is an addition operation, the “bgt” node is a magnitude comparison operation (<), and “1: bgt: 20” in the first row represents “y <0”. The “neg” node represents a sign inversion operation, “lsl” represents a left shift operation, and “6: lsl: 20” in the first stage represents a 4-bit left shift “<< 4”. The “mbgt” node is a selection operation for selecting one of two inputs according to the condition of the “bgt” node, and the broken line represents the condition data. The “asr” node is a right shift operation, the “bne” node is an equivalent comparison operation (! =), And the “mbne” node is a selection operation (merge operation) that selects one of the two inputs according to the condition of the “bne” node. The broken line represents the condition data. The “nop” node is a data-through node that does not perform an operation. From FIG. 14, it is understood that 20 stages of nodes are necessary for calculation of 24 bits × 4 bits, and 65 basic operation nodes are necessary.

  FIG. 15 shows a diagram in which a group of data flows having a predetermined rule is surrounded by a dotted line in the data flow graph shown in FIG. In this DFG, there are four node groups 70 arranged according to a predetermined rule. This group of data flows, that is, a group of nodes, has the property that a plurality of calculation functions to be used are the same and the execution order of the calculation functions is also the same. The data flow graph processing unit 31 (see FIG. 1) searches for a node group having a predetermined rule from the DFG shown in FIG.

  FIG. 16 shows the DFG of the node group 70 shown in FIG. As described above, this node group 70 is used in the process of multiplication. The DFG shown in FIG. 16 includes a right 1-bit shift operation, an addition operation, a nop (signal through), a bit product operation with 1, an equivalent comparison operation with 1, and a merge operation. In the present embodiment, this node group 70 is replaced with one new node “mul_t”. Therefore, the node mul_t is a node composed of a plurality of basic operations. As shown in FIG. 15, there are four DFGs having a node mul_t structure in a DFG of multiplication of multiplicand 24 bits × multiplier 4 bits.

  Note that the node mul_t can perform arithmetic processing in one ALU. For this purpose, in the ALU, a plurality of basic arithmetic elements such as a right bit shift arithmetic element, an addition arithmetic element, a bit product arithmetic element, an equivalent comparison arithmetic element, and a merge arithmetic element are connected so as to realize the arrangement relationship of the node group 70. Combination wiring is provided. Since this combination connection only connects the existing basic arithmetic elements, the circuit scale is not so large. For example, when the ALU performs only the addition operation, the addition operation element is selected by the selector in the ALU. However, when the operation of the node mul_t is performed, a plurality of combinations necessary for the combination connection in the ALU are selected. By linking the basic arithmetic elements, the arithmetic processing of the node group 70 is executed.

  FIG. 17 shows the configuration of the data flow graph processing unit 31. The data flow graph processing unit 31 includes a node group search unit 60, a node replacement unit 61, and a DFG reconstruction unit 62. The data flow graph processing function in the embodiment is realized by the CPU 10, the memory, the DFG processing program loaded in the memory, and the like in the processing device 10, and here, functional blocks realized by their cooperation are depicted. The DFG processing program may be built in the processing apparatus 10 or supplied from the outside in a form stored in a recording medium. Accordingly, those skilled in the art will understand that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof.

  The node group search unit 60 searches the DFG generated by the compiling unit 30 for a group of data flows having a predetermined rule, that is, a node group 70 having a predetermined rule. In the example of FIG. 15, since predetermined regularity is recognized in the node group surrounded by the dotted line, the node group search unit 60 finds four node groups 70 from the DFG.

  The node replacement unit 61 replaces the searched node group 70 with a predetermined number of nodes. The number of nodes and the number of stages to be replaced are preferably smaller than the number of nodes included in the node group 70 and smaller than the number of stages of the node group 70. As described above, in this embodiment, the node replacement unit 61 replaces the node group 70 with one node mul_t.

  FIG. 18 shows the DFG after node replacement. A state in which the node group 70 (see FIG. 16) configured in four stages is replaced with one node mul_t is shown.

  The DFG reconfiguration unit 62 reconfigures the DFG using the replaced node mul_t. The DFG reconstruction unit 62 deletes a nop node located in the same stage when an operation is not assigned to a node located in the same stage as the nodes included in the node group 70, that is, when a nop node is assigned. To do. Thereby, DFG can be reconfigure | reconstructed small. Further, the DFG reconstruction unit 62 replaces the sign inversion nodes of the x input system, and integrates the two x input systems into one system. Thereby, DFG can be reconfigure | reconstructed still smaller.

  FIG. 19 shows a DFG from which the nop node located at the same stage as the nodes included in the node group 70 is deleted. Since the node group 70 for four stages is replaced with one node mul_t, the number of nop nodes of the x input system, which is a multiplicand, is three stages per node mul_t. Compared with FIG. 18, ten stages of nop nodes can be deleted, and the DFG can be reduced.

  FIG. 20 shows a state in which the sign inversion node (−1 ×) existing in one of the two systems of the x input system is replaced with the nop node arranged at the end of the same system.

  Replace the 4-bit left shift operation at the second stage of the right system of the x input system with the first stage nop node of the same system, or the 4-bit left shift operation at the first stage of the left system of the same system It can be seen that in the two systems, the sequence of the nodes above the sign inversion node (−1 ×) is exactly the same in the two systems.

  FIG. 21 shows the DFG after the 4-bit left shift operation in the second stage of the right system is replaced with the first stage nop node of the same system. FIG. 21 shows that two x input systems can be integrated into one system.

  FIG. 22 shows the DFG after the x input system is integrated into one system. As shown in FIG. 22, when the node mul_t is used, multiplication of multiplicand 24 bits × multiplier 4 bits can be executed with an 8-stage ALU sequence. Compared with the fact that 20 stages are required in the DFG of FIG. 14, the number of stages is 0.4 (= 8/20) times. Further, as shown in FIG. 22, the number of nodes is 15, which is 0.23 (= 15/65) times the number of nodes compared with 65 required in the DFG in FIG. As a result, the number of DFG stages can be reduced, the number of circuit reconfigurations in the reconfigurable circuit 12 can be reduced, and the power consumption associated with circuit reconfiguration can be reduced.

  FIG. 23 shows a state where the condition processing part for the upper two stages of the y system in FIG. 22 is replaced with a bit product operation node. The bit product operation uses a value in which all bits are 1 with respect to the multiplier y. For example, in the case of y = 3, since y is a positive number in the condition processing part of FIG. 22, it becomes F (false) and “3 = 0011” is output from the merge node. In the bit product operation of FIG. 23, “(3 = 0011) & (1111) = 0011” is obtained, which is the same as the output from the condition processing portion of FIG. In the case of y = -3, since y is a negative number in the condition processing part of FIG. 13, T (true) is obtained and “16 + (− 3) = 13 = 1101” is output from the merge node. In the bit product operation of FIG. 23, “(−3 = 11101) & (1111) = 11101” is obtained, which is the same as the output from the condition processing portion of FIG. By using the bit product operation node, the number of stages of the DFG can be reduced by one compared to the DFG that performs the condition processing for the upper two stages of the y system in FIG.

  FIG. 24 shows a DFG of multiplication of multiplicand 8 bits × multiplier 8 bits. In this case, 8 mul_t are required. As in the DFG shown in FIG. 23, it is possible to replace the condition processing part for the upper two stages of the y system with a bit product operation node.

  FIG. 25 shows a DFG of multiplication of multiplicand 4 bits × multiplier 24 bits. In this case, 24 mul_t are required, and the 24th power of 2 is added by the first stage addition. From the above DFG, it can be seen that the node mul_t is required by the number of multipliers. By exchanging the multiplicand and the multiplier, the operation result of the multiplicand 24 bits × multiplier 4 bits and the multiplicand 4 bits × multiplier 24 bits becomes the same, but the DFG is efficiently created when the number of bits of the multiplier is small. Can do. Thus, when the number of bits of the multiplier is larger than the number of bits of the multiplicand, it is preferable to create a DFG by exchanging the multiplier and the multiplicand.

  FIG. 26 shows another example of the writing algorithm. FIG. 26 shows an example of multiplication of 4 bits (1011 in binary display) × 4 bits (1111 in binary display). The decimal display is 11 × 15. In this example, an object is to divide a multiplication operation by a predetermined digit and perform parallel processing for each divided digit. By performing multiplication operations in parallel, the number of DFG stages can be reduced, and efficient calculation processing can be realized. In the following, the multiplication operation when the multiplier is displayed in binary is divided into odd and even digits. Even if the multiplication of odd bits and the multiplication of even bits of the multiplier y is performed in parallel, and finally the multiplication results are added, the operation result is the same.

  FIG. 27 shows the DFG of the node group 70 when it is divided into even digits and odd digits. The DFG shown in FIG. 27 includes a right 2-bit shift operation, an addition operation, a nop (signal through), a bit product operation with 1, an equivalent comparison operation with 1, and a merge operation. Hereinafter, this node group 70 is replaced with one new node “mul_t2”. Therefore, the node mul_t2 is a node configured by the plurality of basic operations described above.

  Similarly to the node mul_t illustrated in FIG. 16, the node mul_t2 can perform arithmetic processing in one ALU. Therefore, in the ALU, a plurality of basic arithmetic elements such as a right 2-bit shift arithmetic element, an addition arithmetic element, a bit product arithmetic element, an equivalent comparison arithmetic element, and a merge arithmetic element are connected so as to realize the arrangement relationship of the nodes mul_t2. Combination wiring is provided. Since this combination connection only connects the existing basic arithmetic elements, the circuit scale is not so large. When the operation of the node mul_t2 is executed, the operation processing of the node group 70 is executed by linking a plurality of basic arithmetic elements necessary for combination connection in the ALU.

  FIG. 28 shows a DFG in which multiplication operation is realized by mul_t. The multiplicand x is 10 bits and the multiplier y is 10 bits. When DFG is realized by mul_t, the number of nodes is 37 and the number of stages is 19.

  FIG. 29 shows a DFG in which multiplication operation is realized by mul_t2. For comparison with FIG. 28, the multiplicand x is 10 bits and the multiplier y is 10 bits. When DFG is realized by mul_t2, the number of nodes is 34 and the number of stages is 13. Therefore, in the case of a 10-bit × 10-bit multiplication operation, the scale of the DFG can be reduced by realizing the multiplication operation with mul_t2.

  The present invention has been described based on the embodiments. The embodiments are exemplifications, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. .

  For example, in the embodiment, an example in which a multiplication operation is processed has been described, but other than that, a commonly used division operation can be processed in the same manner. In this way, for operations that frequently appear on the DFG and that have a large circuit scale of arithmetic elements that execute the operations alone, a node group having a predetermined rule can be replaced with another node. It is possible to reduce the DFG and realize the processing speed of the processing apparatus 10.

  The arrangement of ALUs in the reconfigurable circuit 12 is not limited to a multistage arrangement that permits connection only in the vertical direction, but may be a mesh-like arrangement that permits connection in the horizontal direction. In the above description, connection lines for connecting logic circuits by skipping stages are not provided, but a connection connection for skipping such stages may be provided.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a block diagram of the processing apparatus which concerns on embodiment. It is a figure for demonstrating the setting data of the some circuit which can divide | segment the target circuit which should be produced | generated. It is a figure which shows the general structure of a reconfigurable circuit. It is a figure for demonstrating the structure of a data flow graph. It is a figure which shows the FIR filter circuit which consists of 7 taps using the front and back 7 points. FIG. 6 is a diagram showing a circuit in which the FIR filter circuit shown in FIG. 5 is replaced. FIG. 7 is a diagram showing a circuit in which the FIR filter circuit shown in FIG. 6 is further replaced. It is a figure which shows the data flow graph produced by compiling the FIR filter circuit shown in FIG. It is a figure which shows an example of a reconfigurable circuit. It is a figure which shows the example which implement | achieves the data flow graph shown in FIG. 8 using the reconfigurable circuit of FIG. It is a figure which shows the flowchart of the writing algorithm of m-bit multiplicand x and n-bit multiplier y. It is a figure which shows an example of a specific processing operation of 4 bits x 4 bits displayed in binary number. It is a figure which shows another example of the specific processing operation | movement of 4 bits x 4 bits displayed by the binary number. It is a figure which shows DFG which calculates multiplicand 24 bits x multiplier 4 bits using a writing algorithm. FIG. 15 is a diagram in which a group of data flows having a predetermined rule is surrounded by a dotted line in the data flow graph shown in FIG. 14. It is a figure which shows DFG of the node group shown in FIG. It is a figure which shows the structure of a data flow graph process part. It is a figure which shows DFG after performing replacement of a node. It is a figure which shows DFG which deleted the nop node located in the same stage as the node contained in a node group. It is a figure which shows the state which replaced the sign inversion node (-1x) in one of 2 systems of x input system with the nop node arrange | positioned at the end of the same system. It is a figure which shows DFG after replacing the 4 bit left shift operation in the 2nd step | paragraph of the right side system with the 1st nop node of the same type | system | group. It is a figure which shows DFG after integrating x input system into 1 system. It is a figure which shows the state which replaced the condition processing part for the upper 2 steps | paragraphs of y system | strain of FIG. 22 with the bit product operation node. It is a figure which shows DFG of the multiplication of multiplicand 8 bits x multiplier 8 bits. It is a figure which shows DFG of the multiplication of multiplicand 4 bits x multiplier 24 bits. It is a figure which shows another example of a writing algorithm. It is a figure which shows DFG of the node group at the time of dividing | segmenting into even-numbered digits and odd-numbered digits. It is a figure which shows DFG which implement | achieved multiplication operation by mul_t. It is a figure which shows DFG which implement | achieved multiplication operation by mul_t2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Processing apparatus, 12 ... Reconfigurable circuit, 14 ... Setting part, 18 ... Control part, 26 ... Integrated circuit device, 30 ... Compile part, 31 ... Data Flow graph processing unit, 32 ... setting data generation unit, 34 ... storage unit, 36 ... program, 38 ... data flow graph, 40 ... setting data, 52 ... connection unit, 53 ... ALU sequence, 60 ... node group search unit, 61 ... node replacement unit, 62 ... DFG reconstruction unit, 70 ... node group.

Claims (1)

A reconfigurable circuit having a multi-stage arrangement of logic circuits each capable of selectively executing a plurality of arithmetic functions, and a connection section for setting a connection relationship between an output of a preceding logic circuit and an input of a succeeding logic circuit A data flow graph processing apparatus for processing a data flow graph to be supplied to the data flow graph;
Means for generating a data flow graph expressing the dependency of execution order between operations based on a behavioral description describing the behavior of processing;
Means for replacing a group of data flows composed of basic operations in a reconfigurable circuit with one node;
Means for deleting a node located at the same stage when an operation is not assigned to a node located at the same stage as a node included in the group of data flows to be replaced;
A data flow graph processing apparatus comprising:

Images