JP4357326B2 - Reconfigurable circuit and processing device - Google Patents

Description

  The present invention relates to a reconfigurable circuit whose function can be changed, and more particularly to a technique for supplying data to a logic circuit included in the reconfigurable circuit.

  In recent years, development of reconfigurable processors capable of changing hardware operations in accordance with applications has been underway. As an architecture for realizing a reconfigurable processor, there are methods using a DSP (Digital Signal Processor) and an FPGA (Field Programmable Gate Array).

An FPGA (Field Programmable Gate Array) can design circuit configuration relatively freely by writing circuit data after LSI manufacture, and is used for designing dedicated hardware. The FPGA includes a lookup table (LUT) for storing a truth table of a logic circuit, a basic cell composed of an output flip-flop, and a programmable wiring resource connecting the basic cells. In the FPGA, a target logical operation can be realized by writing data stored in the LUT and wiring data. However, when an LSI is designed using an FPGA, the mounting area is very large and the cost is high as compared with an ASIC (Application Specific IC) design. Thus, a method has been proposed in which the circuit configuration is reused by dynamically reconfiguring the FPGA (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 10-256383

  For example, in satellite broadcasting, image quality may be adjusted by switching broadcast modes depending on the season. In the receiver, a plurality of circuits are built in hardware for each broadcast mode in advance, and the circuit is switched by a selector according to the broadcast mode for reception. Therefore, the other broadcast mode circuits of the receiver are idle during that time. When switching and using multiple dedicated circuits, such as mode switching, and the switching interval is relatively long, instead of creating multiple dedicated circuits, the LSI can be reconfigured instantaneously at the time of switching. The structure can be simplified to improve versatility, and at the same time the mounting cost can be reduced. In order to meet such needs, the manufacturing industry has attracted attention to dynamically reconfigurable LSIs. In particular, LSIs mounted on mobile terminals such as cellular phones and PDAs (Personal Data Assistance) must be downsized, and if LSIs can be dynamically reconfigured and functions can be switched appropriately according to the application, Mounting area can be reduced.

  The FPGA has a high degree of design freedom in circuit configuration and is general-purpose. On the other hand, in order to enable connection between all the basic cells, it is necessary to include a large number of switches and a control circuit for controlling ON / OFF of the switches. This inevitably increases the mounting area of the control circuit. Further, since a complicated wiring pattern is used for the connection between the basic cells, the wiring tends to be long, and the delay increases because of the structure in which many switches are connected to one wiring. For this reason, FPGA based LSIs are often used only for trial manufacture and experiments, and are not suitable for mass production in view of mounting efficiency, performance, cost, and the like. Furthermore, in the FPGA, it is necessary to send configuration information to a large number of basic cells of the LUT method, so that it takes a considerable time to configure the circuit. For this reason, the FPGA is not suitable for applications that require instantaneous switching of the circuit configuration.

  In order to solve these problems, in recent years, an ALU array called ALU (Arithmetic Logic Unit) in which multi-functional elements having a plurality of basic arithmetic functions are arranged in multiple stages has been studied. In the ALU array, processing flows in one direction from the upper stage to the lower stage, so that wiring that connects the ALUs in the horizontal direction is basically unnecessary. Therefore, the circuit scale can be reduced as compared with the FPGA.

  On the other hand, also in the ALU array, it is preferable to supply various data to each ALU and execute the arithmetic processing efficiently. For this purpose, a configuration such as a route and connection for supplying data to the ALU, and a switch for selecting the route and connection are required. In the circuit, the proportion of the area occupied by the connection and the switch cannot be ignored, and if the high-speed processing of the ALU array is pursued, the circuit scale around the ALU array itself and the ALU array tends to increase. In particular, when an ALU array is mounted on a mobile terminal, it is preferable to reduce the circuit scale while realizing efficient arithmetic processing.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a technique capable of improving the processing capability of a processing apparatus including an ALU array while suppressing the circuit scale.

In order to solve the above problems, according to one aspect of the present invention, there is provided a multi-stage arrangement of logic circuits each capable of selectively executing a plurality of arithmetic functions, and connection between an output of a preceding logic circuit and an input of a subsequent logic circuit A reconfigurable circuit including a connection unit capable of setting a relationship, wherein the logic circuit includes at least two input terminals of a first input terminal and a second input terminal, and the connection unit includes: In addition to the connection for connection between the logic circuits, the first data can be input to the first input terminal, and the second data that can be input to the second input terminal that is not input to the first input terminal can be input. Constructed with connections. The number of second data input per stage of the connection unit is limited to less than the number of logic circuits per stage of the reconfigurable circuit. According to the reconfigurable circuit of this aspect, by not inputting the second data to the first input terminal, the configuration of the selection unit for supplying data to the first input terminal can be reduced, and the circuit scale can be reduced. Can be reduced. Also, by limiting the number of input data, the input connection can be simplified and the circuit scale can be further reduced.

Another aspect of the present invention is a multi-stage arrangement of logic circuits each capable of selectively executing a plurality of arithmetic functions, and a connection section capable of setting a connection relationship between an output of a preceding logic circuit and an input of a succeeding logic circuit A reconfigurable circuit including: a first input path that is connected to the connection unit and can input output data of the reconfigurable circuit to the connection unit; and connected to the connection unit and constant data is input to the logic circuit. The present invention relates to a processing device including a second input path that can be input to the input. In the processing apparatus of this aspect, the logic circuit is provided with at least two input terminals of the first input terminal and the second input terminal, and the connection portion is provided separately from the connection connection between the logic circuits. Only the output data supplied from the first input path to the input terminal and only the constant data supplied from the second input path to the second input terminal can be input. Further, the number of data input per stage of the connection unit is limited to less than the number of logic circuits per stage of the reconfigurable circuit. According to the processing apparatus of this aspect, by limiting the number of data input to the first input terminal and the second input terminal, it is possible to reduce the configuration of a selection unit for supplying data to the input terminal.

  The logic circuit may be an arithmetic logic circuit capable of selectively executing a plurality of types of multi-bit operations.

  It should be noted that any combination of the above components and the expression of the present invention expressed as a method, apparatus, system, and computer program are also effective as an aspect of the present invention.

  According to the present invention, it is possible to provide a technique for reducing the circuit scale while maintaining or improving the processing capability of the reconfigurable circuit.

  FIG. 1 is a configuration diagram of a processing apparatus 10 according to the embodiment. The processing device 10 includes an integrated circuit device 26 having a function that allows the circuit configuration to be reconfigured. The integrated circuit device 26 is configured as one chip, and includes a reconfigurable circuit 12, a setting unit 14, a control unit 18, an internal state holding circuit 20, an output circuit 22, a feedback path 24, and a multiplexer unit 25. The reconfigurable circuit 12 can change the function by changing the setting. The reconfigurable circuit 12 is configured as a logic circuit such as a combinational circuit or a sequential circuit. A path connecting the output and input of the reconfigurable circuit 12 through the feedback path 24 is referred to as an input path through which the output of the reconfigurable circuit 12 can be input to the logic circuit.

  The reconfigurable circuit 12 includes a multi-stage arrangement of logic circuits each capable of selectively executing a plurality of arithmetic functions, and a connection unit capable of setting a connection relationship between the output of the preceding logic circuit and the input of the succeeding logic circuit. Is provided. Structurally, a connection part for setting connection lines between logic circuit strings is provided between the plurality of logic circuit strings. The reconfigurable circuit 12 can change the function by arbitrarily setting the function of each logic circuit arranged in a plurality of stages and the connection between the logic circuits.

  The setting unit 14 supplies setting data 40 for configuring a desired circuit to the reconfigurable circuit 12. The setting unit 14 may be configured as a command memory that outputs stored data based on the count value of the program counter. In this case, the control unit 18 controls the output of the program counter. In this case, the setting data 40 may be command data output from the command memory.

  The feedback path 24 functions as a feedback path, and connects the output of the reconfigurable circuit 12 to the input of the reconfigurable circuit 12. The internal state holding circuit 20 and the output circuit 22 are configured as sequential circuits such as a data flip-flop (DFF), for example, and receive the output of the reconfigurable circuit 12. The internal state holding circuit 20 is connected to the feedback path 24 and feeds back the output of the reconfigurable circuit 12 to the input of the reconfigurable circuit 12.

  The reconfigurable circuit 12 includes a logic circuit whose function can be changed. The plurality of logic circuits may have a structure arranged in a matrix. The function of each logic circuit and the connection relationship between the logic circuits are set based on setting data 40 supplied by the setting unit 14. The setting data 40 is generated by the following procedure.

  A program 36 to be realized by the integrated circuit device 26 is held in the storage unit 34. The program 36 shows an operation description describing the operation of processing in the circuit, and describes a signal processing circuit or a signal processing algorithm in a high-level language such as C language. The compiling unit 30 compiles the program 36 stored in the storage unit 34, converts it into a data flow graph (DFG) 38, and stores it in the storage unit 34. The data flow graph 38 expresses the dependency of execution order between operations in a circuit, and shows the flow of operations of input variables and constants in a graph structure. In general, the data flow graph 38 is created so that the calculation proceeds from top to bottom.

  The setting data generation unit 32 generates setting data 40 from the data flow graph 38. The setting data 40 is data for mapping the data flow graph 38 to the reconfigurable circuit 12 and determines the function of the logic circuit in the reconfigurable circuit 12 and the connection relationship between the logic circuits. The setting data generation unit 32 may generate setting data 40 for a plurality of circuits obtained by dividing one circuit to be generated.

  FIG. 2 is a diagram for explaining setting data 40 of a plurality of circuits formed by dividing one target circuit 42 to be generated. A circuit generated by dividing one target circuit 42 is referred to as a “divided circuit”. In this example, one target circuit 42 is divided into four divided circuits, that is, divided circuit A, divided circuit B, divided circuit C, and divided circuit D. The target circuit 42 is divided according to the calculation flow in the data flow graph 38. In the data flow graph 38, when the calculation flow is expressed in a direction from the top to the bottom, the data flow graph 38 is cut from the top at a predetermined interval, and the cut portion is set as a dividing circuit. The interval to be cut according to the flow is determined to be equal to or less than the number of logic circuit stages in the reconfigurable circuit 12. The target circuit 42 may be divided in the horizontal direction of the data flow graph 38. The width to be divided in the horizontal direction is determined to be equal to or less than the number of logic circuits in the reconfigurable circuit 12 per stage.

  In particular, when the target circuit 42 to be generated is larger than the reconfigurable circuit 12, the setting data generation unit 32 may divide the target circuit 42 so as to have a size that can be mapped to the reconfigurable circuit 12. preferable. The setting data generation unit 32 determines the division method of the target circuit 42 based on the arrangement structure of the logic circuits in the reconfigurable circuit 12 and the data flow graph 38. The arrangement structure of the reconfigurable circuit 12 may be transmitted from the control unit 18 to the setting data generation unit 32 or may be recorded in the storage unit 34 in advance. In addition, the control unit 18 may instruct the setting data generation unit 32 on how to divide the target circuit 42.

  By executing the above procedure, the storage unit 34 stores a plurality of setting data 40 for configuring the reconfigurable circuit 12 as a desired circuit. The plurality of setting data 40 constitute setting data 40a for configuring the dividing circuit A, setting data 40b for configuring the dividing circuit B, setting data 40c for configuring the dividing circuit C, and a dividing circuit D. This is setting data 40d. As described above, the plurality of setting data 40 represent a plurality of divided circuits obtained by dividing one target circuit 42, respectively. As described above, by generating the setting data 40 of the target circuit 42 to be generated according to the circuit scale of the reconfigurable circuit 12, it is possible to realize the processing apparatus 10 with high versatility. From another point of view, according to the processing device 10 of the embodiment, it is possible to reconfigure a desired circuit using the reconfigurable circuit 12 having a small circuit scale.

  Returning to FIG. 1, in the present embodiment, the feedback path 24 is provided with a multiplexer unit (MUX) 25. The multiplexer unit 25 has a function of selectively supplying output data from a plurality of DFFs of the internal state holding circuit 20 and input data from the outside to the logic circuit of the reconfigurable circuit 12.

  The logic circuit of the reconfigurable circuit 12 performs an operation using variables or constants. Addition and multiplication are typical examples. Therefore, there are frequently occasions where the output data of the reconfigurable circuit 12 is used as variable data in the reconfigurable circuit 12 to be reconfigured after the next time. In the processing apparatus 10 shown in FIG. 1, the output data of the reconfigurable circuit 12 is supplied by the feedback path 24, and all the output data can be input to each logic circuit of the reconfigurable circuit 12. is there. As a result, the logic circuit can directly acquire the data necessary for the fed back calculation, and can execute the intended calculation process.

  However, if all data is input to all logic circuits in the reconfigurable circuit 12, for example, the area required for wiring increases. The reduction in circuit scale is one of the important issues in the integrated circuit technology because it leads not only to the problem of the mounting area but also to the reduction of power consumption, which is the integrated circuit device 26 shown in this embodiment. Is no exception. For the above reasons, in the processing apparatus 10 of the present embodiment, the number of output data through the feedback path 24 may be limited to reduce the circuit scale.

  FIG. 3 shows the reconfigurable circuit 12 in the embodiment. The reconfigurable circuit 12 has a multi-stage arrangement of logic circuits each capable of selectively executing a plurality of arithmetic functions, and a connection that can arbitrarily set the connection relationship between the output of the preceding logic circuit and the input of the succeeding logic circuit. Part 52. In the reconfigurable circuit 12, the operation proceeds from the upper stage to the lower stage due to the multistage arrangement structure of the logic circuits. In the present specification and claims, “multi-stage” means a plurality of stages.

  The reconfigurable circuit 12 has an ALU (Arithmetic Logic Unit) as a logic circuit. The ALU is an arithmetic logic circuit capable of selectively executing a plurality of types of multi-bit operations, and can selectively execute a plurality of types of multi-bit operations such as logical sum, logical product, and bit shift by setting. Each ALU has a selector for setting a plurality of arithmetic functions. The ALU has two input terminals.

  The reconfigurable circuit 12 is configured as an ALU array of X stages and Y columns in which X ALUs in the vertical direction and Y ALUs in the horizontal direction are arranged. Here, a three-stage 6-column ALU array in which three ALUs in the vertical direction and six ALUs in the horizontal direction are arranged is shown. The reconfigurable circuit 12 includes a connection unit 52 and an ALU column 53. The ALU row 53 is provided in a plurality of stages, and the connection unit 52 is provided between the front and rear ALU rows 53 to set the connection relationship between the output of the previous ALU and the input of the rear ALU.

  In the example shown in FIG. 3, a connection section 52b constituting the second stage is provided between the first-stage ALU row 53a and the second-stage ALU row 53b, and the second-stage ALU row 53b and the third-stage ALU row 53b are provided. Between the two ALU rows 53c, a connecting portion 52c constituting the third stage is provided. In addition, the connection part 52a which comprises a 1st stage is provided above the ALU row | line | column 53a of a 1st stage.

  Input variables and constants are input to the first-stage ALU 11, ALU 12,..., ALU 16, and a set predetermined calculation is performed. The calculation result output is input to the second-stage ALU 21, ALU 22,..., ALU 26 according to the connection set in the second-stage connection unit 52b. In the second-stage connection unit 52b, an arbitrary connection relationship between the output of the first-stage ALU column 53a and the input of the second-stage ALU column 53b, or a combination of predetermined connection relationships is selected. The connection connection is configured so as to realize the established connection relationship, and the desired connection is made effective by setting. The second stage ALU 21, ALU 22,..., ALU 26 receives the output of the ALU column 53a and performs a predetermined calculation. The output of the calculation result is input to the third-stage ALU 31, ALU 32,..., ALU 36 according to the connection set in the connection connection of the third-stage connection section 52c.

  Output data from the third-stage ALU column 53c, which is the final stage, is output to the internal state holding circuit 20. The internal state holding circuit 20 inputs output data to the connection unit 52a via the feedback path 24.

  Each connection unit 52 is configured to have a plurality of SWs (switches). In the illustrated example, six SWs are shown for each connection unit 52, but the SWs are provided for the input terminals of each ALU. Here, since each ALU has two input terminals, the connection unit 52 is actually configured with twelve SWs. The SW is configured as a multiplexer, and selectively outputs the output data from the upper ALU, the output data supplied from the feedback path 24, or the constant data supplied from the setting unit 14 to the input terminal of the corresponding ALU. Has a function to output.

  FIG. 4 shows the reconfigurable circuit 12 and its peripheral circuits in the embodiment. The internal state holding circuit 20 has six DFFs corresponding to the ALUs in the ALU column 53c at the final stage. The feedback path 24 supplies six DFF output data to the multiplexer unit 25.

  The multiplexer unit 25 includes a plurality of multiplexers, and each multiplexer selects external input and data from the internal state holding circuit 20 and outputs the selected data to the first input path 17. The first input path 17 is connected to the connection portions 52a, 52b, and 52c of the reconfigurable circuit 12, and the output data or external input data of the reconfigurable circuit 12 can be input to the connection portions 52a, 52b, and 52c. it can. The output data or external input data of the reconfigurable circuit 12 constitutes variable data. The data selection in the multiplexer may be performed by the setting data 40 or may be performed by a selection instruction from the control unit 18. Hereinafter, data input through the first input path 17 is referred to as “variable input”. Note that the entire path constituted by the feedback path 24 to the first input path 17 may be referred to as a first input path capable of inputting the output data of the reconfigurable circuit 12 to the ALU.

  The setting unit 14 includes a constant RAM unit 15 that stores constant data. The constant RAM unit 15 outputs constant data to the second input path 19 based on a read instruction from the control unit 18. When the setting unit 14 is configured as a command memory, the command memory outputs constant data to the second input path 19. The second input path 19 is connected to the connection parts 52a, 52b, and 52c of the reconfigurable circuit 12, and constant data supplied from the constant RAM part 15 can be input to the connection parts 52a, 52b, and 52c. Hereinafter, input of constant data through the second input path 19 is referred to as “constant input”.

  In order to enable direct input of data to the ALU column 53, the connection unit 52 provides the data supplied from the first input path 17 and the second input path 19 to the intended ALU of the ALU column 53. The first input path 17 and the second input path 19 are connected to the ALU. The connection unit 52 includes an input connection capable of inputting data supplied from the first input path 17 and the second input path 19 to the ALU, separately from the connection connection for connecting the ALUs. As a result, the ALU can receive data from the SW, and can execute the intended arithmetic processing.

  In the present embodiment, the constant data and variable data supplied to the connection unit 52 are limited to be smaller than the number of SWs of the connection unit 52. That is, the constant data and variable data supplied to the connection unit 52 are limited to four for six ALUs per stage. Therefore, regarding the constant input, the second input path 19 is configured to include 12 wires of 4 × 3 (the number of ALU stages).

  Regarding the variable input, the multiplexer unit 25 has three multiplexer groups corresponding to the three stages of ALU columns 53, each multiplexer group has four multiplexers, and four variables for each ALU column 53. Data can be input. Therefore, the multiplexer unit 25 has 12 multiplexers. Each multiplexer is supplied with one external input data and output data from six DFFs. Therefore, the multiplexer is configured as a 7: 1 multiplexer that selects and outputs one data from a total of seven data.

  Variable input and constant input may be allowed for all ALUs, but in that case, the number of wires in the second input path 19 is 18, and the number of multiplexers in the multiplexer unit 25 and the number of first input paths 17 The number of wirings is also 18. As described above, in order to enable data input to all ALUs, the circuit scale of the first input path 17, the second input path 19 and the multiplexer unit 25 is increased, and input connections are also made at each connection unit 52. Since it becomes complicated, the circuit scale of the connection part 52 also becomes large. Therefore, in this embodiment, the circuit scale is reduced by limiting the number of inputs to each connection unit 52. This is based on the inventor's knowledge that, of the six ALUs arranged in the same stage, five or more ALUs have a low probability of requiring constant input or variable input.

  If five or more ALUs in one stage require variable data, four variable data are supplied to the first stage ALU through the first input path 17 and the remaining variable data is supplied to the first input. The processing can be continued by supplying to the lower ALU through the path 17. Similarly, when five or more ALUs in one stage require constant data, four constant data are supplied to the one stage ALU through the second input path 19 and the remaining constant data is supplied to the second ALU. The processing can be continued by supplying to the lower ALU through the input path 19. In this case, there is a possibility that the DFG becomes large and the processing time may increase. However, considering that the probability is not large, it is better to reduce the circuit scale than to strictly pursue the processing speed. Is big.

  FIG. 5 shows an example of data types that can be input to the ALU. As described above, the ALU is configured to have two input terminals, and desired data is supplied from the SW provided corresponding to each input terminal. In this example, SW1 corresponding to the input terminal a and SW2 corresponding to the input terminal b are respectively input with three types of data of ALU output data, constant data, and variable data of the previous stage, and based on the setting data 40 Any data is selectively output to the ALU.

  FIG. 6 shows the details of the input to the SW shown in FIG. Six previous-stage ALU output data, four constant data, and four variable data are input to SW1 and SW2, respectively. Therefore, SW1 and SW2 are configured as a 14: 1 multiplexer that selects and outputs one data from a total of 14 data.

  FIG. 7 shows an example of operations in the ALU. IN_a indicates input data of the input terminal a, and IN_b indicates input data of the input terminal b. As an example of operation, Verilog representation of addition, subtraction, bit AND, bit OR, bit EXOR, and sign inversion is shown. In the input configuration to the SW shown in FIGS. 5 and 6, since all data can be input to the input terminal a and the input terminal b, the data input to the input terminal a and the input terminal b are input. All combinations of data can be realized, and operations in the ALU can be easily executed.

  Here, considering the constant data, for example, a one-input operation of constant data, for example, an operation for bit-shifting a constant can be calculated in advance by the compiling unit 30 based on a program. Since the compiling unit 30 can create the data flow graph 38 based on the calculation result, it is not necessary to process one-input operation of constant data with the ALU. Therefore, when a one-input operation is performed on the ALU, the input is output data from the previous stage ALU or variable data.

  In the case of two-input arithmetic, if both the two inputs are constant data, the compiling unit 30 can calculate in advance based on the program as described above. For example, addition of constants. Since the compiling unit 30 can create the data flow graph 38 based on the calculation result, it is not necessary to process the two-input operation of the constant data with the ALU. Therefore, when performing a two-input operation on the ALU, both are not constant data, and the constant data is only one input at most.

  From the above consideration, constant data is not supplied to both the input terminal a and the input terminal b in the ALU. Therefore, as shown in FIGS. 5 and 6, constant data is input to both SW1 and SW2. It turns out that there is no need to do. Based on the above consideration, the present inventor has obtained knowledge that the input configuration shown in FIGS. 5 and 6 is useless, and the input configuration to SW1 and SW2 is unnecessarily large. It was found to increase.

  FIG. 8 shows the input configuration of the ALU in the embodiment. The input configuration shown in FIG. 8 improves the input configuration of the ALU shown in FIGS.

  In the input configuration of the ALU shown in FIG. 8, the constant input is only SW1, and the constant input to SW2 is not performed. Connection unit 52 has an input connection that allows constant data and variable data to be input to input terminal a and allows variable data to be input to input terminal b. That is, the input connection enables variable data to be input to the input terminal b, and constant data not input to the input terminal b can be input together with the variable data to the input terminal a. According to the above consideration, since it is not necessary to input constant data to both the input terminal a and the input terminal b, it is possible to omit constant input to SW2. Note that the output data from the previous ALU is input to SW1 and SW2 by connection connection.

  FIG. 9 shows details of the input to the SW shown in FIG. SW1 is input with six previous-stage ALU output data, four constant data, and four variable data. On the other hand, six previous-stage ALU output data and four variable data are input to SW2. Thereby, SW2 can be configured as a 10: 1 multiplexer that selects and outputs one data out of a total of 10 data, so that the circuit scale of SW2 can be reduced compared to the SW input configuration shown in FIG. . The reduction in circuit scale leads not only to the problem of mounting area but also to reducing power consumption.

  FIG. 10 shows the input configuration of the ALU according to the embodiment, and the input to the SW is further restricted than the input configuration shown in FIG.

  In the input configuration of the ALU shown in FIG. 10, not only the constant input is SW1 and the constant input to SW2 is not performed, but the variable input is only SW2 and the variable input to SW1 is not performed. The connection unit 52 has an input connection that allows constant data to be input to the input terminal a and allows variable data to be input to the input terminal b. That is, the input connection allows variable data not input to the input terminal a to be input to the input terminal b, and constant data not input to the input terminal b can be input to the input terminal a.

  Therefore, the connection unit 52 supplies either constant data or previous-stage ALU output data to the input terminal a, and supplies either variable data or previous-stage ALU output data to the input terminal b.

  FIG. 11 shows the details of the input to the SW shown in FIG. Six pre-stage ALU output data and four constant data are input to SW1. On the other hand, six previous-stage ALU output data and four variable data are input to SW2. As a result, SW1 and SW2 can be configured as a 10: 1 multiplexer that selects and outputs one data from a total of 10 data, so that the circuit scale of SW2 is further reduced compared to the SW input configuration shown in FIG. be able to.

  FIG. 12 shows an example in which the connection unit 52 restricts connection of four constant inputs, four variable inputs, and each ALU. In the figure, ALU surrounded by a dotted line indicates a range in which a constant input and variable input of any of a to d are input. As shown in the figure, the connection unit 52 sets the ALU range in which a plurality of data input from the first input path 17 and the second input path 19 can be supplied to be different for each input data. ing. This is realized by forming an input connection at the connection portion 52 in association with the first input path 17 and the second input path 19.

  The connection unit 52 sets this range by gradually shifting the range from the ALU 1 arranged at one end of the plurality of ALUs included in one stage to the ALU 6 arranged at the other end. That is, the constant data “a” and the variable data “a” can be supplied to the ALU existing in the range of ALU1 to ALU3. Similarly, the constant data b and the variable data b can be supplied to the ALU existing in the range of ALU2 to ALU4, and the constant data c and the variable data c can be supplied to the ALU existing in the range of ALU3 to ALU5. The constant data d and the variable data d can be supplied to the ALU existing in the range of ALU4 to ALU6. In this way, by gradually shifting the range in which data can be supplied between ALU1 and ALU6, each data can be uniformly allocated to the ALU while suppressing the circuit scale of the input connection. .

  In this way, by restricting the range of the ALU that can supply constant data and variable data, the input connection of the connection unit 52 can be simplified, and the circuit scale of the connection unit 52 can be reduced.

  FIG. 13 shows details of input to the SW corresponding to each ALU. Here, as described with reference to FIG. 12, the connection between the constant input and variable input and each ALU is limited. 13A shows the input configuration of the SW corresponding to ALU1, FIG. 13B shows the input configuration of the SW corresponding to ALU2, and FIG. 13C shows the input of the SW corresponding to ALU3. FIG. 13 (d) shows the input configuration of the SW corresponding to ALU4, FIG. 13 (e) shows the input configuration of the SW corresponding to ALU5, and FIG. 13 (f) corresponds to ALU6. The input configuration of the SW to be performed is shown.

  By limiting the connection of each ALU, the SW corresponding to ALU1 and ALU6 can be realized by a 7: 1 multiplexer, and the SW corresponding to ALU2 and ALU5 can be realized by an 8: 1 multiplexer, respectively. ALU3 and ALU4 Each SW corresponding to can be realized by a 9: 1 multiplexer. Since the multiplexer can be made small in this way, the circuit scale can be reduced.

  By limiting the input to the SW as shown in FIG. 10, it is possible to reduce the circuit scale. However, by limiting the input, the operation in the ALU as shown in FIG. There are cases where processing in a column is impossible. Specifically, this is a case of subtraction in which the order relationship between the input terminal a and the input terminal b is important. In the ALU operation shown in FIG. 7, only (IN_a−IN_b) is defined as subtraction. With the input restriction in FIG. 10, either the previous stage ALU output or the constant input is applied to the input terminal a, and the input terminal b is applied. This is due to the fact that either the previous stage ALU output or the variable input is input. FIG. 14 to FIG. 16 show cases in which processing with a single ALU row is impossible.

  FIG. 14 shows the processing of (variable input)-(variable input). Since variable input cannot be input to the input terminal a, the DFG shown in FIG. 14A cannot be mapped to the reconfigurable circuit 12. Therefore, as shown in FIG. 14B, (variable input)-(variable input) can be executed by performing variable input using the input terminals b of the ALUs arranged in two stages. Note that “nop” indicates a through node that does not execute an operation.

  FIG. 15 shows the processing of (variable input)-(constant input). Since variable input cannot be input to the input terminal a and constant input cannot be input to the input terminal b, the DFG shown in FIG. 15A cannot be mapped to the reconfigurable circuit 12. Therefore, as shown in FIG. 15B, (variable input)-(constant input) can be executed by supplying the variable input and constant input input to the upper stage with the input terminals switched to the lower stage. .

  FIG. 16 shows the processing of (previous stage ALU output)-(constant input). Since constant input cannot be input to the input terminal b, the DFG shown in FIG. 16A cannot be mapped to the reconfigurable circuit 12. Therefore, as shown in FIG. 16B, by supplying the constant input inputted to the upper stage to the input terminal b of the lower stage, (previous stage ALU output)-(constant input) can be executed.

  As described above, FIGS. 14 to 16 show examples in which processing cannot be performed with a single ALU column. Even in this case, each subtraction process can be executed by using a two-stage ALU sequence. When a two-stage ALU sequence is used, the reconfiguration speed of the reconfigurable circuit 12 is slightly reduced. However, such subtraction is a small part of the entire arithmetic processing, while the circuit scale is greatly reduced. The advantage is greater because it can. In the following, an ALU function is added so that the subtraction processing shown in FIGS. 15 and 16 is executed in a single ALU column.

  FIG. 17 shows another example of operations in the ALU. With respect to the calculation example shown in FIG. 7, subtraction 2 (IN_b−IN_a) is added in the calculation example of FIG. Subtraction 1 corresponds to the subtraction in FIG. As shown in the ALU input example of FIG. 5, when all data is supplied to both input terminals without considering the reduction in circuit scale, one subtraction (IN_a-IN_b) may be used, but as shown in FIG. Thus, when the ALU input restriction is performed, the reconfiguration speed of the circuit can be increased by adding the subtraction 2.

  FIG. 18 shows the processing of (variable input)-(constant input). By inputting the variable input to the input terminal b, the constant input to the input terminal a, and setting the arithmetic function of the ALU to (IN_b-IN_a), (variable input)-(constant input) is executed in a single ALU sequence. become able to.

  FIG. 19 shows the processing of (previous stage ALU output) − (constant input). By inputting the constant input to the input terminal a, the previous stage ALU output to the input terminal b, and setting the arithmetic function of the ALU to (IN_b-IN_a), the (previous stage ALU output)-(constant input) is a single stage ALU sequence. Can be executed with

  FIG. 20 shows an adder. a and b are inputs, cin is a carry input, cout is a carry output, and q is an output.

  FIG. 21 shows an adder / subtracter (ab). The adder / subtracter is only added one multiplexer and one inverting circuit to the adder, and the added circuit is considerably smaller than the adder portion.

  FIG. 22 shows an adder / subtracter in which the function of (b−a) is added to the adder / subtracter shown in FIG. 21. Compared to the adder / subtracter shown in FIG. 21, two selectors are added to the inputs a and b, but these added circuits are considerably smaller than the adder / subtractor. Therefore, although the circuit of the ALU becomes slightly larger, the circuit scale does not increase so much because the common part with the adder / subtracter (ab) shown in FIG. Therefore, by adding the subtraction 2 calculation function shown in FIG. 17, an efficient DFG can be created, the processing in the compiler becomes easy, and the compilation time can be shortened. As described above, even when the input restriction as shown in FIG. 10 is performed, the total circuit scale can be effectively reduced without reducing the processing speed.

  Note that the (variable input)-(variable input) operation shown in FIG. 14 is considered to have a low appearance frequency when viewed from the whole operation, so that even if the DFG becomes very small, the circuit scale can be reduced. Merits are better.

  The present invention has been described based on the embodiments. The embodiments are exemplifications, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. .

  In the embodiment, the output of the reconfigurable circuit 12 is made from the last-stage ALU string 53c, but the output may be made from the first-stage ALU string 53a or from the second-stage ALU string 53b. May be made.

  For example, the array of ALUs in the reconfigurable circuit 12 is not limited to a multistage array that allows connection only in the vertical direction, but may be a mesh-like array that allows connection in the horizontal direction. In the above description, connection lines for connecting logic circuits by skipping stages are not provided, but a connection connection for skipping such stages may be provided.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a block diagram of the processing apparatus which concerns on embodiment. It is a figure for demonstrating the setting data of the some circuit which can divide | segment the target circuit which should be produced | generated. It is a figure which shows the reconfigurable circuit in embodiment. 1 is a diagram illustrating a reconfigurable circuit 12 and its peripheral circuits in an embodiment. FIG. It is a figure which shows an example of the data type which can be input into ALU. It is a figure which shows the detail of the input to SW shown in FIG. It is a figure which shows an example of the calculation in ALU. It is a figure which shows the input structure of ALU in embodiment. It is a figure which shows the detail of the input to SW shown in FIG. It is a figure which shows another example of the input structure of ALU in embodiment. It is a figure which shows the detail of the input to SW shown in FIG. It is a figure which shows an example which gave a restriction | limiting to the connection of four constant inputs, four variable inputs, and each ALU. It is a figure which shows the detail of the input to SW corresponding to each ALU. It is a figure which shows the process of (variable input)-(variable input). It is a figure which shows the process of (variable input)-(constant input). It is a figure which shows the process of (previous stage ALU output)-(constant input). It is a figure which shows another example of the calculation in ALU. It is a figure which shows the process of (variable input)-(constant input). It is a figure which shows the process of (previous stage ALU output)-(constant input). It is a figure which shows a full adder adder. It is a figure which shows an adder / subtracter (ab). It is a figure which shows the adder / subtracter which added the function of (ba) to the adder / subtracter shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Processing apparatus, 12 ... Reconfigurable circuit, 14 ... Setting part, 17 ... 1st input path | route, 18 ... Control part, 19 ... 2nd input path | route, 20 * ..Internal state holding circuit, 22 ... output circuit, 24 ... feedback path, 25 ... multiplexer unit, 26 ... integrated circuit device, 34 ... storage unit, 52 ... connecting unit, 53 ... ALU column.

Claims (2)

Reconfigurable circuit having a multi-stage arrangement of logic circuits each capable of selectively executing a plurality of arithmetic functions, and a connection section capable of setting a connection relationship between the output of the preceding logic circuit and the input of the succeeding logic circuit Because
The logic circuit includes at least two input terminals, a first input terminal and a second input terminal,
The connection unit can input first data to the first input terminal and input second data not to be input to the first input terminal to the first input terminal separately from the connection for connection between the logic circuits. have a input for connection to,
The reconfigurable circuit, wherein the number of second data input per stage of the connection unit is limited to less than the number of logic circuits per stage of the reconfigurable circuit.
Reconfigurable circuit having a multi-stage arrangement of logic circuits each capable of selectively executing a plurality of arithmetic functions, and a connection section capable of setting a connection relationship between the output of the preceding logic circuit and the input of the succeeding logic circuit When,
A first input path connected to the connection unit and capable of inputting output data of the reconfigurable circuit to the connection unit;
A second input path connected to the connecting portion and capable of inputting constant data to the connecting portion to the logic circuit, wherein the logic circuit has at least two input terminals, a first input terminal and a second input terminal. Provided,
In addition to the connection for connection between the logic circuits, the connection unit outputs only output data supplied from the first input path to the first input terminal, and constant data supplied from the second input path to the second input terminal. only to have the input for the connection can be input to,
The processing apparatus , wherein the number of data input per stage of the connection unit is limited to less than the number of logic circuits per stage of the reconfigurable circuit .

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