JP5025509B2 - Arithmetic processing circuit - Google Patents

Description

  The present invention relates to an arithmetic processing circuit. In particular, the present invention relates to an arithmetic processing circuit capable of performing a multiple-length operation and having a carry output from one logic circuit to another logic circuit.

  In recent years, development of reconfigurable processors capable of changing hardware operations in accordance with applications has been underway. As an architecture for realizing a reconfigurable processor, there are methods using a DSP (Digital Signal Processor) and an FPGA (Field Programmable Gate Array).

  An FPGA (Field Programmable Gate Array) can design circuit configuration relatively freely by writing circuit data after the LSI is manufactured, and is used for designing dedicated hardware. The FPGA includes a lookup table (LUT) for storing a truth table of a logic circuit, a basic cell composed of an output flip-flop, and a programmable wiring resource that connects the basic cells. In the FPGA, a target logical operation can be realized by writing data stored in the LUT and wiring data. However, when an LSI is designed using an FPGA, the mounting area is very large and the cost is high compared to an ASIC (Application Specific IC) design. Therefore, a method has been proposed in which the circuit configuration is reused by dynamically reconfiguring the configuration of the arithmetic circuit in the LSI (see, for example, Patent Document 1).

  In recent years, an ALU array in which logic circuits having basic arithmetic functions called ALUs (Arithmetic Logic Units) (arithmetic functions are, for example, addition and subtraction functions) are arranged in a matrix and in a matrix direction. A reconfigurable circuit used has been proposed (for example, Patent Document 2 and Non-Patent Document 1). In this reconfigurable circuit, configuration information including an instruction set for controlling the function of the ALU and a connection data set for controlling a connection destination between the ALUs is set in each ALU, thereby functioning as a desired arithmetic processing circuit.

  A reconfigurable circuit using an ALU array has advantages in that the mounting size can be reduced as compared with a reconfigurable circuit using an FPGA, and the circuit can be reconfigured at high speed. For this reason, there is an advantage that a processing circuit corresponding to various standards can be realized by one LSI, and that a new standard can be immediately supported by software update.

  FIG. 9 is a diagram illustrating a configuration of the reconfigurable circuit 400 disclosed in Patent Document 2. In FIG. a11, a12, ..., a16, a21, ..., a26, a31, ..., a36 are ALUs. Each ALU has an arithmetic function set according to the setting data. For example, according to the setting data, it functions as an adder in some cases, a subtracter, a logical sum operator, a logical product operator, a bit shift arithmetic unit, etc. in some cases.

  Further, the reconfigurable circuit 400 has a structure including a plurality of sets of logic circuits based on ALU. That is, the first-stage logic circuit composed of a11,..., A16 forms an aggregate g1, and the second-stage logic circuit composed of a21,..., A26 forms an aggregate g2, and includes three stages composed of a31,. The logic circuit of the eye forms an aggregate g3.

  Further, the output of the calculation by the ALU is limited to the next-stage ALU arranged in the same column and the ALUs arranged in the left and right columns. For example, with regard to a22, the calculation output is connected only to a31, a32, and a33. As described above, in the reconfigurable circuit 400, the connection of the arithmetic output by the ALU is limited to the ALU in the same column in the next stage and the ALUs in the left and right columns (a circuit configuration having a so-called connection limitation), The scale is being reduced.

FIG. 10 shows an execution example of the operation by the reconfigurable circuit 400. This is the output from the ALUa 13 and ALUa 14 arranged in the first stage (referred to as A and B, respectively) by the ALUa 23 arranged in the second stage (execution of A + B) is arranged in the third stage. Are output to the ALUa 33, and the outputs from the ALUa13 and ALUa14 are subtracted by the ALUa24 arranged in the second stage (A-B calculation is executed) and output to the ALUa34 arranged in the third stage.
Japanese Patent Laid-Open No. 10-256383 JP 2005-182654 A : "Small Reconfigurable Device for Information Appliances", Sanyo Engineering Reports VOL.37, No.2, MARCH 2006 Volume 77

  When the processing circuit is realized by the above reconfigurable circuit, depending on the processing contents, a multi-bit operation exceeding the number of operation bits that the ALU of the reconfigurable circuit can perform may be required. That is, realization of multiple length arithmetic using a reconfigurable circuit is required.

  In general, a multiple-precision operation means performing, for example, a 32-bit operation (double-length operation) or a 48-bit operation (triple-length operation) using an ALU having an operation bit width of 16 bits. Say. The double length operation in the addition operation can be executed by passing the carry of the addition performed by the ALU to the upper ALU.

  In order to perform multiple length arithmetic, it is first considered to change the reconfigurable circuit 400 of Patent Document 2 to the reconfigurable circuit 300 shown in FIG. In this reconfigurable circuit 300, each ALU has a carry output c, and this carry output is connected to the ALU located in the left adjacent column.

  An example in which double length addition is performed by the reconfigurable circuit 300 of FIG. 11 will be described with reference to FIG. Here, an example will be described in which the arithmetic bit width of the ALU is 16 bits, and A and B which are 32-bit variables are added to obtain an addition result C (32-bit variable). First, the output from ALUa14 is AL, which is the lower 16-bit data of A, the output from ALUa15 is BL, which is the lower 16-bit data of B, and the output from ALUa12 is the upper 16-bit data of A, AH, ALUa13 Assume that the output is BH, which is the upper 16-bit data of B. The calculation of the lower data is performed by the ALU a 24 to which the addition function is assigned, and the operation result AL + BL is output to the ALU a 34 as CL which is the lower 16 bits of C. The carry is output to the ALU a23. On the other hand, the calculation of the upper data is performed by the ALUa 23 to which the addition function is assigned, and the AH + BH + carry as the operation result is output to the ALUa 33 as CH which is the upper 16 bits of C. In this way, double length calculation is possible.

  However, in the reconfigurable circuit 300 of FIG. 11, a double-length operation may not be executed depending on the content of the operation. In a reconfigurable circuit with connection restrictions such as the reconfigurable circuit 300, the operation output destination from the ALU is limited, and therefore there is a restriction on the allocation of the ALU. In addition to this, when a double length operation is to be executed, it is necessary to consider the carry output. In particular, when the carry output is connected to the ALU in the adjacent column as in the reconfigurable circuit 300, the ALU This is because there are further restrictions on allocation. A specific example will be described below.

  With reference to FIG. 13, a case where simultaneous processing of addition and subtraction of A + B and AB is performed by double length calculation by the reconfigurable circuit 300 will be described. In order to perform a double length operation in the reconfigurable circuit 300, it is necessary to arrange an ALU that adds upper data and an ALU that adds lower data to be adjacent to each other. Similarly, the ALU that subtracts the upper data and the ALU that subtracts the lower data need to be arranged adjacent to each other. For example, A upper data AH and lower data AL are set in ALUa12 and a13, B upper data BH and lower data BL are set in ALUa14 and a15, respectively, and upper addition and lower addition are executed in ALUa22 and a23, respectively. It is assumed that upper subtraction and lower subtraction are executed by ALUa 24 and ALUa 25, respectively. In this case, it is necessary to input AL and BL to the ALUa 23 in order to perform the lower addition, but since the BL is set to the ALUa 15 at the upper right of the two columns, the reconfigurable circuit 300 performs the addition by the a23. I can't do it.

  In view of the above problems, an object of the present invention is to provide an arithmetic processing circuit that can efficiently perform multiple-length arithmetic in an arithmetic processing circuit such as a reconfigurable processor.

  An embodiment of the present invention includes a plurality of logic circuit units configured in a matrix in the stage direction and the column direction, and an operation output from a predetermined logic circuit unit is one of the logic circuit units arranged in the next stage. An arithmetic processing circuit configured to be connected to a limited number of logic circuit units, wherein the predetermined logic circuit unit includes a carry output, and the carry output is two or more columns from the predetermined logic circuit unit It is characterized in that it is configured to be connected to a logic circuit portion located in a remote column.

  In such an arithmetic processing circuit, for example, when the operation output destination from the logic circuit unit is limited to only the logic circuit unit arranged in the adjacent column, the carry output is connected to the logic circuit unit in the remote column, Since restrictions on ALU allocation during execution of double length operations can be relaxed, multiple length operations can be performed efficiently.

  The arithmetic processing circuit further includes a state holding unit that holds an arithmetic output from the logic circuit unit, and the arithmetic output from the logic circuit unit is input to the next-stage logic circuit unit via the state holding unit. The carry output from the predetermined logic circuit unit may be connected to the logic circuit unit located at the next stage of the predetermined logic circuit unit.

  In the arithmetic processing circuit of this aspect, the arithmetic output from the predetermined logic circuit unit is arranged within p columns (where p is a natural number) from the predetermined logic circuit unit among the logic circuit units arranged in the next stage. The carry output is configured to be connected to a logic circuit unit located in a column separated by (p + 1) columns or more from the predetermined logic circuit unit. Anyway.

  Another aspect of the present invention includes a plurality of logic circuit units configured in a stage direction, and an operation output from a predetermined logic circuit unit is limited to a part of the plurality of logic circuits. Arithmetic circuit configured to be connected to each other, wherein the predetermined logic circuit unit includes a carry output, and the carry output is located in a column separated from the predetermined logic circuit unit by two or more columns It is comprised so that it may connect to a part.

  In such an arithmetic processing circuit, the circuit scale can be reduced in addition to the efficiency of the multiple length arithmetic.

  In the arithmetic processing circuit of this aspect, the arithmetic output from the predetermined logic circuit unit is limited to the logic circuit unit arranged within p columns (where p is a natural number) from the predetermined logic circuit unit. The carry output may be connected to a logic circuit unit separated by (p + 1) columns or more from the predetermined logic circuit unit.

  In the arithmetic processing circuit of each aspect described above, the logic circuit unit may be capable of changing the arithmetic function in accordance with setting data supplied from the outside of the logic circuit. Here, the calculation function refers to, for example, an addition operation or a subtraction operation.

  Further, in the arithmetic processing circuit of each aspect described above, n × k logic circuit units (where n and k are integers of 2 or more) are arranged on the same stage, and the predetermined logic circuit unit outputs a carry output. The carry output may be configured to be connected to a logic circuit unit located in a column separated by k columns from the predetermined logic circuit unit.

  According to the present invention, multiple length arithmetic can be efficiently performed in an arithmetic processing circuit having a so-called connection restriction.

  FIG. 1 is a diagram illustrating a configuration of a processing device 10 and a configuration of a setting data generation device 30 according to the embodiment.

<Configuration of Processing Device 10>
The processing device 10 includes an integrated circuit configured as one chip, and includes a reconfigurable circuit 12, a setting unit 14, and a control unit 18.

  The reconfigurable circuit 12 has a structure including a plurality of logic circuits using ALUs whose functions can be changed. Such a reconfigurable circuit 12 functions as an arithmetic circuit that operates in accordance with setting data supplied from a setting unit 14 to be described later. That is, the reconfigurable circuit 12 performs an operation according to the setting data on externally input data, and outputs an operation result. The configuration of the reconfigurable circuit 12 will be described in detail later. The reconfigurable circuit 12 corresponds to an example of an arithmetic processing circuit according to the present invention.

  The setting unit 14 supplies setting data for configuring a desired arithmetic circuit to the reconfigurable circuit 12. By supplying setting data from the setting unit 14, the reconfigurable circuit 12 is configured as a desired arithmetic circuit. This setting data is generated by a setting data generation device 30 described later.

  The control unit 18 controls each unit of the processing apparatus 10, that is, the reconfigurable circuit 12 and the setting unit 14.

<Configuration of Setting Data Generating Device 30>
The setting data generation device 30 analyzes a program that sets the operation of processing to be realized by the reconfigurable circuit 12 and generates setting data for mapping to the reconfigurable circuit 12. This setting data determines the function of the logic circuit in the reconfigurable circuit 12 and the connection relationship between the logic circuits. The setting data generated by the setting data generation device 30 is supplied to the reconfigurable circuit 12 via the setting unit 14.

<Configuration of Reconfigurable Circuit 12 (Part 1)>
FIG. 2 is a schematic diagram of the reconfigurable circuit 12. The reconfigurable circuit 12 includes a plurality of ALUs (a11, a12,..., A16, a21,..., A26, a31,..., A36) arranged in a matrix in the step direction and the column direction. This embodiment is an example in the case of p = 1 as referred to in the claimed invention.

  Each ALU has an arithmetic function set according to the setting data. For example, according to the setting data, it functions as an adder in some cases, a subtracter in other cases, a logical sum operation unit, a logical product operation unit, a bit shift operation unit,. In addition, the first stage logic circuit by a11,..., A16 forms an aggregate g1, and the second stage logic circuit by a21,..., A26 forms an aggregate g2, and three stages by a31,. The logic circuit of the eye is configured to form an aggregate g3.

  Further, the output of the calculation by the ALU is limited to the next-stage ALU arranged in the same column and the ALUs arranged in the left and right columns. In other words, the output of the operation by the ALU is limited and connected to other ALUs arranged within one column from the ALU. For example, with regard to a22, the calculation output is connected only to a31, a32, and a33.

  Some ALUs have carry outputs (here, a25, a26). Carry outputs from these ALUs are configured to connect to other ALUs located in a row three columns away from the ALU. For example, the carry output from ALUa 25 is connected to ALUa 22, and the carry output from ALUa 26 is connected to ALUa 23. In the reconfigurable circuit 12, since the number of columns in which the carry output is separated is 3, this number of columns 3 satisfies the condition of (p + 1) or more, that is, 2 or more, as stated in the invention of the claims.

  With reference to FIG. 3, an example in which double length addition / subtraction (A + B and AB) by the reconfigurable circuit 12 of FIG. 2 is simultaneously processed will be described. Here, it is assumed that the operation bit width of each ALU of the reconfigurable circuit 12 is 16 bits, and A and B are 32-bit variables. First, the output data from ALUa 15 is AL, which is the lower 16-bit data of A, the output data from ALUa 16 is BL, which is the lower 16-bit data of B, and the output data from ALUa 12 is AH, which is the upper 16-bit data of A. Assume that the output data from the ALUa 13 is BH, which is the upper 16-bit data of B.

  The lower addition is performed by the ALUa 25 to which the addition function is assigned, and the addition result CL is output to the ALUa 35. The carry generated by the addition at ALUa 25 is output to ALUa 22. On the other hand, the higher-order addition is performed by the ALUa 22 to which the addition function is assigned, and CH as the addition result is output to the ALUa 32.

  On the other hand, the lower order subtraction is performed by the ALUa 26 to which the subtraction function is assigned, and the DL as the subtraction result is output to the ALUa 36. The carry generated by the subtraction at the ALUa 26 is output to the ALUa 23. On the other hand, the upper subtraction is performed by the ALUa 23 to which the subtraction function is assigned, and the subtraction result DH is output to the ALUa 33.

  In the reconfigurable circuit 12, since the carry output is connected to the ALU located in a column separated by three columns, the ALU that performs the upper data calculation and the ALU that performs the lower data calculation can be arranged separately. Does not interfere with connection restrictions. Therefore, the arrangement of the ALU that performs the upper calculation and the ALU that performs the lower calculation can be executed by the same arrangement of the ALU as in the case of the single precision calculation, so that the multiple length calculation can be performed efficiently. it can. In other words, double-length arithmetic can be performed without reducing circuit utilization efficiency and arithmetic execution speed.

  In FIG. 2, it is described that only some ALUs have carry outputs, but all ALUs may have carry outputs. On the other hand, for example, by setting a rule such that addition / subtraction is performed by an even number of ALUs in advance, it is possible to provide a carry output only for some ALUs. As a result, the wiring of the carry output can be suppressed to the minimum necessary, and the reconfigurable circuit can be reduced in size and power consumption can be reduced.

<Configuration example of reconfigurable circuit (2)>
FIG. 4 shows a configuration of the reconfigurable circuit 12B.

  In the reconfigurable circuit 12B, each logic circuit (L11,..., L64) includes an ALU and a D-type flip-flop (hereinafter referred to as “DFF”) that receives an operation output from each ALU. This embodiment is also an example in the case of p = 1 as referred to in the claimed invention.

  Output data from each ALU stored in the DFF is output to the next-stage ALU in synchronization with the clock. As a result, pipeline processing can be performed, and different operations can be simultaneously executed by the ALUs of the respective stages.

  Some ALUs have carry outputs (for example, a42, a52, a62). The carry outputs from these ALUs are connected to the ALUs located in the next three columns away via the carry DFF (d1, d2, or d3). In the reconfigurable circuit 12B, since the number of columns in which the carry output is separated is 3, the condition of (p + 1) or more, that is, 2 or more as defined in the claimed invention is satisfied.

  With reference to FIG. 5, an example in which double length addition (A + B) and double length subtraction (AB) are simultaneously processed by the reconfigurable circuit 12B will be described.

  First, at the first timing, AL and BL are output from the ALUs a51 and a61 of the first stage logic circuits L51 and L61, respectively. Further, AL and BL are also stored in DFFs d51 and d52 of the logic circuits L51 and L61, respectively.

  Next, at the second timing, the data stored in d51 and d61 are output to both ALUs 52 and a62 of the second stage logic circuits L52 and L62. In a52, AL and BL are added. The addition result CL is stored in the DFF d52 of the logic circuit L52, and the carry by the addition is stored in the carry DFF (d2). On the other hand, at a62, AL and BL are subtracted. The subtraction result DL is stored in the DFF d62 of the logic circuit L62, and the carry by the subtraction is stored in the carry DFF (d3). At the second timing, AH and BH are output from the ALUs a22 and a32 of the first-stage logic circuits L22 and L32, respectively. Further, AH and BH are also stored in DFFs d22 and d32 of the logic circuits L22 and L32, respectively.

  At the third timing, the data stored in the DFFs d22, d32, d42, and d52 and the carry DFFs d2 and d3 are output to the third-stage logic circuit. The ALUa23 of the logic circuit L23 receives AH from L22, BH from L32, and carry from d2, and these addition operations are performed in a23. CH that is the addition result is stored in DFF d23. The ALUa33 of the logic circuit L33 receives AH from L22, BH from L32, and carry from d3, and these subtraction operations are performed at a33. The subtraction result DH is stored in DFFd33.

  At the third timing, CL from L52 is input to ALUa53 of the logic circuit L53, and DH from L62 is input to ALUa63 of the logic circuit L63.

  At the fourth timing, the data stored in d23 and d33 is output to the fourth-stage logic circuit. Then, CH from L23 is input to ALUa24 of logic circuit L24, and DH from L33 is input to ALUa34 of logic circuit L34.

  As described above, double-length addition / subtraction (A + B) and (A−B) can be simultaneously processed by the reconfigurable circuit 12B.

  Further, the reconfigurable circuit 12B can perform pipeline processing of operations. For example, at the second timing, values different from the AL and BL are respectively set in the ALUs a51 and a61 in the first stage logic circuits L51 and L61, and at the third timing, the second stage logic circuit L22. By setting a variable different from AH and BH in ALUa22 and a32 in L32, it is possible to execute an operation different from the addition / subtraction (A + B) and (A−B).

  Further, according to the reconfigurable circuit 12B, it is possible to improve the calculation speed when performing such pipeline processing. For example, when the carry output is connected to an ALU located in a column separated by three columns in the same stage, the ALU that performs upper addition needs to wait for the carry input from the ALU that performs lower addition. If the period of one clock is set in consideration of this waiting time, the period of one clock becomes long and the calculation becomes slow. On the other hand, in the reconfigurable circuit 12B, the logic circuit that performs the upper operation is arranged in the lower stage of the logic circuit that performs the lower operation, and the upper operation and the lower operation are executed at different timings. There is no need to consider time, and the clock cycle can be shortened. Thereby, calculation speed can be improved.

<Configuration Example of Reconfigurable Circuit 12 (Part 3)>
In the reconfigurable circuit of the above example, the carry output from the ALU is connected and wired to the ALU located in a column separated by three columns, but the present invention is not limited to this.

  For example, when processing an n-fold length operation in a reconfigurable circuit in which n × k ALUs are arranged in the horizontal direction (same stage), the ALU is divided for each k pieces, It is conceivable to assign operations. In this case, the carry may be connected to an ALU located in a row separated by k rows.

  FIG. 6 shows an example in which a triple-length operation is performed using a reconfigurable circuit 12C in which six ALUs are arranged in the horizontal direction. The reconfigurable circuit 12C is configured such that the operation output by the ALU is limited to the next-stage ALU arranged in the same column and the ALU arranged in the left and right columns. The ALU is divided into two, and arithmetic units are assigned such as lower, middle, and upper operations. In this case, the carry connection is a connection between the lower level and the middle level, and the middle level and the higher level, and the carry is connected to an ALU located in a row two columns away.

  In this way, in each of the k ALUs, since the connection limit is affected only by the operation of the peer, it is not affected by the connection limit by the double length calculation, and becomes efficient. Note that the reconfigurable circuit 12C of this configuration example is also an example in the case of p = 1 in the invention of the claims. Further, in this reconfigurable circuit 12C, the number of columns in which the carry output is separated is 2, which satisfies the condition of (p + 1) or more, that is, 2 or more as stated in the invention of the claims.

<Configuration example of reconfigurable circuit (4)>
FIG. 7 is a diagram showing a configuration of a reconfigurable circuit 12D that loops back in a single-stage configuration. The output from each logic circuit is connected to the same logic circuit input and to the logic circuit inputs in the left and right columns. This embodiment is also an example in the case of p = 1 as referred to in the claimed invention.

  The ALU of each logic circuit can change the arithmetic function according to the setting data. By performing control to switch the type of calculation at each timing, for example, the same calculation as that shown in FIG. 4 can be performed.

  An execution example of double-length addition (A + B) and subtraction (AB) using such a reconfigurable circuit will be described below.

  First, at the first timing, AL that is the lower data of A from ALUa5 to BL that is the lower data of ALUa6 to B is set. Further, AL is held in DFF5 that receives the arithmetic output of ALUa5, and BL is held in DFF6 that receives the arithmetic output of ALUa6.

  At the next second timing, the addition function is set to ALUa5 and the subtraction function is set to ALUa6. AL and BL stored in DFF5 and DFF6 are output to both a5 and a6. In ALUa5, an addition operation by AL output from DFF5 and BL output from DFF6, that is, addition of lower data is performed. On the other hand, in ALUa6, a subtraction operation by AL output from DFF5 and BL output from DFF6, that is, subtraction of lower-order data is performed. CL, which is the addition result in ALUa5, is stored in DFF5, and DL, which is the subtraction result in ALUa6, is stored in DFF6. Carries generated by addition and subtraction in ALUs a5 and a6 are output to carry DFF1 and carry DFF2, respectively. In the reconfigurable circuit 12C, since the number of columns in which the carry output is separated is 3, the condition of (p + 1) or more, that is, 2 or more as defined in the claimed invention is satisfied.

  At the second timing, AH, which is the upper data of A, is set in ALUa2, and BH, which is the upper data of B, is set in ALUa3. DFF2 holds AH and DFF3 holds BH.

  At the next third timing, the addition function is set to ALUa2, and the subtraction function is set to ALUa3. AH and BH respectively stored in DFF2 and DFF3 are output to both a2 and a3. The carry stored in carry DFF1 and carry DFF2 is output to a2 and a3, respectively. In ALUa2, addition operation is performed by the AH output from the DFF2, the BH output from the DFF3, and the carry output from the carry DFF1, that is, the upper data is added. On the other hand, in ALUa3, subtraction is performed by the AH output from DFF2, the BH output from DFF3, and the carry output from carry DFF2, that is, the upper data is subtracted.

  At the third timing, CL, which is the lower addition result at the second timing, is output to ALUa5, and DL, which is the lower subtraction result at the second timing, is output to ALUa6.

  At the subsequent fourth timing, CH, which is the upper addition result at the third timing, is output to ALUa2, and DH, which is the upper subtraction result at the third timing, is output to ALUa3. As described above, the double length operation can be realized also by a reconfigurable circuit configured to be looped back in a single stage configuration.

  The above-described embodiment is to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and is intended to include meanings equivalent to the scope of claims for patent and all modifications within the scope.

  In the above description, the reconfigurable circuit that performs the double length operation is described as an example. However, a reconfigurable circuit that performs both the double length operation and the single precision operation is also included in the scope of the present invention. For example, it can be realized by configuring a part of the reconfigurable circuit 12B of FIG. 4 as shown in FIG. For example, a selector MUX is provided in front of carry inputs of ALUs such as a13, a23, and a33, and when performing a single precision operation, 0 is selected by the MUX, and a double length operation is performed. The carry input from the lower bits (for example, in the example of FIG. 8, the output of DFFd3 that temporarily holds the carry output of a62) may be selected by the MUX. Note that not only the reconfigurable circuit 12B but also the reconfigurable circuits 12, 12C, and 12D can perform both double length arithmetic and single precision arithmetic by performing the same improvement.

It is a figure which shows the structure of the processing apparatus 10 and setting data generation apparatus 30 which concern on embodiment. 2 is a schematic diagram showing a configuration of a reconfigurable circuit 12. FIG. It is a figure explaining the example which processes double length addition (A + B) and double length subtraction (AB) simultaneously by the reconfigurable circuit 12. FIG. It is a schematic diagram which shows the structure of the reconfigurable circuit 12B. It is a figure explaining the example which processes double length addition (A + B) and double length subtraction (AB) simultaneously by the reconfigurable circuit 12B. It is a figure which shows the example which performs a 3 times length calculation using the reconfigurable circuit which arranged 6 ALU in the same stage. It is a schematic diagram which shows the structure of reconfigurable circuit 12D. It is a figure which shows a part of reconfigurable circuit 12B in which both a double length calculation and a single precision calculation are possible. FIG. 6 is a schematic diagram of a conventional reconfigurable circuit 400. FIG. 6 is a diagram illustrating an execution example of a calculation by the reconfigurable circuit 400. 3 is a schematic diagram of a reconfigurable circuit 300. FIG. 5 is a diagram illustrating an example in which double length addition is performed by the reconfigurable circuit 300. FIG.

It is a figure which shows the example which processes double length addition (A + B) and double length subtraction (AB) simultaneously by the reconfigurable circuit 300. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Processing apparatus 12 Reconfigurable circuit 14 Setting part 18 Control part 30 Setting data generation apparatus

Claims (7)

Provided with a plurality of logic circuit sections arranged in a matrix in the step direction and the column direction,
Operation output from a given logic circuit portion, the configured Rutotomoni logic circuit portion upper level computing and lower operations to be connected is limited to the logic circuit section of a part of the logic circuit portion disposed on the next stage An arithmetic processing circuit that individually executes and performs multiple length arithmetic ,
The predetermined logic circuit unit that executes the lower operation includes a carry output, and the carry output is configured to be connected to an upper operation logic circuit unit located in a column that is two or more columns away from the predetermined logic circuit unit. An arithmetic processing circuit characterized by that. A state holding unit for holding an operation output from the logic circuit unit;
The operation output from the logic circuit unit is input to the logic circuit unit of the next stage through the state holding unit,
The arithmetic processing circuit according to claim 1, wherein a carry output from the predetermined logic circuit unit is configured to be connected to a logic circuit unit located at a next stage of the predetermined logic circuit unit. Provided with a plurality of logic circuit parts configured in the stage direction,
Operation output from a given logic circuit section, among the plurality of logic circuits, perform individually configured Rutotomoni logic circuit portion upper level computing and lower operations to be connected are restricted to a subset of the logic circuit portion An arithmetic processing circuit that performs multiple length arithmetic ,
The lower operation predetermined logic circuit unit includes a carry output, and the carry output is configured to be connected to an upper operation logic circuit unit located in a column separated from the predetermined logic circuit unit by two or more columns. An arithmetic processing circuit. An operation output from the predetermined logic circuit unit is limited to a logic circuit unit arranged within p columns (where p is a natural number) from the predetermined logic circuit unit among the logic circuit units arranged in the next stage. Configured to be connected
3. The arithmetic processing according to claim 1, wherein the carry output is configured to be connected to a logic circuit unit located in a column separated by (p + 1) columns or more from the predetermined logic circuit unit. 4. circuit. An arithmetic output from the predetermined logic circuit unit is limited and connected to a logic circuit unit arranged within p columns (where p is a natural number) from the predetermined logic circuit unit,
4. The arithmetic processing circuit according to claim 3, wherein the carry output is configured to be connected to a logic circuit unit separated by (p + 1) columns or more from the predetermined logic circuit unit. 5.   The arithmetic processing circuit according to claim 1, wherein the logic circuit unit can change an arithmetic function in accordance with setting data supplied from the outside of the logic circuit. On the same stage, n × k logic circuits (where n and k are integers of 2 or more) are arranged,
The predetermined logic circuit unit includes a carry output, and the carry output is configured to be connected to a logic circuit unit located in a column separated by k columns from the predetermined logic circuit unit. The arithmetic processing circuit according to any one of 1 to 6.