JP4597075B2 - Operation mapping method to reconfigurable circuit, reconfigurable circuit, and data flow graph - Google Patents

Description

  The present invention relates to an operation mapping method to a reconfigurable circuit, a reconfigurable circuit, and a data flow graph necessary for setting the operation of the reconfigurable circuit.

  Recently, wireless communications such as mobile phones, GPS, and VICS have become widespread, and the types of wireless devices are increasing. If these radios or their functions are all implemented by hardware, the cost and mounting area increase. Therefore, there is a concept of “software radio” that implements various functions by installing a circuit having general-purpose capability as hardware and switching software loaded thereon.

Circuits that implement a software defined radio include an FPGA (Field Programmable Gate Array) and a DSP (Digital Signal Processor). Patent Document 1 proposes a method of reusing a circuit configuration by dynamically reconfiguring an FPGA. The type of circuit that can be dynamically changed is hereinafter referred to as a reconfigurable circuit.

The FPGA can design circuit configuration relatively freely by writing circuit data after the LSI is manufactured, and is used for designing dedicated hardware. The FPGA includes a lookup table (LUT) for storing a truth table of a logic circuit, a basic cell composed of an output flip-flop, and a programmable wiring resource connecting the basic cells. In the FPGA, a target logical operation can be realized by writing data stored in the LUT and wiring data. However, when an LSI is designed using an FPGA, the mounting area is very large and the cost is high as compared with an ASIC (Application Specific IC) design. In view of this, there has been proposed a method of measuring the reuse of the circuit configuration by dynamically configuring the FPGA (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 10-256383

  For example, in satellite broadcasting, image quality may be adjusted by switching broadcast modes depending on the season. In the satellite broadcast receiver, a plurality of circuits are built in hardware for each broadcast mode in advance, and the circuit is switched by a selector according to the broadcast mode for reception. Therefore, the other broadcast mode circuits of the receiver are idle during that time. When switching and using multiple dedicated circuits, such as mode switching, and the switching interval is relatively long, instead of creating multiple dedicated circuits, the LSI can be reconfigured instantaneously at the time of switching. The structure can be simplified and versatility can be improved, and at the same time the mounting cost can be reduced. In order to meet such needs, the manufacturing industry has become increasingly interested in dynamically reconfigurable LSIs. In particular, LSIs mounted on mobile terminals such as mobile phones and PDAs (Personal Digital Assistants) need to be miniaturized. If LSIs can be dynamically reconfigured and functions can be switched appropriately according to the application, The mounting area can be kept small.

The FPGA has a high degree of design freedom in circuit configuration and is general-purpose. On the other hand, to enable connection between all the basic cells, it is necessary to include a control circuit for controlling ON / OFF of the switches. This inevitably increases the mounting area of the control circuit. Moreover, since a complicated wiring pattern is used for connection between basic cells, the wiring tends to be long. Furthermore, the delay is increased because of the structure in which many switches are connected to one wiring. For this reason, FPGA based LSIs are often used only for trial manufacture and experiments, and are not suitable for mass production in view of mounting efficiency and performance cost. Furthermore, in the LSI based on the FPGA, it is necessary to send setting data to a large number of basic cells of the LUT method, so that considerable time is required for circuit configuration. For this reason, FPGA LSIs are not suitable for applications that require instantaneous switching of the circuit configuration.

In order to solve these problems, in recent years, a reconfigurable processor using a multi-functional element called ALU (Arithmetic Logic Unit) having a plurality of basic arithmetic functions has been developed. In the reconfigurable processor, the command data is set to control the arithmetic function configuration and the connection part of the ALU circuit, so that the desired arithmetic processing circuit can be realized as a whole. Command data is generally created based on the data flow called DFG (Data Flow Graph) created from a source program written in a high-level programming language such as C language.

  However, in the conventional data flow creation method, it is assumed that the calculation is performed for general purposes, and the number of ALUs required for one calculation is large, the circuit scale is increased, and the processing time of the circuit is increased accordingly. There was a problem.

  The present invention has been made in view of such a situation, and in a reconfigurable circuit, an operation mapping method to a reconfigurable circuit that contributes to a reduction in circuit scale and a reduction in processing time, and the like are used. An object is to provide a reconfigurable circuit.

In order to achieve the above object, an operation mapping method to a reconfigurable circuit according to the first aspect of the present invention includes:
A reconfigurable circuit comprising: an arithmetic unit composed of a plurality of logic circuits each capable of selectively executing a plurality of arithmetic logic operation functions; and a connection unit for maintaining a connection relationship between the plurality of logic circuits. In addition, there is an operation mapping method for mapping an intended operation function,
An effective bit number determination step for determining the effective bit number of the input of the intended arithmetic function based on the bit number designation means for designating the effective bit number of the input of the intended arithmetic function;
A mapping step of mapping the intended arithmetic function to the reconfigurable circuit based on the effective bit number determined in the effective bit number determining step;
It is characterized by providing.

The operation mapping method to the reconfigurable circuit according to the second aspect of the present invention is as follows:
A reconfigurable circuit comprising: an arithmetic unit composed of a plurality of logic circuits each capable of selectively executing a plurality of arithmetic logic operation functions; and a connection unit for maintaining a connection relationship between the plurality of logic circuits. In addition, there is an operation mapping method for mapping an intended operation function,
A sign determination step for determining a sign of an input of the expected arithmetic function based on a sign specifying means for specifying a sign of the input of the expected arithmetic function;
A mapping step for mapping the intended arithmetic function to the reconfigurable circuit based on the code determined in the code determination step;
It is characterized by providing.

Preferably, the effective bit number of the input of the intended arithmetic function is determined based on a bit number specifying means for specifying the effective bit number of the input of the intended arithmetic function and a sign specifying means for specifying the sign of the input An effective bit number determining step, and a code determining step for determining a sign of an input of the intended arithmetic function,
The mapping step maps the expected arithmetic function to the reconfigurable circuit based on the effective bit number determined in the effective bit number determination step and the code determined in the code determination step.
It is characterized by that.

In particular, the intended calculation function includes division or remainder calculation,
The mapping step maps the division or remainder calculation to a process including repetition of subtraction for the effective bit number of the dividend of the division or remainder calculation.
It is characterized by that.

  Preferably, the number-of-bits designating means for designating an effective number of input bits of the intended arithmetic function is a source program that expresses the intended arithmetic function in a programming language.

  The effective bit number determining step determines the effective bit number of the input based on the comment description of the source program.

  Preferably, the code designating means for designating an input code of the intended arithmetic function is a source program expressing the intended arithmetic function in a program language.

  The code determination step is characterized in that an input code is determined based on a description of a comment of the source program.

A reconfigurable circuit according to a third aspect of the present invention is:
Operate according to data obtained from the result of the operation mapping method to any one of the reconfigurable circuits according to the first aspect or the operation mapping method to any one of the reconfigurable circuits according to the second aspect It is characterized by doing.

The data flow graph according to the fourth aspect of the present invention is:
A reconfigurable circuit comprising: an arithmetic unit composed of a plurality of logic circuits each capable of selectively executing a plurality of arithmetic logic operation functions; and a connection unit for maintaining a connection relationship between the plurality of logic circuits. In addition, a data flow graph necessary for setting the operation of the expected calculation function,
When the desired calculation function is decomposed into repetitive calculations according to the number of input bits of the calculation, the predetermined calculation function is determined based on a source program expressing the calculation function in a programming language. The number of repetitions of the repetitive operation is reduced in correspondence with the number of effective bits input to the operation function of the period.

The data flow graph according to the fifth aspect of the present invention is:
A reconfigurable circuit comprising: an arithmetic unit composed of a plurality of logic circuits each capable of selectively executing a plurality of arithmetic logic operation functions; and a connection unit for maintaining a connection relationship between the plurality of logic circuits. In addition, a data flow graph necessary for setting the operation of the expected calculation function,
In the case where the intended arithmetic function includes the input sign determination process so that the sign of the input of the intended arithmetic function is processed corresponding to either positive or negative,
The code determination process is omitted corresponding to the input code of the expected calculation function, which is determined based on a source program expressing the expected calculation function in a programming language.

According to the operation mapping method to the reconfigurable circuit of the present invention, it is possible to reduce the number of operation circuits that have been invalidated because the operations are conventionally mapped to general-purpose processing. The scale can be reduced, power consumption can be reduced, and calculation processing can be speeded up.

  An operation mapping method to a reconfigurable circuit and an embodiment of the reconfigurable circuit according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a processing apparatus including a reconfigurable circuit according to an embodiment of the present invention. As shown in FIG. 1, the processing apparatus 10 includes an integrated circuit device 26. The integrated circuit device 26 has a function that makes it possible to reconfigure the circuit configuration. The integrated circuit device 26 is configured as one chip, and includes a reconfigurable circuit 1, a setting unit 14, a control unit 18, an internal state holding circuit 20, an output circuit 22, and a path unit 24. The reconfigurable circuit 1 can change the function by changing the setting.

  The setting unit 14 includes a first setting unit 14a, a second setting unit 14b, a third setting unit 14c, a fourth setting unit 14d, and a selector 16, and configures an intended circuit in the reconfigurable circuit 1. The setting data 40 is supplied. The path unit 24 functions as a feedback path, and connects the output of the reconfigurable circuit 1 to the input of the reconfigurable circuit 1. The internal state holding circuit 20 and the output circuit 22 are configured by a sequential circuit such as a data flip-flop (D-FF) or a memory, for example, and receive the output of the reconfigurable circuit 1. The internal state holding circuit 20 is connected to the path unit 24. The reconfigurable circuit 1 is configured as a combinational circuit or a sequential circuit including state holding such as D-FF.

  FIG. 2 is a diagram illustrating a configuration example of the reconfigurable circuit 1 using an ALU array. As shown in FIG. 2, the reconfigurable circuit 1 has a structure including a plurality of sets of logic circuits 2 that are operation units including an ALU (arithmetic logic operation unit) and the like whose functions can be changed. And having at least one connection portion 3 provided between the respective assemblies and capable of selectively establishing the connection of the logic circuit 2 between the assemblies.

  In the reconfigurable circuit 1, a plurality of logic circuits 2 that can selectively execute an arithmetic function are arranged in a matrix, and in the example of FIG. 2, an ALU array of X stages and Y columns is configured and arranged in each stage. The plurality of logic circuits 2 thus configured constitute an aggregate, and the processing result in the upstream aggregate is delivered to the downstream aggregate according to the connection selectively established in the connection unit 3. The data transfer between the logic circuits from the upper stage to the lower stage is determined to which logic circuit 2 in the lower stage the data is transferred by setting a connection data set in a connection switch for switching the connection between the logic circuits. During operation, arithmetic processing is performed according to the configuration information and the result is output.

  The function of each logic circuit 2 and the connection relationship between the logic circuits 2 are set based on setting data 40 supplied by the setting unit 14 shown in FIG. The setting data 40 is generated by the following procedure.

  A source program 36 that describes arithmetic functions to be realized by the integrated circuit device 26 is held in the storage unit 34. The source program 36 describes a signal processing circuit or a signal processing algorithm in a high-level language such as C language. The compiling unit 30 compiles the source program 36 stored in the storage unit 34, converts it into a data flow graph (DFG) 38, and stores it in the storage unit 34. The data flow graph 38 is a graph structure representing operations or data flow from input data to output data by input variables and constants. Here, the compiling unit 30 generates the data flow graph 38 according to the connection restriction of the assembly of the logic circuits 2 in the reconfigurable circuit 1.

  The setting data generation unit 32 generates setting data 40 from the data flow graph 38. The setting data 40 is data for mapping the data flow graph 38 to the reconfigurable circuit 1, and defines the function of the logic circuit 2 in the reconfigurable circuit 1 and the connection relationship between the logic circuits.

  The reconfigurable circuit 1 can be regarded as a general-purpose processor in which logic circuits 2 are arranged in a matrix. The data flow graph 38 and the setting data 40 are considered to correspond to a kind of program or the like for instructing the processor.

(Embodiment 1)
In the first embodiment, an operation mapping method to the reconfigurable circuit 1 of the present invention will be described by taking division as an example. FIG. 3 shows an example of the division source program 36 as an example of the mapping method according to the embodiment.

  As one method for realizing division by a logical operation circuit, there is a method in which a division function is incorporated in a logic circuit and a division instruction is given to the logic circuit to perform division. However, division has a large circuit scale. For example, if all logic circuits have a division function, the circuit scale becomes enormous and the signal delay of one arithmetic means increases, resulting in the circuit scale of the entire reconfigurable circuit. Leads to an increase in the calculation speed and a decrease in calculation speed.

  As a method for solving this problem, there is a method of dividing the division into a so-called handwriting calculation method and realizing the division by giving only a simple instruction to one logic circuit. However, in this case, the number of necessary logic circuits increases. In addition, a method of assigning a certain pattern of computation to one computing means using the regularity of division by the calculation method of writing can be considered.

  FIG. 4 is an example of a data graph representing one-stage subtraction processing when division is decomposed into a calculation method of writing composed of multi-stage subtraction. In FIG. 4 and the like, the data flow graph 38 is represented as a drawing using circles, squares, symbols therein and arrow lines so that the data flow graph 38 can be easily understood visually. The graph 38 is expressed in a data format indicating the number of the node representing the logic circuit 2, the contents of the arithmetic processing, the input / output relationship between the nodes, and the like.

  In FIG. 4A, the variable x represented by the input P is a dividend, and the variable y represented by the input Q is a divisor. Variables x and y are integers in binary notation and are expressed in two's complement. The condition is that the variables x and y are positive numbers. The variable ret represented by the output R is the result of the subtraction one-stage process, and the division result of this digit is recorded in the number and the least significant bit of the next subtraction dividend.

  The subtraction stage constituting the division is performed as follows. First, the dividend x is shifted to the left by 1 bit (step A1). The divisor y is subtracted from the dividend shifted by 1 bit (step A2). 1 (input A7) is added to the subtraction result (step A5). In the meantime, the dividend shifted to the left by 1 bit is held as it is (step A3, step A4). The mov instruction is an operation (holding circuit) that directly transfers an input to an output.

  The result of step A2 is also input to step A6. In step A6, it is determined whether or not it is larger than “0” (input A8). If the result of step A2 is positive, the result of step A6 is true, and if the result of step A2 is not positive, the result of step A6 is false. The broken line at the output of step A6 indicates that the value is a truth value.

“Merge” in step A9 represents a logical operation for selecting one of the two solid line inputs in accordance with the truth of the broken line input. When the broken line input is true, the input indicated by T is selected from the solid line inputs.

  In step A9, the result of step A4 or the result of step A5 is selected according to the result of step A6. If the result of step A6 is true, a result obtained by subtracting the divisor y from the result of step A5, that is, the dividend shifted by 1 bit, and adding 1 is selected. If the result of step A6 is false, the result of step A4, that is, the dividend shifted by 1 bit is selected.

  If the result of subtracting the divisor from the value obtained by shifting the dividend to the left by 1 bit is positive (if the divisor can be subtracted), 1 is recorded in the least significant bit, and the result of subtracting the divisor remains in the upper bit ing. If the result of subtracting the divisor from the value obtained by shifting the dividend to the left by 1 bit is not positive, the dividend shifted by 1 bit to the left becomes the output R, and the least significant bit is 0. Therefore, the least significant bit of the output R is the quotient of the stage, and the dividend of the next stage remains in the upper bit, and FIG. 4A shows one subtraction stage when division is decomposed into the calculation method of writing. Represents the process.

  FIG. 4B shows that the processes of FIG. 4A are collectively expressed as div_x (step B1). div_x represents being decomposed into steps A1 to A9 in FIG.

  Returning to FIG. 3, the first line of the source program 36 is a comment field. The second line indicates that the quotient obtained by dividing the dividend x by the divisor y is substituted into the variable ret. The comment on the first line indicates that in the division on the second line, the dividend is positive and the number of effective bits is 5, the divisor is negative and the number of effective bits is 6.

  FIG. 3 is an example showing the dividend, the effective number of bits and the sign of the divisor in division. In the source program 36, how the dividend and the effective bit number and sign of the divisor are expressed is arbitrary. For example, the effective bit number and sign of a variable can be expressed by adding / and a signed integer after the variable of the variable type declaration statement.

  The compiling unit 30 of the processing device 10 reads the information described in the comment column of the source program 36 shown in FIG. 3, for example, and determines the dividend in division and the effective bit number and sign of the divisor. Then, a data flow graph (DFG) 38 corresponding to the dividend, the number of effective bits of the divisor, and the sign is generated.

  In addition, for example, the compiling unit 30 may read information added after the variable of the above-described variable type declaration statement, and determine the dividend and the effective bit number and sign of the divisor in the division. In addition, when the compiling unit 30 compiles the source program 36, for the variable whose configuration of the data flow graph 38 may change depending on the number of valid bits or the sign, the information on the number of valid bits or the sign of the variable is input to the operator. The effective bit number or sign of the variable may be determined based on the input information. Alternatively, the effective bit number or sign information of the variable may be read from a file different from the source program 36. In this case, the effective bit number or sign information of the variable read from the file is a kind of instruction given to the compiling unit 30 and can be considered as a part of the source program 36 in a broad sense.

FIG. 5 is a flowchart in which division processing is developed in consideration of the number of effective bits of the dividend in division. In FIG. 5, x_BIT represents the number of effective bits of the dividend x. Each variable in the flowchart of FIG. 5 corresponds to the source program 36 of FIG. FIG. 6 shows an example of the contents of variables in the flowchart of FIG. In FIG. 6, the dividend is 29 and the divisor is −5 as an example. The steps in FIG. 6 correspond to the steps (C1 etc.) in FIG. Also, the numbers other than the numbers with d indicating decimal numbers are binary numbers. In FIG. 6, the dividend x and the divisor y are 8 bits. The internal variables $ x and $ y are 16 bits, but the upper bits are omitted in FIG.

  The dividend x and divisor y as inputs are substituted into the double precision variables $ x and $ y, and the variable $ sign for determining the sign of the quotient is first set to 1 (positive) (step C1). In the example of FIG. 6, $ x is 11101 (decimal 29) and $ y is 11111011 (decimal -5). It is determined whether the dividend x is positive (step C2). If the dividend x is not positive (step C2; No), $ x is set to -x (that is, inverted to positive), and the sign of the quotient $ sign Is set to -1 (negative) (step C3). If the dividend is positive (step C2; Yes), the setting of step C1 is maintained. In the example of FIG. 6, step C3 is not executed because x is positive.

  Next, it is determined whether or not the divisor y is positive (step C4). If the divisor y is not positive (step C4; No), $ y is -y (that is, inverted to positive), and the sign of the quotient $ Sign is inverted (step C5). In the example of FIG. 6, since y is a decimal number of -5, $ y is 101 (decimal number 5), and $ sign is -1. If $ sign is negative in step C3, the dividend and the divisor are negative, so the quotient is positive, and $ sign is positive (+1). If the divisor is positive (step C4; Yes), the sign inversion of $ y and $ sign is not performed.

  Next, the variable $ x is shifted to the left by 1 bit, and if the sign of the quotient $ sign is negative, 1 is added (step C6). In this method, one bit separating the quotient finally set in the lower bits of the variable $ x and the dividend (remainder) is left, and the sign of the quotient is set in that bit. In FIG. 6, 1 bit separating the quotient from the dividend (the remainder) is represented by S. If the quotient is positive, S is 0, and if the quotient is negative, S is set to 1. In the example of FIG. 6, since the quotient is negative, S is 1. In FIG. 6, it is displayed as S for easy viewing.

  Next, in order to align the digit with the variable $ x, the variable $ y is shifted to the left by the effective bit number of the dividend x + 1 bit (step C7). In the example of FIG. 6, since the number of effective bits of x is 5, $ y is shifted to the left by 6 bits to become 0101000000.

  Next, step C9 is repeated for the number of effective bits of the dividend x (steps C8, C9, C10). In step C9, the process of div_x shown in FIG. 4B is performed with $ x as a dividend and $ y as a divisor. In the example of FIG. 6, the process of div_x is repeated 5 times. Steps C8, C9, and C10 in FIG. 6 show the result of $ x in each process of Step C9. The upper part of each column shows a state where the input $ x of div_x is shifted to the left by 1 bit. The lower part of each column shows the result of subtracting the divisor $ y and adding 1. The blank at the bottom indicates that the result of subtracting $ y is not positive. In this case, the value obtained by shifting the input $ x of div_x to the left by 1 bit is passed to the next processing as it is.

  In the first and second div_x (step C9), since $ x is smaller than $ y, $ x shifted to the left by 1 bit is passed to the next processing as it is. At the third time, $ x becomes larger than $ y, and a value obtained by adding 1 to the remainder obtained by subtracting $ y is passed to the next processing. In the fourth time, $ x is smaller than $ y, and $ x is only shifted 1 bit to the left. At the fifth time, $ x becomes larger than $ y, and a value obtained by adding 1 to the remainder obtained by subtracting $ y is output. As a result of repeating div_x five times, the lower 5 bits (right of S) of $ x are 00101, which is the absolute value of the quotient (29/5 = 5). The remainder of the division is shown on the left side of the symbol S.

In order to extract only the quotient of division from $ x, the logical product (&) of 2 ^x_BIT −1 and each bit is taken and substituted into the variable ret (step C11). The variable ret has the same precision as the dividend x and the divisor y (8 bits in the example of FIG. 6). In the example of FIG. 6, since x_BIT is 5, 2 ⁵ −1 (decimal) = 11111 (binary), and the lower 5 bits (00101) of $ x are extracted.

Further, the sign of the quotient set to $ x is taken out and set to $ sign (step C11). Since the bit position of S is the x_BIT + 1 bit from the lower order, $ x and 2 ^x_BIT
The bit representing the sign of the quotient can be taken out.

  Finally, when the sign of the quotient $ sign is not 0 (the quotient is negative) (step C12; No), the sign of the variable ret is inverted (step C13). If $ sign is 0 (the quotient is positive) (step C12; Yes), the sign of the quotient ret is not inverted. In the example of FIG. 6, since $ sign is 1, the sign of the ret is inverted to 11111011 (decimal number −5).

  As described above, when the number of effective bits of the dividend is taken into consideration, the number of repetitions of subtraction processing obtained by dividing division into strokes can be reduced to the number of effective bits. When the number of effective bits is not considered, for example, when the dividend and the divisor are 8 bits, it is necessary to shift the divisor by 8 bits and repeat the maximum of 7 subtraction processes (since the most significant bit represents a sign, The maximum valid bit is 7).

  In the example of FIG. 6, for easy understanding, the dividend and the divisor are 8 bits. However, for example, when the dividend is 16 bits or 32 bits, the maximum number of subtractions is 17 or 31, The difference in the number of subtraction repetitions from when the number of effective bits is taken into consideration is large, and the difference between the circuit scale for performing the operation and the processing time is large.

  FIG. 7 shows an example of the data flow graph 38 when the processing represented by the flowchart of FIG. 5 is applied to the example of FIG. In FIG. 7, inputs P, P1, and P2 represent the dividend x. Inputs Q, Q1, and Q2 represent the divisor y. The output R represents the division quotient ret. Constants in the middle of processing, temporary storage, and the like are also indicated by numbers with the same D as the calculation. In the following, steps including constants are called steps.

  Steps D1 to D11 in FIG. 7 represent processing for determining the sign of the quotient ($ sign in FIG. 5). Either 1 (step D5) or -1 (steps D1 and D2) is selected (step D6) according to the result of the sign determination (steps D3 and D4) of the input P2 (dividend x). Then, the result of step D6 (step D8) or its sign inversion (step D7) is selected (step D11) according to the result of the sign determination (steps D9 and D10) of the input Q2 (divisor y). The result of step D11 is 1 if the inputs P2 and Q2 have the same sign, and -1 if the inputs P2 and Q2 have different signs (or any one is 0).

  Steps D12 to D14 are processes for making the dividend positive. Depending on the result (step D12) of the sign determination (steps D3 and D4) of the input P2, the input P or the sign inversion of the input P1 (step D13) is selected (step D14).

  Steps D15 and D16 (and D10) are processes for making the divisor positive. Depending on the result of the sign determination (step D10) of the input Q2, the input Q or the sign inversion of the input Q1 (step D15) is selected (step D16).

Steps D17 to D23 are processes for shifting the dividend to the left by one bit and setting the sign of the quotient in the least significant bit. The dividend converted to a positive number is shifted to the left by 1 bit (step D1
7). When $ sign is 1 (steps D18 and D19; true), the number is selected (step D23; T). When $ sign is −1 (step D19; false), the number (step D21) in which 1 is added to the result of step D17 (the least significant bit is set to 1) is selected (step D23). Here, the sign represented by S in FIG. 6 is set to 0 when the quotient is positive and to 1 when the quotient is negative.

  In the meantime, the divisor is shifted to the left by the effective bit number of the dividend + 1 bit (steps D24 and D25). In the example of FIG. 3, since the effective number of bits of the dividend is 5, it is shifted to the left by 6 bits. In FIG. 7, the shift is performed in two steps, that is, a 4-bit left shift (step D24) and a 2-bit left shift (step D25). This is due to the characteristic of the logic circuit that the number of shift bits is a power of two.

  Then, the process of div_x is repeatedly executed for the number of effective bits of the dividend (steps D26 to D35). The result of step D25 is temporarily output to B (step D28) and used as input B (step D35) of step D34. However, a configuration in which another mov operation is added below step D32 may be used, and the result of division is the same. is there.

  A quotient portion is extracted from the result of the last div_x (step D34) (steps D36 and D37). In this example, since the number of effective bits is 5, the logical product for each bit of 25-1 = 31 is calculated. Meanwhile, a bit representing the sign of the quotient (S in FIG. 6) is extracted from the calculation result (steps D38 and D39). If the bit representing the sign of the quotient is 0 (the quotient is positive) (step D42; true), the result of step D37 is selected as it is (step D41) (step D44; T). If the bit representing the sign of the quotient is 1 (the quotient is negative) (step D42; false), the value obtained by inverting the sign of the result of step D37 (step D40) is selected.

  As described above, the effective bit number of the dividend described in the source program 36 is determined, the effective bit number is reflected in the subtraction repetition number, and the data flow graph 38 in which the div_x repetition number is reduced is generated. Can do. By mapping the operation to the reconfigurable circuit 1 using the data flow graph 38 reflecting the number of effective bits, the scale of the reconfigurable circuit 1 used for the operation is reduced and the processing speed is simultaneously improved. In addition, power consumption can be reduced.

  Furthermore, a case where the dividend and the sign of the divisor are determined and reflected in the data flow graph 38 will be described. FIG. 8 is a flowchart in which division processing is developed in consideration of the dividend in division, the number of effective bits of the divisor, and the sign. Compared with the flowchart of FIG. 5, the processes of dividend and divisor sign determination, conversion to positive numbers, quotient sign setting and sign determination are omitted. The flowchart of FIG. 8 is based on the source program 36 of FIG. In the flowchart of FIG. 8, the dividend is a positive number and the number of effective bits is 5, and the divisor is a negative number and the number of effective bits is 6.

  In the example of the source program 36 in FIG. 3, the compiling unit 30 determines that the dividend is a positive number and the effective number of bits is 5 and the divisor is a negative number and the effective number of bits is 6 from the description in the comment field on the first line. it can. Therefore, as shown in the flowchart of FIG. 8, x is shifted to the left by 1 bit from the beginning, and a value obtained by adding 1 is substituted into $ x, and y is inverted, and the effective number of dividends + 1 bits to the left The shifted value can be substituted for $ y (step E1).

According to the method of the present embodiment, since the dividend and the sign of the divisor are specified, it is possible to omit the process of extracting the quotient code from the result of div_x and the process of determining the quotient sign. As a result, the flowchart of FIG. 8 does not have processing corresponding to the latter half of step C11 and step C12 of FIG. Steps E2 to E4 in FIG. 8 are the same as steps C8 to C10 in FIG.
Further, step E5 in FIG. 8 is the same as the first half of step C11 in FIG. 5, and step E6 is the same as step C13 in FIG.

  FIG. 9 shows an example of a data flow graph (DFG) 38 when the process represented by the flowchart of FIG. 8 is applied to the example of FIG. Compared to the DFG 38 in FIG. 7, the DFG 38 in FIG. 9 omits dividend and divisor sign determination, quotient code setting, and quotient sign determination processing.

  The dividend x is shifted to the left by 1 bit (step F1), and 1 is added as a bit representing the sign of the quotient (steps F2 and F3). The divisor y is sign-inverted (step F4) and shifted to the left by the effective bit number of the dividend + 1 bit (6 bits) (step F5).

  Steps F6 to F15 are the same as steps D26 to D35 in FIG. The part which becomes the quotient is taken out from the result of the last div_x (step F14) (steps F16 and F17). In this example, since the number of effective bits is 5, the logical product for each bit of 25-1 = 31 is calculated. Since it is known that the quotient is negative, the result of step F17 is inverted (step F18) to obtain a quotient ret for division.

  As described above, the dividend and the sign of the divisor are determined from the description of the source program 36 and reflected in the data flow graph 38, whereby the scale of the logic circuit can be further reduced and the processing time can be shortened. Power consumption can also be reduced.

(Embodiment 2)
In the second embodiment, an arithmetic mapping method to the reconfigurable circuit 1 of the present invention will be described by taking a remainder calculation as an example. FIG. 10 is a diagram illustrating an example of a remainder source program 36 as an example of the mapping method according to the second embodiment.

  There is also a method of realizing the remainder calculation by dividing the remainder calculation into the calculation method of the handwriting calculation and having only a simple instruction in one logic circuit. In addition, a method of assigning a certain pattern of computation to one computing means using the regularity of division by the calculation method of writing can be considered.

  FIG. 11 is an example of a data graph representing a single-stage subtraction process when the remainder calculation is decomposed into a calculation method of writing composed of multi-stage subtraction. In FIG. 11A, a variable x represented by an input P is a dividend, and a variable y represented by an input Q is a divisor. Variables x and y are integers in binary notation and are expressed in two's complement. The condition is that the variables x and y are positive numbers. The variable ret represented by the output R is a processing result of one subtraction stage, and stores a number (remainder at this stage) that becomes a dividend of the next subtraction stage.

  The subtraction stage constituting the remainder calculation is performed as follows. First, the dividend x is input to three logic circuits of steps G3, G4, and G5 (step G1). The divisor y is input to the two logic circuits of steps G4 and G5 (step G2). In step G3, the input is held as it is and used as the input in step G6. In step G4, the divisor y is subtracted from the dividend x. In step G5, the dividend x is compared with the divisor y. The result of step G5 is true if the dividend x is greater than the divisor y, and false if the dividend x is less than or equal to the divisor y. The broken line at the output of step G5 indicates that the value is a truth value.

In Step G6, either the output of Step G3 (dividend x) or the output of Step G4 (the result of subtracting the divisor y from the dividend x) is selected as the output R according to the determination result of Step G5. “Merge” in step G6 represents a logical operation for selecting one of the two solid line inputs in accordance with the truth of the broken line input. When the broken line input is true, the input indicated by T is selected from the solid line inputs.

  In the one-stage subtraction process constituting the remainder calculation, if the dividend x is larger than the divisor y, the divisor y is subtracted from the dividend x. If the dividend x is less than or equal to the divisor y, the dividend x is output as it is. The divisor y is shifted one bit to the right before entering the next subtraction stage (not shown in FIG. 11).

  FIG. 11B shows that the processes of FIG. 11A are collectively expressed as mod_y (step H1). mod_y represents the decomposition into steps G1 to G6 in FIG.

  Returning to FIG. 10, the first line of the source program 36 is a comment field. The second line indicates that the remainder obtained by dividing the dividend x by the divisor y is substituted into the variable ret. The comment on the first line indicates that in the remainder calculation on the second line, the dividend is positive and the number of effective bits is 5, the divisor is negative and the number of effective bits is 6.

  FIG. 10 is an example showing the dividend, the effective number of bits of the divisor, and the sign in the remainder calculation. In the source program 36, how the dividend and the effective bit number and sign of the divisor are expressed is arbitrary. For example, the effective bit number and sign of a variable can be expressed by adding / and a signed integer after the variable of the variable type declaration statement.

  For example, the compiling unit 30 of the processing device 10 reads information described in the comment column of the source program 36 illustrated in FIG. 10 and determines the dividend and the effective bit number and sign of the divisor in the remainder calculation. Then, a data flow graph (DFG) 38 corresponding to the dividend, the number of effective bits of the divisor, and the sign is generated.

  FIG. 12 is a flowchart in which the remainder calculation process is developed in consideration of the number of effective bits of the dividend in the remainder calculation. In FIG. 12, x_BIT represents the number of effective bits of the dividend x. Each variable in the flowchart of FIG. 5 corresponds to the source program 36 of FIG. FIG. 13 shows an example of the contents of variables in the flowchart of FIG. In FIG. 13, the dividend is 29 and the divisor is −5 as an example. The steps in FIG. 13 correspond to the steps in FIG. 12 (J1 etc.). Also, the numbers other than the numbers with d indicating decimal numbers are binary numbers. In FIG. 13, the dividend x and the divisor y are 8 bits. The internal variables $ x and $ y are 16 bits, but the upper bits are omitted in FIG. In the example of FIG. 13, the absolute value of the divisor is small and the effective bit number of the dividend is 5, and even if the divisor is bit-shifted to the left, it remains within 8 bits. However, in general, when the divisor is 8 bits, A variable requires a maximum of 15 bits.

  The value of the divisor y is substituted into the double precision variable $ y (step J1). The sign of the divisor y is determined (step J2). If the divisor y is not positive (step J2; No), the variable $ y is set to -y (step J3). If the divisor y is positive (step J2; Yes), the variable $ y remains y. In the example of FIG. 13, the decimal number -5 is substituted into the variable $ y (step J1), and since the variable y is negative, the sign is inverted to become the decimal number 5 (step J3). In FIG. 13, in order to represent the dividend x, the decimal number 29 is written as the variable $ x in the line of Step J1.

The dividend x is shifted to the left by 1 bit and assigned to the double precision variable $ x (step J4). As in the case of division, the least significant bit of $ x represents the sign of the remainder. The sign of the remainder is the same as the sign of the dividend except when the remainder is 0 (ie, divisible). The sign of variable $ x is determined (step J5). If variable $ x is not positive (step J5; No), the sign of $ x is inverted and 1 is added to $ x (step J6). That is, the least significant bit is set to 1 to indicate that the dividend is positive and the sign of the remainder is negative. If the variable $ x is positive (step J5; Yes), $ x remains the value obtained by shifting the dividend to the left by 1 bit, and the least significant bit is 0. In FIG. 13, since the dividend x is positive, no sign inversion is performed. Further, the least significant bit of $ x is described as S in order to make the dividend range easy to see. In this case, S is 0.

In order to match the digit with the variable $ x, the variable $ y is shifted to the left of the effective bit number (x_BIT) of the dividend x (step J7). In the example of FIG. 13, since the number of effective bits of the dividend is 5, $
y is shifted left by 5 bits (step J7).

  Next, step J9 is repeated by the effective bit number -1 of the dividend x (steps J8, J9, J10). Step J9 performs the mod_y process shown in FIG. 11 with $ x as the dividend and $ y as the divisor, and then shifts $ y to the right by 1 bit.

  In the example of FIG. 13, the mod_y process is repeated four times. Steps J8, J9, and J10 (1) to (4) in FIG. 13 show the result of $ x in each processing of step J9. The upper part of each column shows mod_y inputs $ x and $ y. The lower part of each column shows the result when the divisor $ y is subtracted from the dividend $ x. The blank in the lower row of $ x indicates that the result of subtracting $ y from $ x is not positive. In that case, the value of $ x is passed to the next processing as it is. The result of shifting $ y to the right by 1 bit is shown in the lower part.

  In the first and second mod_y (step J9), since $ x is smaller than $ y, $ x is passed to the next processing as it is. In the third time, $ x becomes larger than $ y, and the value obtained by subtracting $ y is passed to the next processing. In the fourth time, $ x is smaller than $ y, and $ x remains as it is.

  Further, mod_y is processed once again, and a value obtained by shifting $ x to the right by 1 bit is set as a variable ret (step J11). Further, the least significant bit of the variable $ x is extracted and set as a variable $ sign (step J11).

  In the example of FIG. 13, in step J11 (the fifth mod_y), $ x is greater than $ y, and the value obtained by subtracting $ y is $ x. As a result of repeating mod_y five times, the upper bit (left of S) of the remainder code of $ x is 0000100 (decimal number 4), which is a remainder (29 / (− 5) = − 5 remainder 4) . ret is a value 00000100 (decimal number 4) obtained by shifting the result of $ x to the right by 1 bit. Also, $ sign is 0.

  Finally, when the remainder sign $ sign is not 0 (the remainder is negative) (step J12; No), the sign of the variable ret is inverted (step J13). When $ sign is 0 (the remainder is positive) (step J12; Yes), the sign of the variable ret is not reversed. In the example of FIG. 6, since $ sign is 0, ret is not inverted in sign.

  As described above, when the number of effective bits of the dividend is taken into consideration, the number of repetitions of subtraction processing obtained by dividing the remainder calculation into handwriting can be reduced to the number of effective bits. If the effective number of bits is not taken into consideration, if the dividend and the divisor are 8 bits, the divisor needs to be shifted by 7 bits and the maximum 7 subtractions must be repeated (the most significant bit represents the sign, so the maximum The valid bit is 7).

  In the example of FIG. 13, for easy understanding, the dividend and the divisor are 8 bits. For example, when the dividend is 16 bits or 32 bits, the maximum number of subtractions is 17 or 31, The difference in the number of subtraction repetitions from when the number of effective bits is taken into consideration is large, and the difference between the circuit scale for performing the operation and the processing time is large.

  FIG. 14 shows an example of the data flow graph 38 when the processing represented by the flowchart of FIG. 12 is applied to the example of FIG. In FIG. 14, the input P represents the dividend x. Inputs Q, Q1, and Q2 represent the divisor y. The output R represents the remainder ret of the division. Constants in the middle of processing, temporary storage, and the like are also indicated by the numbers with the same K as the calculation. In the following, steps including constants are called steps.

  Steps K1 to K3 in FIG. 14 are processes for making the divisor positive. Depending on the result of the sign determination (step K2) of the input Q2, the input Q or the sign inversion (step K1) of the input Q1 is selected (step K3).

  Steps K4 to K12 represent processing for determining the sign of the remainder with the dividend being positive. The input P (dividend x) is shifted one bit to the left (step K4) and input to steps K5 and K6. In step K5, the sign is inverted and 1 is added (steps K7 and K9). In step K6, the value is held and input to steps K10 and K11. Step K10 holds the value. Step K11 determines the sign of the dividend. A value obtained by shifting the input P to the left by 1 bit (steps K4, K6, K10) or a value obtained by inverting the sign and adding 1 (steps K5, K9) according to the result of the sign determination (steps K8, K11) Is selected (step K12). The result of step K12 is that when the input P is positive, the value is shifted to the left by 1 bit and the least significant bit is 0. When the input P is not positive, it is shifted to the left by 1 bit and the sign is inverted. It becomes the value made.

  Meanwhile, the divisor is shifted to the left by the number of effective bits of the dividend (steps K13 and K14). In the example of FIG. 10, since the effective bit number of the dividend is 5, the shift is performed to the left by 5 bits. In FIG. 14, the shift is performed in two steps, that is, a 4-bit left shift (step K13) and a 1-bit left shift (step K14). This is due to the characteristic of the logic circuit that the number of shift bits is a power of two.

  Then, the process of mod_y and the process of shifting the divisor to the right by 1 bit are repeated by the effective bit number-1 of the dividend (steps K15 to K22). Further, mod_y is processed once (step K23).

  A surplus part is extracted from the result of the last mod_y (step K23) (steps K25 to K31). The result of step K23 is shifted to the right by 1 bit (step K26), its value (step K29), and a value obtained by inverting the sign of that value (step K30) are prepared. In the meantime, the least significant bit of the result of step K23 is extracted (step K25), and it is determined whether or not the value is 0 (step K27). If the result of step K27 is true (the remainder is positive), the output of step K29 is selected. If the result of step K27 is false (the remainder is negative), the output of step K30 is selected and the remainder ret ( Output R) (step K31).

  As described above, the effective bit number of the dividend described in the source program 36 is determined, the effective bit number is reflected in the repetition number of subtraction, and the data flow graph 38 in which the repetition number of mod_y is reduced is generated. Can do. By mapping the operation to the reconfigurable circuit 1 using the data flow graph 38 reflecting the number of effective bits, the scale of the reconfigurable circuit 1 used for the operation is reduced and the processing speed is simultaneously improved. In addition, power consumption can be reduced.

Furthermore, a case where the dividend and the sign of the divisor are determined and reflected in the data flow graph 38 will be described. FIG. 15 is a flowchart in which the remainder calculation process is developed in consideration of the dividend in the remainder calculation, the effective number of bits of the divisor, and the sign. Compared with the flowchart of FIG. 12, the determination of the dividend and the sign of the divisor, the conversion to the respective positive numbers, and the sign setting of the remainder and the sign determination are omitted. The flowchart of FIG. 15 is based on the source program 36 of FIG. In the flowchart of FIG. 15, the dividend is a positive number and the number of effective bits is 5, and the divisor is a negative number and the number of effective bits is 6.

  In the example of the source program 36 in FIG. 10, the compiling unit 30 determines that the dividend is a positive number and the effective number of bits is 5, and the divisor is a negative number and the effective number of bits is 6, from the description in the comment field on the first line. it can. Therefore, as shown in the flowchart of FIG. 15, the divisor y is inverted from the beginning and substituted into $ y (step L1), and the value obtained by shifting the dividend x to the left by 1 bit is substituted into $ x (step L2). . The sign determination of $ x and the sign inversion process (steps J5 and J6 in FIG. 12) are omitted. From the process of shifting $ y to the left by the effective bit number of the dividend, the process of repeating mod_y and 1-bit right shift of $ y (steps L3 to L6) is the same as steps J7 to J10 of FIG.

  In the example of FIG. 10, since it is known that the remainder is positive, the process of mod_y is performed once again, and the result is shifted to the right by 1 bit to obtain the remainder ret (step L7).

  According to the method of the present embodiment, since the dividend and the sign of the divisor are specified, it is possible to omit the process of extracting the remainder code from the result of mod_y and the process of determining the remainder code. As a result, the flowchart of FIG. 15 does not have processing corresponding to step J13 from the third line of step J11 of FIG.

  FIG. 16 shows an example of a data flow graph (DFG) 38 when the process represented by the flowchart of FIG. 15 is applied to the example of FIG. Compared to the DFG 38 in FIG. 14, the DFG 38 in FIG. 16 omits dividend and divisor sign determination, remainder code setting, and remainder sign determination processing.

  Since the divisor y is a negative number, the sign is inverted (step M1) and shifted to the left by the effective number of bits (5 bits) of the dividend (step M2). The dividend x is shifted to the left by 1 bit (step M3). Since the dividend x is a positive number and the bit representing the remainder sign is 0, it is directly input to the mod_y process (step M5). When the dividend x is a negative number, a sign inversion and a process of adding 1 are added after shifting by 1 bit to the left.

  Steps M4 to M12 are the same as steps K15 to K23 in FIG. The result of the last mod_y (step M12) is shifted to the right by 1 bit (step M13) to obtain a remainder ret of division. In this example, steps K24, K25 and K27 to K31 in FIG. 14 are not necessary. When the sign of the remainder is negative, the sign inversion process of the remainder is added.

  As described above, the dividend and the sign of the divisor are determined from the description of the source program 36 and reflected in the data flow graph 38, whereby the scale of the logic circuit can be further reduced and the processing time can be shortened. Power consumption can also be reduced.

  Although the operation mapping method of the present invention has been described by taking division as an example in the first embodiment and remainder calculation as an example in the second embodiment, the operation mapping method of the present invention is not limited to division or remainder calculation, and the number of operations This can be applied to an operation that can reduce the data flow mapped to the reconfigurable circuit 1 by using the effective bit number or sign. For example, it is possible to reduce the number of repetitions of addition processing, which is a decomposition of multiplication into strokes, to the number of effective bits. Also, with regard to multiplication, it is possible to reduce code determination and code inversion processing.

In the above example, the integer type variable has been described. However, also for the floating point type variable, the effective bit number or sign of the mantissa part is determined from the description of the source program 36, and the reconfigurable circuit is based on the determination. The arithmetic processing mapped to 1 can be reduced.

  In the above example, the case of determining the number of input effective bits, or the number of effective bits and the sign has been described. However, only the input code is determined, and processing such as code determination and sign inversion of arithmetic processing is reduced. The data flow graph 38 may be generated.

  In addition, the hardware configuration and the flowchart described above are merely examples, and can be arbitrarily changed and modified.

It is a block diagram which shows the structure of a processing apparatus provided with the reconfigurable circuit which concerns on embodiment of this invention. It is a block diagram which shows the example of a structure of the reconfigurable circuit which concerns on embodiment of this invention. It is a figure which shows an example of the source program of the division used for description of the operation mapping method of this invention. It is an example of the data graph showing the process of one step of subtraction when division is decomposed | disassembled into the calculation method of the pen calculation comprised by multistage subtraction. It is the flowchart which expanded the process of the division in consideration of the effective bit number of the dividend in the division. It is a figure which shows the example of the content of the variable in the flowchart of FIG. FIG. 6 is a diagram illustrating an example of a data flow graph when the process represented by the flowchart of FIG. 5 is applied to the example of FIG. 3. It is the flowchart which expanded the process of the division in consideration of the dividend in the division, the effective bit number of the divisor, and the sign. It is a figure which shows the example of a data flow graph at the time of applying the process represented by the flowchart of FIG. 8 to the example of FIG. It is a figure which shows an example of the source program of the remainder calculation used for description of the operation mapping method of this invention. It is an example of the data graph showing the process of subtraction one step when decomposing remainder calculation into the calculation method of the pen calculation comprised by multistage subtraction. It is the flowchart which expanded the process of remainder calculation in consideration of the number of effective bits of the dividend in remainder calculation. It is a figure which shows the example of the content of the variable in the flowchart of FIG. It is a figure which shows the example of a data flow graph at the time of applying the process represented by the flowchart of FIG. 12 to the example of FIG. It is the flowchart which expanded the process of the remainder calculation in consideration of the dividend in the remainder calculation, the effective bit number of the divisor, and the sign. It is a figure which shows the example of a data flow graph at the time of applying the process represented by the flowchart of FIG. 15 to the example of FIG.

Explanation of symbols

1 Reconfigurable circuit
2 logic circuit
3 connections
10 Processing device
30 Compilation section
32 Setting data generator
34 Memory
36 Source program
38 Data flow graph
40 Setting data

Claims (10)

A reconfigurable circuit comprising: an arithmetic unit composed of a plurality of logic circuits each capable of selectively executing a plurality of arithmetic logic operation functions; and a connection unit for maintaining a connection relationship between the plurality of logic circuits. In addition, there is an operation mapping method for mapping an intended operation function,
An effective bit number determination step for determining the effective bit number of the input of the intended arithmetic function based on the bit number designation means for designating the effective bit number of the input of the intended arithmetic function;
A mapping step of mapping the intended arithmetic function to the reconfigurable circuit based on the effective bit number determined in the effective bit number determining step;
An operation mapping method comprising: A reconfigurable circuit comprising: an arithmetic unit composed of a plurality of logic circuits each capable of selectively executing a plurality of arithmetic logic operation functions; and a connection unit for maintaining a connection relationship between the plurality of logic circuits. In addition, there is an operation mapping method for mapping an intended operation function,
A sign determination step for determining a sign of an input of the expected arithmetic function based on a sign specifying means for specifying a sign of the input of the expected arithmetic function;
A mapping step for mapping the intended arithmetic function to the reconfigurable circuit based on the code determined in the code determination step;
An operation mapping method comprising: The intended calculation function includes division or remainder calculation,
The mapping step maps the division or remainder calculation to a process including repetition of subtraction for the effective bit number of the dividend of the division or remainder calculation.
The operation mapping method according to claim 1, wherein:   The number-of-bits designating means for designating a valid number of input bits of the intended arithmetic function is a source program expressing the intended arithmetic function in a programming language. Operation mapping method.   5. The operation mapping method according to claim 4, wherein the effective bit number determination step determines an effective bit number of an input based on a description of a comment of the source program.   3. The operation mapping method according to claim 2, wherein the code designating means for designating an input code of the desired operation function is a source program expressing the desired operation function in a program language.   The operation mapping method according to claim 6, wherein the code determination step determines an input code based on a comment description of the source program.   A reconfigurable circuit which operates according to data obtained from the result of the operation mapping method according to claim 1. A reconfigurable circuit comprising: an arithmetic unit composed of a plurality of logic circuits each capable of selectively executing a plurality of arithmetic logic operation functions; and a connection unit for maintaining a connection relationship between the plurality of logic circuits. In addition, a data flow graph necessary for setting the operation of the expected calculation function,
When the desired calculation function is decomposed into repetitive calculations according to the number of input bits of the calculation, the predetermined calculation function is determined based on a source program expressing the calculation function in a programming language. A data flow graph, wherein the number of repetitions of the repetitive operation is reduced in correspondence with the number of valid bits of the input of the operation function of the period. A reconfigurable circuit comprising: an arithmetic unit composed of a plurality of logic circuits each capable of selectively executing a plurality of arithmetic logic operation functions; and a connection unit for maintaining a connection relationship between the plurality of logic circuits. In addition, a data flow graph necessary for setting the operation of the expected calculation function,
When the expected calculation function includes the input sign determination process so that the input sign of the expected calculation function is processed corresponding to either positive or negative, the expected calculation function A data flow graph in which the code determination process is omitted corresponding to a code of an input of the intended arithmetic function, which is determined based on a source program expressed in a program language.

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