JP3702475B2 - Automatic circuit generator - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to an automatic circuit generation device that is preferably used as a circuit design device used in LSI development, for example.
[0002]
[Prior art]
Circuit design using CAD devices is rapidly spreading. In particular, circuit design and circuit input of LSI logic circuits as application-specific ICs (ASICs) such as gate arrays can be converted directly into netlists and layout data, enabling efficient simulation and layout. Therefore, it is usually performed using a CAD apparatus.
In circuit design using a CAD apparatus, a designer first reads out a desired arithmetic element from a library prepared in advance and sequentially arranges it at an arbitrary position on a circuit diagram displayed on the screen. Then, circuit input is performed by sequentially connecting the input / output terminals of these arithmetic elements using a mouse or the like. The library stores basic arithmetic elements such as inverters, AND, OR, NAND, and NOR, and functional arithmetic elements such as adders, counters, comparators, and multiplexers. In addition, arithmetic circuits that can be configured with higher speed or lower power consumption, which are configured by combining basic arithmetic elements by the designer, are also stored as one module.
[0003]
In such a designed circuit, the bit length of processing data handled by a circuit configured on a normal substrate often takes a power of 2 such as 8 bits, 16 bits, 32 bits. However, a circuit inside an LSI is often designed with a bit length necessary and sufficient for data to be handled due to restrictions such as the number of gates and power consumption. For example, data such as 9 bits and 17 bits considering the carry, and processing with bit lengths of 15 bits and 31 bits due to the limitation of the maximum value are frequently performed.
In many cases, the bit length is determined by a method in which a circuit in which the bit length is actually changed is input, simulation is performed, the characteristics of the circuit are evaluated, and the bit length is finally determined.
For this reason, especially when designing the circuit inside the LSI, changes to increase or decrease the bit length of the processing data are frequently made.
[0004]
[Problems to be solved by the invention]
However, there is a problem that even if circuit design is performed using a CAD device, it takes a very long time because the actual input operation is a repeated manual operation. In particular, changing the bit length of the data to be processed as described above, which is frequently performed when designing a circuit inside an LSI, often takes time and wastes time, and hinders improvement in the efficiency of circuit design. It was.
Further, when a circuit is configured using a module that processes data of a plurality of bit lengths, for example, changing the bit length of 1-bit data is not limited to correcting the circuit corresponding to the 1-bit data, In many cases, the entire processing unit must be reviewed. In such a case, the circuit must be significantly modified, and the circuit design efficiency has been greatly reduced.
[0005]
Accordingly, it is an object of the present invention to provide an automatic circuit generation device that can automatically generate a circuit for processing data having a desired bit length, and thus can easily redesign a circuit in accordance with a change in bit length. There is to do. It is another object of the present invention to provide a CAD device that can greatly reduce the design time by making it possible to easily redesign a circuit accompanying a change in bit length.
[0006]
[Means for Solving the Problems]
The change of the bit length of the processing data is originally a simple and regular change. Therefore, for example, if processing circuits for 1 bit are stored so that they can be connected to each other, circuits connected in series or in parallel to some degree should be able to be generated regularly.
Therefore, an automatic circuit generation device has been invented that automatically generates a circuit capable of processing data of an arbitrary bit length by storing such circuit module data and inputting the bit length from the outside. Also, circuit differences based on bit positions and regular differences can be dealt with by storing a plurality of modules and selecting and connecting them appropriately. Furthermore, a module that processes data of a plurality of bits such as 2 bits or 4 bits is used, and a circuit that processes data of a desired bit length can be generated by combining them.
[0007]
  BookThe circuit automatic generation device of the inventionA device for automatically generating a carry-look-ahead circuit,Circuit module storage means for storing circuit information of a plurality of types of circuit modules having different bit lengths of processing data and connection information between the circuit modules, bit length of input processing data, and maximum bit length of the circuit module Based on the result of the calculation, the circuit modules having different bit lengths can be combined into a bit length of the input processing data so as to be more suitable than the plurality of types of circuit modules stored in the circuit module storage means. Circuit module selection means for sequentially selecting a plurality of types of circuit modules stored in the circuit module storage means for sequentially selecting modules, and the circuit module selected by the circuit module selection means as the connection information of the circuit modules Circuit connection means for sequentially connecting based on the circuit connection means, and the circuit connection means Yes and output means for outputting information indicating a more connected circuitryThe circuit module storage means includes a first circuit module that is a 1-bit carry-look-ahead circuit that outputs a carry to the upper order based on two 1-bit inputs and a carry input from the lower order, Each information of the second circuit module in which an output buffer is further added to the first circuit module is stored, and the circuit module selection means is configured to reduce the first length of the first processing module by one less than the bit length of the input processing data. Are successively selected, and one of the second circuit modules is further selected..
[0014]
【Example】
First embodiment
An automatic circuit generation device according to a first embodiment of the present invention will be described with reference to FIGS.
First, the configuration of the automatic circuit generation device of the first embodiment will be described with reference to FIG.
FIG. 1 is a block diagram showing the configuration of the automatic circuit generation device of the first embodiment.
The automatic circuit generation device 10 includes an input unit 11, a bit length storage unit 12, a module selection unit 13, a basic module a generation unit 14, a basic module b generation unit 15, a generation circuit storage unit 16, a subtraction unit 17, and an output unit. 18 is comprised.
The circuit automatic generation device 10 of this embodiment is incorporated in a CAD device used when designing a logic circuit or the like.
[0015]
Hereinafter, the operation of each unit will be described.
The input unit 11 is an input device such as a keyboard, and a bit length B, which is a data width of a circuit, is input from the input unit 11 by an operator. The input bit length B is stored in the bit length storage unit 12 as a parameter N for selecting a module. Since this bit length B is the bit width of data, an integer of 2 or more is usually input.
The bit length storage unit 12 is a data storage circuit configured by a memory, and is used to select a module based on the bit length B input from the input unit 11 and a parameter Nnew updated by a subtraction unit 17 described later. Store as parameter N. The parameter N stored in the bit length storage unit 12 can be read out by the module selection unit 13 and the subtraction unit 17.
[0016]
The module selection unit 13 is a selection unit that selects a basic module based on the parameter N stored in the bit length storage unit 12. When the parameter N is 2 or more, the module selection unit 13 applies a selection signal S1 indicating that to the basic module a generation unit 14 and the subtraction unit 17 via a predetermined selection line. When the parameter N is 1, a selection signal S2 indicating that is applied to the basic module b generation unit 15 and the output unit 18 via a predetermined selection line.
[0017]
When the selection signal S <b> 1 is applied from the module selection unit 13, the basic module a generation unit 14 generates the basic module a stored in the basic module a generation unit 14 as actual circuit information, and generates the generation circuit storage unit 16. Output to. The basic module a generation unit 14 stores arithmetic elements constituting the basic module a and their connection information, connection information with other elements, and circuit characteristic information such as element delay. Therefore, the basic module generation unit 14 reads out the information and adds identification information such as a signal name, thereby generating actual circuit information that can be connected to other elements and arranged in a circuit drawing or the like.
When the selection signal S <b> 2 is applied from the module selection unit 13, the basic module b generation unit 15 generates the basic module b stored in the basic module b generation unit 15 as actual circuit information, and generates the generation circuit storage unit 16. Output to. Generation of the stored information and real circuit information is the same as that of the basic module a generation unit 14 described above.
[0018]
The generation circuit storage unit 16 is a storage unit that stores the basic modules sequentially generated by the basic module a generation unit 14 and the basic module b generation unit 15 by sequentially connecting them in the input order. This connection method information is described in the information of each basic module stored in the basic module a generation unit 14 and the basic module b generation unit 15 in advance.
When the selection signal S1 is applied from the module selection unit 13, the subtraction unit 17 subtracts 1 from the bit length parameter N stored in the bit length storage unit 12, and sets the new parameter Nnew of the subtraction result to the bit length. Input to the storage unit 12. That is, every time the basic module a is selected as the generation module by the module selection unit 13, 1 is subtracted from the bit length parameter N stored in the bit length storage unit 12 and the modules are sequentially updated.
[0019]
When the selection signal S2 is applied from the module selection unit 13, the output unit 18 has been generated by the basic module a generation unit 14 and the basic module b generation unit 15 and is sequentially connected and stored by the generation circuit storage unit 16. Read out the circuit information. The output information is arranged at a designated position on the circuit drawing, and is displayed on an output device such as a display in a state that can be viewed by an operator.
[0020]
Next, the operation of automatic circuit generation by the circuit generation device 10 will be specifically described with reference to FIGS.
In this embodiment, the automatic circuit generation device 10 generates a CLA circuit having a desired number of bits for a carry look ahead circuit (carry look ahead signal, hereinafter referred to as a CLA circuit) frequently used in an adder or the like. This is an automatic circuit generation device.
FIG. 2 is a diagram illustrating basic modules stored in the basic module a generation unit 14 and the basic module b generation unit 15, and FIG. 2A illustrates a basic module a corresponding to a 1-bit logic circuit of the CLA circuit. FIG. 2B is a diagram showing a basic module b having a configuration in which an output buffer is added to a 1-bit logic circuit of a CLA circuit.
[0021]
FIG. 3 is a diagram illustrating a circuit generated by the automatic circuit generation device 10 and is a 4-bit CLA circuit. As shown in FIG. 3, the 4-bit CLA circuit has a 4-bit carry check circuit connected in series, and an output buffer is added to the output section of the final circuit. . Therefore, in the basic module shown in FIG. 2, three basic modules a shown in FIG. 2A and one basic module b shown in FIG. 2B are sequentially connected. .
[0022]
The operation of the automatic circuit generation device 10 when generating a 4-bit CLA circuit will be described below.
First, 4 is input as an input value having a bit length from the input unit 11, and stored as a parameter N in the bit length storage unit 12. In the module selection unit 13, the parameter N is referred to and the selection signal S1 is selected because N ≠ 1. As a result, the basic module a is selected, and the circuit shown in FIG. 2A generated by the basic module a generation unit 14 is stored in the generation circuit storage unit 16. On the other hand, in the subtraction unit 17 to which the selection signal S1 is applied, 1 is subtracted from the parameter N stored in the bit length storage unit 12, and is set in the bit length storage unit 12 as a new parameter Nnew.
[0023]
Thereafter, the circuit generation process is repeated based on the updated parameters. When the basic module is selected for the second time, the parameter N is 3 and N ≠ 1, so the basic module a is generated again as in the case of the first time. Further, since N = 2 at the time of the third circuit generation, the basic module a is generated in the same manner. The three generated basic modules a are sequentially connected and stored in the generation circuit storage unit 16.
[0024]
After generating the three basic modules a, the parameter N stored in the bit length storage unit 12 is 1. Therefore, when the circuit is generated for the fourth time, the parameter N = 1, so the module selection unit 13 selects the selection signal S2. As a result, the basic module b is selected, and the circuit shown in FIG. 2B generated by the basic module b generation unit 15 is input to the generation circuit storage unit 16 and connected to and stored in the previous circuit. . As a result, a 4-bit CLA circuit as shown in FIG. The selection signal S2 is simultaneously applied to the output unit 18, and the output unit 18 reads out and outputs the CLA circuit from the generation circuit storage unit 16.
[0025]
The automatic circuit generation device 10 can also be realized by a CAD tool or the like mounted on a workstation or the like. A process when the circuit automatic generation device 10 of the first embodiment is applied to such a computer device will be described with reference to FIG.
FIG. 4 is a diagram showing a flowchart when the automatic circuit generation device 10 is realized by a computer device.
[0026]
First, in step 11, the bit length input from the input device is set to a variable N. Next, in step 12, it is checked whether N = 1 or not. If N ≠ 1, a circuit of the basic module a stored in the memory is generated in step 13. In step 14, 1 is subtracted from N, and the process is repeated from step 12. When N = 1 in step 12, the circuit of the basic module b is generated in step 15. In step 16, the basic modules generated and stored so far are sequentially connected and output.
[0027]
Thus, according to the circuit automatic generation device of the first embodiment, it is possible to generate the CLA circuit having the input bit length. In addition, since the circuit modules can be selected according to the order of generation, even when the circuit configuration is slightly different depending on the bit position, for example, an output buffer is added only to the output of the final stage, A circuit can be generated.
[0028]
Second embodiment
A circuit automatic generation apparatus according to a second embodiment of the present invention will be described with reference to FIGS.
First, the configuration of the automatic circuit generation device of the second embodiment will be described with reference to FIG.
FIG. 5 is a block diagram showing the configuration of the automatic circuit generation device of the second embodiment.
The automatic circuit generation device 20 includes an input unit 21, a bit length storage unit 22, a remainder calculation unit 23, a module selection unit 24, a 4-bit module generation unit 25, a 3-bit module generation unit 26, a 2-bit module generation unit 27, and a generation circuit. The storage unit 28, the subtraction value determination unit 29, the subtraction unit 30, the determination unit 31, and the output unit 32 are configured.
Similarly to the automatic circuit generation device 10 of the first embodiment, the automatic circuit generation device 20 of this embodiment is also incorporated in a CAD device used when designing a logic circuit or the like.
[0029]
Hereinafter, the operation of each unit will be described.
The input unit 21 is an input device such as a keyboard, and a bit length B, which is a data width of the circuit, is input from the input unit 21 by an operator. The input bit length B is stored in the bit length storage unit 22. Since this bit length B is the bit width of data, an integer of 2 or more is usually input.
The bit length storage unit 22 is a data storage unit configured by a memory, and receives data from the input unit 21, and the data is sequentially updated by a determination unit 31 described later. The data stored in the bit length storage unit 22 is a parameter N representing the bit length for circuit generation. The parameter N stored in the bit length storage unit 22 can be read from the remainder calculation unit 23 and the subtraction unit 30.
[0030]
The remainder calculation unit 23 divides the parameter N stored in the bit length storage unit 22 by a predetermined number, obtains the remainder, and supplies the remainder to the module selection unit 24 and the subtraction value determination unit 29 as a parameter M for selecting a module. Output. The predetermined divisor is a numerical value determined by the maximum bit length of the basic module generated by the module generation unit described later, and is 4 in this embodiment. Accordingly, the remainder of the parameter M takes a value of 0 to 3.
[0031]
The module selection unit 24 is a selection unit that selects a basic module based on the parameter M input from the remainder calculation unit 23. The module selection unit 24 decodes the parameter M, generates a selection signal corresponding to the value of the parameter M, and applies the signal to the corresponding module generation unit. In this embodiment, since the parameter M takes four values of 0 to 3, the module selection unit 24 generates one of the four selection signals S0 to S3, and four output signal lines corresponding to the selection signals. A signal is applied to each module generation unit via. Specifically, when the parameter M is 0, the selection signal S0 is applied to the 4-bit module generation unit 25, and when the parameter M is 1, the 3-bit module generation unit 26 and the 2-bit module generation unit 27 When the selection signal S1 is applied and the parameter M is 2, the selection signal S2 is applied to the 2-bit module generation unit 27. When the parameter M is 3, the selection signal S3 is input to the 3-bit module generation unit 26. Applied.
[0032]
When the selection signal S0 is applied from the module selection unit 24, the 4-bit module generation unit 25 generates a 4-bit module stored in the 4-bit module generation unit 25 as actual circuit information, and generates a generation circuit storage unit 28. Output to. The stored information and the generation of actual circuit information are the same as those in the first embodiment described above.
The 3-bit module generation unit 26 generates a 3-bit module in the same manner as the 4-bit module generation unit 25 based on the selection signal S2 and the selection signal S3 applied from the module selection unit 24.
The 2-bit module generation unit 27 generates a 2-bit module based on the selection signal S1 and the selection signal S2 applied from the module selection unit 24.
[0033]
The generation circuit storage unit 28 stores the basic modules sequentially generated by the 4-bit module generation unit 25, the 3-bit module generation unit 26, and the 2-bit module generation unit 27 by sequentially connecting them in the input order. Part. Information on how to connect is described in the information on each basic module stored in advance in each module generation unit.
[0034]
The subtraction value determination unit 29 obtains the bit length of the circuit module selected by the module selection unit 24 based on the parameter M calculated by the remainder calculation unit 23 and outputs the bit length to the subtraction unit 30 as the subtraction value P. The bit length is obtained by referring to a table stored in advance in the subtraction value determining unit 29 corresponding to each circuit module when each circuit module is stored. In this embodiment, the subtraction value P = 4 when the parameter M = 0, the subtraction value P = 5 when the parameter M = 1, the subtraction value P = 2 when the parameter M = 2, and the parameter M = 3. In this case, the subtraction value P = 3 is obtained and output.
In the subtraction value determination unit 29 according to the present embodiment, the subtraction value P is obtained based on the parameter M calculated by the remainder calculation unit 23. Similarly, the module selection unit 24 generated based on the parameter M is used. May be obtained using the selection signals S0 to S3 output from.
[0035]
The subtraction unit 30 subtracts the subtraction value P selected by the subtraction value determination unit 29 from the bit length parameter N stored in the bit length storage unit 22, calculates the subtraction result Nnew, and outputs the result to the determination unit 31. . That is, each time a circuit module is sequentially selected, a value corresponding to the bit length of the selected circuit module is subtracted from the bit length parameter N to obtain a bit length Nnew waiting for circuit generation.
[0036]
Based on the subtraction result Nnew input from the subtraction unit 30, the determination unit 31 determines whether to repeat the module generation process again or to output the generated circuit after completing the process. Since the subtraction result Nnew is a value indicating the bit length of the circuit to be generated from now on, the determination unit 31 terminates the process when the subtraction result Nnew is 0 or less, and continues to generate the circuit when it is greater than 0. Process. Accordingly, when the subtraction result Nnew is 0 or less, a signal that outputs the circuit data generated and stored so far is output to the output unit 32. If the subtraction result Nnew is greater than 0, the subtraction result Nnew is input to the bit length storage unit 22 and the parameter stored in the bit length storage unit 22 is updated with the subtraction result Nnew.
[0037]
When an output signal is applied from the determination unit 31, the output unit 32 is generated by the 4-bit module generation unit 25, the 3-bit module generation unit 26, and the 2-bit module generation unit 27 until then, and the generation circuit storage unit 28 The circuit information sequentially connected and stored in is read out and output. The output information is arranged at a designated position on the circuit drawing, and is displayed on an output device such as a display in a state that can be viewed by an operator.
[0038]
Next, the operation of automatic circuit generation by the automatic circuit generation device 20 will be specifically described with reference to FIGS.
In this embodiment, the circuit automatic generation device 20 is a circuit automatic generation device that generates a CLA circuit having a desired number of bits for the CLA circuit, as in the first embodiment. In the second embodiment, a CLA circuit having an optimum configuration for each of 4 bits, 3 bits, and 2 bits is prepared in advance as a library, and these are used as basic circuit modules, so that an arbitrary bit length can be obtained. An automatic path generation device that generates a CLA circuit.
FIG. 6 is a diagram illustrating circuit modules stored in the 4-bit module generation unit 25, the 3-bit module generation unit 26, and the 2-bit module generation unit 27. FIG. 6A illustrates a module of a 4-bit CLA circuit. FIG. 2B is a diagram illustrating a module of a 3-bit CLA circuit, and FIG. 3C is a diagram illustrating a module of a 2-bit CLA circuit.
[0039]
FIG. 7 is a diagram illustrating a circuit generated by the automatic circuit generation device 20, which is a 9-bit CLA circuit. As shown in FIG. 7, the 9-bit CLA circuit has a configuration in which a 2-bit CLA circuit, a 3-bit CLA circuit, and a 4-bit CLA circuit are connected in series.
The operation of the automatic circuit generation device 20 when generating a 9-bit CLA circuit will be described below.
[0040]
First, 9 is input as an input value having a bit length from the input unit 21 and stored as a parameter N in the bit length storage unit 22. The remainder calculation unit 23 calculates the remainder 1 by dividing the parameter N by 4. The value 1 of the calculation result is input to the module selection unit 24 as the parameter M, and the selection signal S2 is selected. As a result, the 2-bit module shown in FIG. 6A and the 3-bit module shown in FIG. 6B are generated and stored in the generation circuit storage unit 28. On the other hand, the subtraction value determination unit 29 obtains the subtraction value P = 5 based on the parameter M = 1, and the subtraction unit 30 performs subtraction with the parameter N = 9 to obtain the result 4. Since the result of the subtraction is 4, the determination unit 31 inputs the subtraction result to the bit length storage unit 22 as a new bit length parameter.
[0041]
Based on the parameter N updated in this way, a module is generated again. Since the parameter N = 4 this time, the parameter M = 0, which is a remainder, is generated, and the 4-bit module shown in FIG. 6C is generated, input to the generation circuit storage unit 28, connected to the previous circuit, and stored. The Further, the subtraction value determination unit 29 obtains 4 as the subtraction value P, and as a result, the subtraction result Nnew in the subtraction unit 30 becomes 0. Therefore, an output signal is applied from the determination unit 31 to the output unit 32, and a circuit diagram of the 9-bit CLA circuit shown in FIG. 7 stored in the generation circuit storage unit 28 is output.
[0042]
The automatic circuit generation device 20 can also be realized by a CAD tool mounted on a workstation or the like as in the first embodiment. Processing when the circuit automatic generation device 20 of the second embodiment is applied to such a computer device will be described with reference to FIG.
FIG. 8 is a diagram showing a flowchart when the automatic circuit generation device 20 is realized by a computer device.
[0043]
First, in step 21, the bit length input from the input device is set to the variable N. Next, in step 22, the remainder obtained by dividing N by 4 is calculated and set to a variable M. Then, based on this variable M, it is determined in step 23 whether or not M = 0. If M = 0, a 4-bit module is generated in step 24, and 4 is set in variable P in step 25.
If M.noteq.0 in step 23, it is checked in step 26 whether M = 1 or 2. If M = 1 or M = 2, a 2-bit module is generated in step 27. In step 28, it is determined whether M = 1 or M = 2. If M = 1, 2 is set to the variable P in step 29, and if M = 2, 5 is set to the variable P in step 30.
[0044]
On the other hand, if it is determined in step 26 that M is neither 1 nor 2, that is, if M = 3, 3 is set to the variable P prior to circuit generation in step 31. Then, in step 26 to step 30, a 3-bit module is generated in step 32 together with a case where M = 1 in which a 2-bit module has already been generated.
As described above, when the generation of the module and the setting of the subtraction value to the variable P are completed in step 23 to step 32, NP is subtracted in step 33, and the variable N is updated with this subtraction result. In step 34, the value of the variable N is checked. If the variable N is greater than 0, the process is repeated from step 22. In step 34, when the variable N is 0 or less, in step 35, the circuit modules generated and stored so far are sequentially connected and output.
[0045]
As described above, according to the circuit automatic generation device 20 of the second embodiment, it is possible to generate a CLA circuit having a bit length inputted as in the first embodiment. In particular, even if the stored circuit module is a circuit that processes data of a plurality of bits, a CLA circuit having a desired bit length can be generated by appropriately combining them.
[0046]
Third embodiment
A circuit automatic generation apparatus according to a third embodiment of the present invention will be described with reference to FIG.
The circuit automatic generation device of the third embodiment has a plurality of circuit automatic generation devices of the first embodiment or the second embodiment, and generates a circuit with a more complicated configuration by synthesizing a plurality of types of circuit modules having different operations. This is an automatic circuit generation device that can be used.
The circuit automatic generation device 50 according to the third embodiment includes an input unit 51, first to fourth circuit automatic generation devices 52 to 55, and a synthesis unit 56.
[0047]
In the input unit 51, a signal for selecting the type of module constituting the circuit is input together with the bit length of the processing data, and a signal for instructing the bit length and circuit generation to the circuit module generation device corresponding to the selected signal. Is sent out. A plurality of types of modules may be selected as modules constituting this circuit. Note that the selection order is selected in the order in accordance with the composition rule by the composition unit 56.
[0048]
The first to fourth circuit automatic generation units 52 to 55 are generation means for automatically generating circuit modules each performing a predetermined operation on data having an arbitrary bit length of a predetermined operation. These automatic circuit generation units are, for example, generation units such as a CLA circuit, an addition circuit, a selection circuit, and a shift register circuit. Each circuit automatic generation unit is constituted by, for example, the circuit automatic generation device shown in the first embodiment and the second embodiment, but as connection information stored in the circuit module storage means of each circuit automatic generation unit, In addition to the connection information between the plurality of circuit modules in each circuit automatic generation unit, the connection information between the circuits generated between the first to fourth circuit automatic generation units 52 to 55 is also stored. Has been. The bit length of the processing data of the circuit to be generated is input from the input unit 57.
[0049]
The synthesizer 56 further synthesizes the circuit modules generated by the first to fourth automatic circuit generators 52 to 55 to generate and output one circuit. The synthesizer 56 synthesizes each circuit based on the circuit connection information output from each circuit automatic generator and the connection information of each terminal of the circuit. This synthesis is performed based on a predetermined rule such as connecting the output terminal of the generated circuit module to the input terminal of the next selected circuit in the order selected by the input unit 51, for example.
[0050]
According to the circuit automatic generation apparatus of the third embodiment having such a configuration, a circuit for processing data having an arbitrary bit length is automatically generated, and further, a basic circuit module is combined, which is somewhat complicated. Circuit can be automatically generated, and the efficiency of circuit design can be further improved.
[0051]
The present invention is not limited to the first embodiment and the second embodiment described above, and various modifications can be made.
For example, the present embodiment has been specifically described as a circuit automatic generation device that generates a CLA circuit, but is not limited thereto. Any circuit can be applied as long as it is a circuit that can be configured by sequentially connecting a plurality of basic circuits for arbitrary bit data in series or in parallel. For example, the present invention can be applied to a shift register, a multiplexer, an adder, and the like.
[0052]
Further, the configuration of the circuit module generation unit of the present embodiment is such that each circuit module generation unit generates and outputs a predetermined circuit module based on the applied signal. However, for example, one control unit may be configured by a control unit and a storage unit such that a circuit module is appropriately selected from a circuit module stored in the storage unit and output based on a selection signal.
Further, the present invention does not limit the circuit module and the generated circuit description method. For example, a circuit described in the form of a netlist using basic elements and connection states, a circuit described using a hardware description language (HDL), or a circuit whose operation is described in a function or logic The circuit of the description / format is applicable.
[0053]
【The invention's effect】
According to the circuit automatic generation device of the present invention, an arbitrary number of predetermined circuit modules can be connected based on the number of input bits, and a circuit for processing data having a desired bit length is automatically set. I was able to generate. Also, a circuit having a slightly different configuration depending on the bit position could be generated appropriately. Furthermore, a circuit for processing data having a desired bit length can be generated by combining basic circuit modules corresponding to a plurality of bits. Therefore, it is possible to provide an automatic circuit generation device that can easily redesign a circuit according to a change in bit length.
As a result, it was possible to provide a CAD apparatus capable of greatly reducing the design time and designing the circuit efficiently.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of an automatic circuit generation device according to a first embodiment of the present invention.
2 is a diagram showing a circuit module generated by a basic module generation unit of the automatic circuit generation device shown in FIG. 1, in which (A) shows a basic module a, and (B) shows a basic module b. FIG.
FIG. 3 is a diagram illustrating a circuit generated by the automatic circuit generation device illustrated in FIG. 1;
FIG. 4 is a diagram showing a flowchart when the circuit automatic generation device shown in FIG. 1 is realized by a computer device;
FIG. 5 is a block diagram showing a configuration of an automatic circuit generation device according to a second exemplary embodiment of the present invention.
6 is a diagram illustrating a circuit module generated by a module generation unit of the circuit automatic generation device illustrated in FIG. 5, in which (A) illustrates a 2-bit module, and (B) illustrates a 3-bit module. , (C) is a diagram showing a 4-bit module.
7 is a diagram showing a circuit generated by the automatic circuit generation device shown in FIG. 5. FIG.
8 is a diagram showing a flowchart when the automatic circuit generation device shown in FIG. 5 is realized by a computer device.
FIG. 9 is a block diagram showing a configuration of an automatic circuit generation device according to a third exemplary embodiment of the present invention.
[Explanation of symbols]
10 ... Automatic circuit generator
11 ... Input unit 12 ... Bit length storage unit
13 ... Module selection unit 14 ... Basic module a generation unit
15 ... Basic module b generation unit 16 ... Generation circuit storage unit
17 ... Subtraction unit 18 ... Output unit
20 ... Circuit automatic generation device
22: Bit length storage unit 23: Remainder calculation unit
24 ... Module selection unit 25 ... 4-bit module generation unit
26: 3-bit module generation unit 27: 2-bit module generation unit
28 ... Generation circuit storage unit 29 ... Subtraction value determination unit
30 ... Subtraction unit 31 ... Determination unit
32 ... Output section
50. Automatic circuit generation device
51 ... Input unit 52 ... First circuit automatic generation unit
53 ... 2nd circuit automatic generation part 54 ... 3rd circuit automatic generation part
55 ... Fourth automatic circuit generation unit 56 ... Synthesis unit

Claims (1)

Key The automatic generating apparatus of catcher Li look ahead circuit,
Circuit module storage means for storing circuit information of a plurality of types of circuit modules having different bit lengths of processing data and connection information between the circuit modules;
The circuit module storage stores the bit length of the input processing data by combining circuit modules having different bit lengths based on the calculation result of the bit length of the input processing data and the maximum bit length of the circuit module. Circuit module selection means for sequentially selecting a plurality of types of circuit modules stored in the circuit module storage means for sequentially selecting appropriate circuit modules from a plurality of types of circuit modules stored in the means;
Circuit connection means for sequentially connecting the circuit modules selected by the circuit module selection means based on the connection information of the circuit modules;
Output means for outputting information representing a circuit connected by the circuit connecting means;
Have
The circuit module storage means includes a first circuit module that is a 1-bit carry-look-ahead circuit that outputs a carry to a higher order based on two 1-bit inputs and a carry input from a lower order, Each information of the second circuit module in which an output buffer is further added to the one circuit module is stored,
The circuit module selection means continuously selects the first circuit module whose number is one less than the bit length of the input processing data, and further selects one second circuit module.
Circuits automatic generation system.

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