JP4258350B2 - Arithmetic processing unit - Google Patents

Description

  The present invention relates to an arithmetic processing apparatus that performs numerical arithmetic processing using a microprocessor or a digital signal processor (DSP).

FIG. 6 shows an arithmetic processing unit that performs numerical arithmetic processing using a conventional microprocessor or digital signal processor (DSP). FIG. 6 is a block diagram of an arithmetic processing unit showing a conventional example.
In FIG. 6, 1 is an arithmetic operation unit for performing addition / subtraction / division / division / logical operation and numerical comparison, and 2 is an input memory for holding a value input to the arithmetic operation unit 1 and is composed of two of A and B. Reference numeral 3 denotes an output memory for holding calculation results, and 4 is an operation code setting memory for switching functions to be processed by the arithmetic operation unit 1.
Here, when considering the addition process, first, when an operation code for executing addition is set and a numerical value of 10 is set in the memory A and 20 is set as the input value, the arithmetic unit 1 As an output value from (10 + 20 =) 30 is obtained.
This example is a simple arithmetic process, but in a general arithmetic processing system, a lot of complicated arithmetic processes are processed, and the result calculated by the arithmetic operation unit 1 is fed back to the input memory 2 and 1 The arithmetic processing of the entire system is performed by using one arithmetic operation unit many times.
Recently, in order to perform complicated operations such as image processing, an image processing processor in which a plurality of functional modules are arranged in an arithmetic operation unit has been proposed (see, for example, Patent Document 1).
JP 2000-503427 A (FIG. 1)

However, when performing arithmetic processing using an arithmetic operation unit as in the prior art, it is common to increase the operating frequency of a microprocessor or DSP in order to achieve high-speed operation. . This causes heat generation of the chip and radiation noise, and reduces the reliability of the product.
There is also a means for realizing high speed by arranging arithmetic operation units in parallel. In the image processing processor of JP-T-2000-503427, it is possible to finally output one calculation processing result by parallel calculation. However, since a plurality of calculation processing results cannot be output, the parallel processing property is utilized. Processing has not been realized.
In addition, when a conventional microprocessor or DSP is used in a real-time processing system composed of a plurality of tasks, one arithmetic operation unit is switched for a plurality of different processes to perform the operation. Is difficult to output (the processing time is not constant). That is, at present, there is no arithmetic unit dedicated to real-time processing.

  The present invention has been made to solve the above-described problems, and provides an arithmetic processing apparatus optimal for real-time control arithmetic processing that can improve arithmetic performance even at a low operating frequency without increasing the operating frequency. For the purpose.

    In order to solve the above problem, the present invention as set forth in claim 1 includes an input memory for holding a plurality of input data, a plurality of arithmetic operation units for performing addition / subtraction / multiplication / division, logical operation and numerical comparison, and the arithmetic Shift processing using a plurality of operation code setting memories for determining a function to be executed in the arithmetic unit, an output memory for holding an arithmetic result from the arithmetic arithmetic unit, and an arithmetic result executed in the arithmetic arithmetic unit A plurality of barrel shifter circuits, a setting memory for determining a shift amount of the calculation result, a multiplexer for switching and outputting a plurality of calculation results obtained by the barrel shifter circuit, and an arithmetic function for selecting an output value from the multiplexer In the arithmetic processing device including the code setting memory, the barrel shifter circuit is connected to the arithmetic operation unit. A flag memory for selecting an upper or lower word of the input data, a selector for selecting upper or lower word data, and a zero word for adding zero word data to the output data of the selector It comprises data adding means, a flag memory for enabling the upper or lower word selection function, and a selector for switching input data to the barrel shifter circuit.

  According to a second aspect of the present invention, in the arithmetic processing unit according to the first aspect, a comparator for performing limit calculation processing, a memory for storing upper and lower limit setting values, and the comparator function are enabled. A flag memory is provided.

  According to a third aspect of the present invention, in the arithmetic processing unit according to the first or second aspect, the arithmetic operation unit outputs 1 when a carry occurs in the addition result, and when a borrow occurs. An adder that outputs minus 1 and a flag memory for enabling the function of the adder are provided.

  A fourth aspect of the present invention is the arithmetic processing device according to any one of the first to third aspects, wherein a plurality of the arithmetic processing devices are arranged in parallel.

According to the arithmetic processing device of claim 1, by using the operation code setting of each built-in arithmetic operation unit and the arithmetic function code for selecting the multiplexer output value, many arithmetic functions that can be processed by this arithmetic unit are realized. It is possible to perform complicated arithmetic processing at a time. In particular, by constructing frequently used calculation patterns in the calculation processing as in the motor control system as this calculation processing device, it is possible to perform high-level calculation processing that has been difficult to realize in the past.
In addition, the processing performance can be further improved by making it possible to perform arithmetic processing in parallel with the internal configuration of the arithmetic processing unit. Furthermore, in this arithmetic processing unit, the number of clocks required for the arithmetic processing is the same number of clocks every time, so it is possible to predict the processing time, and it is optimal for real-time control in which the arithmetic processing must be completed within a predetermined time. Become. That is, even if the operation frequency of the arithmetic processing device is not increased, the arithmetic processing performance can be improved and real-time performance can be realized, and the chip heat generation can be suppressed and radiation noise can be prevented.
Conventionally, when it is necessary to shift only the upper word of the data input from the arithmetic unit to the barrel shifter circuit, the shift amount a for extracting the upper word and the shift for shifting the data of the upper word The amount b must be added and input to the shift amount setting memory, but the flag memory for selecting the upper word, the flag memory for enabling the function of this selection signal, and the shift amount b It is only input to the shift amount setting memory. That is, it is possible to eliminate the addition process of the shift amount a and the shift amount b and the multi-stage shift process, and the shift process that required several clocks can be realized with one clock, and the arithmetic processing performance can be improved. .
On the other hand, when it is necessary to shift only the lower word, the conventional barrel shifter circuit needs to shift the data after cutting out the lower word (that is, after masking the upper word). In the described arithmetic processing unit, the flag memory for selecting the lower word, the flag memory for enabling the function of the selection signal, and the shift amount are only input to the shift amount setting memory. That is, the mask process for the upper word is deleted, and a shift process requiring several clocks can be realized with one clock, and the arithmetic processing performance can be improved.

  According to the arithmetic processing apparatus of the second aspect, when the limit process is performed on the final calculation result value, the upper limit and the lower limit process can be executed at a time, which leads to the speeding up of the process. Further, when the limit process is not performed, the input data to the comparator is set to the through state by disabling the valid flag. As a result, the processing can be completed with a constant number of operation clocks regardless of whether or not the limit processing is executed, and real-time performance is maintained.

According to the arithmetic processing apparatus according to claim 3, by processing operations to be processed by the processing unit according to claim 1 or claim 2 wherein in another processing unit, realize high-speed further computation it can. Further, when a plurality of similar arithmetic processes are executed in parallel as in the multi-axis motor control, the effect of the arithmetic processing devices arranged in parallel becomes remarkable. That is, even if the operating frequency of the arithmetic processing device targeted by this patent is not increased, the arithmetic processing performance can be improved and real-time performance can be realized, and the chip heat generation can be suppressed and radiation noise can be prevented.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram of an arithmetic processing unit showing a first embodiment of the present invention, and FIG. 2 is a block diagram of a barrel shifter circuit of the present invention. 1 and 2, 1 is an arithmetic operation unit, 2 is an input memory, 3 is an output memory, 4 is an operation code setting memory, 5 is a barrel shifter, 6 is a circuit connection network, 7 is a multiplexer, and 8 is an operation function code setting memory. , 9 is a shift amount setting memory, 22 is a flag memory for selecting upper / lower words of data input to the barrel shifter circuit, 23 is a flag memory for enabling the upper / lower word selection function, and 24 is A selector for selecting upper / lower word data, 25 is a selector for switching data input to the barrel shifter 5, 26 is a barrel shifter circuit of the present invention, and 27 is zero word data adding means for adding zero word data. .

Next, the operation will be described with reference to FIG.
In the arithmetic processing measure, IN1, IN2,... INm are arranged as an input memory 2 for holding a plurality of input data, and a plurality of arithmetic operation units 1 (ALU1) for performing addition / subtraction / multiplication / division, logical operation and numerical comparison are provided. , ALU2,... ALUN). Data of IN1 and IN2 are input to the arithmetic operation unit ALU1, and data of IN3 and IN4 are input to the arithmetic operation unit ALU2. The operation code setting memory 4 for determining the function to be executed in each arithmetic operation unit is arranged by the number of arithmetic operation units, and the operation codes 1 and 2 correspond to the ALU1 and ALU2. The calculation result executed in each arithmetic operation unit 1 is connected to a barrel shifter circuit 26 that performs a shift process to the left and right, and is shifted by a numerical value stored in a setting memory 9 that determines a shift amount. In FIG. 1, the calculation result of ALU1 is connected to BRL1, the calculation result of ALU2 is connected to BRL2, and the shift amount is determined by the memory values of Shift1 and Shift2. The output values from BRL1 and BRL2 are input to ALU3, the arithmetic processing corresponding to opcode 3 is executed, and the arithmetic result is input to BRL3. On the other hand, the output values of BRL1, BRL2 and BRL3, and the input data of INm are connected to a circuit connection network 6 including a plurality of arithmetic operation units 1 and barrel shifter circuits 26, and other arithmetic processing is possible. The output value from the circuit connection network 6 may be connected to a multiplexer 7 for switching and outputting a plurality of calculation results, or may be input to a further arithmetic operation unit ALUn to execute an operation process corresponding to the operation code n. In some cases, the calculation result is input to BRLn, shifted, and finally input to the multiplexer. Data from the calculation function code setting memory 8 for selecting an output value is input to the multiplexer, and the data is stored in the output memory 3 for holding the calculation output value.

Next, the operation of the barrel shifter circuit 26 will be described with reference to FIG.
First, the case where “0 (invalid)” is set in the upper / lower word selection function valid flag memory 23 will be described. When operation result data is input from the arithmetic operation unit 1, it is input to the barrel shifter 5 via the barrel shifter input data selector 25. The input data is shifted by a numerical value set in the shift amount setting memory 9. This operation is the same as that of a conventional barrel shifter.
On the other hand, a case where “1 (valid)” is set in the upper / lower word selection function valid flag memory 23 will be described. At this time, when “1 (upper word)” is set in the upper / lower word selection flag memory 22, when operation result data is input from the arithmetic operation unit 1, this data is converted into upper word data and lower word data. Only the upper word data is output via the upper / lower word data selector 24. The barrel shifter circuit 26 has zero word data adding means 27, and data obtained by adding zero word data having the same bit width as the output data to the upper side of the output data via the barrel shifter input data selector 25. 5 is input. Subsequent shift processing is performed in the same manner as described above.
In addition, when “0 (lower word)” is set in the upper / lower word selection flag memory 22, when operation result data is input from the arithmetic operation unit 1, this data is converted into upper word data and lower word data. The data is divided and only the lower word data is output via the upper / lower word data selector 24. Data obtained by adding zero word data having the same bit width as that of the output data by the zero word data adding unit 27 is input to the barrel shifter 5 via the barrel shifter input data selector 25 on the upper side of the output data. Subsequent shift processing is performed in the same manner as described above.
Since the first embodiment of the present invention is configured as described above, if the upper / lower word selection function valid flag memory 23 is set to “1 (valid)”, if only the upper word needs to be shifted, the shift is performed. By deleting the amount addition processing, multi-stage shift processing can be reduced. If only the lower word needs to be shifted, the mask process for the upper word can be deleted. In either case, shift processing that required several clocks can be realized with one clock, and the arithmetic processing performance can be improved.

Next, a second embodiment of the present invention will be described.
FIG. 3 is a block diagram of an arithmetic processing unit showing a second embodiment of the present invention.
In FIG. 3, 10 is a comparator, 11 is an upper limit / lower limit setting memory, 12 is a comparator function valid flag memory, and 21 is comparator input data LIN.
The second embodiment is different from the first embodiment in that a comparator 10 for performing limit calculation processing, a memory 11 for storing upper and lower limit setting values, and a flag memory 12 for enabling the comparator function are provided. It is to be prepared.
Next, only the differences from FIG. 1 will be described in order to simplify the operation description.
Data output from a circuit connection network provided in the arithmetic processing device becomes input data 21 (LIN) to the comparator 10 (CMP). LIN is subjected to limit processing based on data set in the upper limit / lower limit setting memory 11 in advance. The comparator 10 outputs the LIN as it is when the LIN is within the range from the upper limit setting value to the lower limit setting value. However, when LIN is equal to or greater than the upper limit limit set value, the upper limit limit set value is output, and when LIN is equal to or lower than the lower limit limit set value, the lower limit limit set value is output.
Further, the limit processing in the comparator 10 is executed only when the flag memory 12 that enables the comparator function is set to be effective. When the comparator function is invalid, the input data LIN is output through the comparator 10.

  Since the second embodiment of the present invention is configured as described above, the present arithmetic processing unit differs from the case where the limit processing is executed by comparing the arithmetic operation units (<,>, etc.) with the upper and lower limits. Since limit processing can be executed in one clock at a time, processing speed can be increased. In addition, regardless of whether or not the limit processing is executed, the processing is completed with a fixed number of operation clocks, so that real-time performance can be maintained.

Next, a third embodiment of the present invention will be described.
FIG. 4 is a block diagram of an adder built in the arithmetic operation unit according to the third embodiment of the present invention.
In FIG. 4, 13 is an adder, and 14 is an adder function valid flag memory.
The third embodiment is different from the first and second embodiments in that the arithmetic unit 1 outputs 1 when a carry occurs in the addition result, and outputs minus 1 when a borrow occurs. An adder 13 and a flag memory 14 for enabling the function of the adder are provided.
When this valid flag is invalid, it functions as a normal adder.

Next, the operation will be described.
By using the arithmetic operation unit 1 incorporating the adder 13, when a carry or borrow occurs in the addition result in the conventional adder, a flag indicating each state is used, and a match / mismatch operation is performed by software. (=,! =, Etc.) The condition is determined, and in the case of carry, 1 can be added to the upper word, and in the case of borrow, the process of subtracting 1 can be reduced. That is, the adder function flag memory 14 is validated, and the addition result and the upper word may be added in both carry / borrow processing.
Since the third embodiment of the present invention has the above-described configuration, the condition determination processing that required several clocks can be realized with one clock, and the arithmetic processing performance can be improved.

Next, a fourth embodiment of the present invention will be described.
FIG. 5 is a block diagram of an arithmetic processing unit showing a fourth embodiment of the present invention.
Reference numeral 15 denotes the arithmetic processing unit described in the first to third embodiments of the present invention.
The fourth embodiment is different from the first to third embodiments in that a plurality of arithmetic processing devices 15 are arranged in parallel. The contents of processing in each arithmetic processing unit are as already described in the embodiments.
However, by arranging these arithmetic processing devices in parallel, when one arithmetic processing device of the present invention is used, it is possible to perform parallel processing on the processing that has been performed in several steps.

  Since the fourth embodiment of the present invention is configured as described above, in a system that executes parallel arithmetic processing, it is possible to significantly improve the arithmetic performance by utilizing the parallel arithmetic function of the arithmetic processing unit. it can.

  Since the computation performance can be improved by parallel processing of complex computations, it can be used to improve the performance of FA-use control devices and signal processing devices.

It is a block diagram of the arithmetic processing unit showing the first embodiment of the present invention. It is a block diagram of the barrel shifter circuit of this invention. It is a block diagram of the arithmetic processing unit which shows 2nd Example of this invention. It is a block diagram of the adder built in the arithmetic operation unit which shows 3rd Example of this invention. It is a block diagram of the arithmetic processing unit which shows 4th Example of this invention. It is a block diagram of the arithmetic processing unit which shows a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Arithmetic operation unit 2 Input memory 3 Output memory 4 Operation code setting memory 5 Barrel shifter 6 Circuit connection network 7 Multiplexer 8 Arithmetic function code setting memory 9 Shift amount setting memory 10 Comparator 11 Upper limit / lower limit setting memory 12 Comparator function effective flag memory 13 Addition 14 Adder function valid flag memory 15 Arithmetic processor 21 Comparator input data LIN
22 upper / lower word selection flag memory 23 upper / lower word selection function valid flag memory 24 upper / lower word data selector 25 barrel shifter input data selector 26 barrel shifter circuit 27 zero word data addition means

Claims (3)

An input memory for holding a plurality of input data, a plurality of arithmetic operation units for performing addition / subtraction / multiplication / division, logical operation and numerical comparison, and a plurality of operation code settings for determining a function to be executed by the arithmetic operation unit A memory, an output memory for holding an operation result from the arithmetic operation unit, a plurality of barrel shifter circuits that perform shift processing using the operation result executed by the arithmetic operation unit, and a shift amount of the operation result are determined; In an arithmetic processing device comprising: a setting memory; a multiplexer that switches and outputs a plurality of arithmetic results obtained by the barrel shifter circuit; and an arithmetic function code setting memory that selects an output value from the multiplexer.
The barrel shifter circuit uses a calculation result from the arithmetic operation unit as input data, and a flag memory for selecting an upper or lower word of the input data;
A selector for selecting upper or lower word data;
Zero word data adding means for adding zero word data to the output data of the selector;
A flag memory to enable the upper or lower word selection function;
An arithmetic processing unit comprising: a selector for switching input data to the barrel shifter circuit. A comparator for performing limit calculation processing;
Memory for storing upper and lower limit setpoints,
The arithmetic processing apparatus according to claim 1, further comprising: a flag memory that enables the comparator function. 3. The arithmetic processing device according to claim 1, wherein a plurality of the arithmetic processing devices are arranged in parallel.

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