JPH04342067A - Vector arithmetic unit - Google Patents

Abstract

PURPOSE:To shorten processing time by providing a mask vector register part and a mask vector shifting part and supporting a mask vector generation command with a logic operation mask vector to generate a mask vector after the logic operation of the two mask vectors. CONSTITUTION:A vector command control part 8 controls a vector arithmetic unit 1. The mask vector register part 2 holds the mask vector. An operand comparison part 5 compares the size relation of the data operand of operand storage parts 3 and 4 receiving two data operands and outputs a comparison result as a mask bit of one bit. A mask logic operation part 6 executes the logic operation of the most significant bit of the register part 2 and the one bit outputted by the comparison part 5. A mask vector shifting part 7 receives the content of the register part 2, shifts it by one bit in the direction of the most significant bit and inputs the mask vector of one bit outputted to the idle least significant bit by the operation part 6.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector arithmetic device, and more particularly to a vector arithmetic device that supports mask vector generation instructions.

0002

2. Description of the Related Art In conventional vector arithmetic devices, the use of mask vectors themselves has been prohibited or disabled for the execution of mask vector generation instructions. Therefore, in order to implement a vector operation instruction using mask vectors based on the logical conditions of multiple mask vectors, each mask vector is generated using multiple mask generation instructions, and these are logically operated using a logical variable length instruction. After generating a mask to be finally used, a vector operation instruction using this mask vector is executed.

0003

[Problems to be Solved by the Invention] The conventional vector arithmetic device described above prohibits or disables the use of mask vectors in mask vector generation instructions, and therefore uses masks after logical operations on multiple mask vectors. In order to execute a vector operation instruction, it is necessary to execute a logical variable length operation instruction in addition to the mask generation instruction, and the processing time for executing the logical variable length operation instruction (i.e., the number of mask vectors - 1 time) is required. There is a problem in that the processing time required to execute the logical variable length operation instructions is required.

An object of the present invention is to support a mask vector generation instruction with a logical operation mask vector for generating a mask vector after logical operation of two mask vectors without executing a logical variable length operation instruction. An object of the present invention is to provide a vector arithmetic device capable of shortening program processing time.

[0005]

[Means for Solving the Problems] A vector arithmetic device of the present invention includes a mask vector register section for holding mask vectors, and a mask vector register section for holding mask vectors, and two
an operand comparison section that receives two data operands, compares the magnitude relationship between the two data operands, and outputs the comparison result as a 1-bit mask bit; a mask logic operation unit that performs logical operations with bits and outputs a 1-bit mask vector; and a mask logic operation unit that performs logical operations with bits and outputs a 1-bit mask vector;
The configuration includes a mask vector shift section that inputs a 1-bit mask vector output from the mask logic operation section into the least significant bit vacated by bit shifting, and a vector instruction control section that controls each of the sections.

[0006]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The vector calculation device 1 of the present invention includes a mask vector register section 2 that holds mask vectors and exchanges data with a memory (not shown), and a mask vector register section 2 that holds mask vectors and exchanges data with a memory (not shown); operand storage units 3 and 4 that receive two data operands that are not specified, and an operand comparison unit 5 that compares the magnitude relationship of the two data operands from the operand storage units 3 and 4 and outputs the comparison result as a 1-bit mask bit. and a mask logic operation unit 6 that performs a logical operation on the most significant bit of the mask vector register unit 2 and the 1 bit output from the operand comparison unit 5 and outputs a 1-bit mask vector;
A mask vector shift unit 7 receives the contents of the mask vector register unit 2, shifts one bit in the direction of the most significant bit, and inputs a 1-bit mask vector output from the mask logic operation unit 6 into the vacant least significant bit, and each of the above-mentioned units. and a vector command control section 8 for controlling the vector command control section 8.

Next, the operation will be explained.

The operand comparison unit 5 compares the magnitude relationship between the two data operands from the operand storage units 3 and 4 to be compared, and compares the comparison result (mask 2 ) is output as 1 bit. The mask vector register section 2 initially holds the used mask vector (mask 1) currently stored in the memory used for logical operations, and when processing starts, the used mask vector (mask 1) output from the mask vector shift section 7 is stored. 1) and the edited data of the generated mask vector (mask 3) are held. The mask logic operation unit 6 is a 1-bit logic operation circuit that uses the 1-bit mask bit (mask 2) generated by the operand comparison unit 5 and the used mask vector (mask 1) held in the mask vector register unit 2.
) is subjected to a logical operation according to the type of logical operation instructed by the vector instruction control unit 8, and is output to the mask vector shift unit 7. The mask vector shift unit 7 shifts the 1-bit mask bit (mask 2) output from the mask logic operation unit 6 to the right side of the used mask vector (mask 1) and the generated mask vector (mask 3) held by the mask vector register unit 2. ) are combined, shifted one bit to the left, and outputs the result to the mask vector register section 2.

Next, the actual operation will be explained.

Assuming that there is a mask vector A already generated by a mask vector generation instruction, this mask vector A is used as an AND condition, and a logical operation is performed when the comparison condition of two data operands is "equal". Mask vector with mask vector A case in which a generation instruction is executed will be explained.

First, under the control of the vector instruction control section 8, the mask vector register section 2 sets a mask vector A, which is a mask vector to be used. Next, the two data operands used in this instruction are stored in the operand storage units 3 and 4, and are sequentially input to the operand comparison unit 5. The operand comparison unit 5 is instructed by the vector instruction control unit 8 to specify the condition of “equal”, and if it compares one set of data operands and the condition is met, it will be “1”.
0” to the mask logic operation unit 6. The mask logic operation unit 6 outputs the logic operation type “AN” from the vector instruction control unit 8.
D", performs an AND logical operation between the output of the operand comparison section 5 and the most significant 1 bit of the mask vector A, which is the mask vector to be used held in the mask vector register section 2, and sends the result to the mask vector shift section. 7. The mask vector shift unit 7 outputs the mask vector A to the right side of the mask vector A held in the mask vector register unit 2.
The generated mask vectors output from the mask logic operation unit 6 are concatenated and inputted, shifted 1 bit to the left, discarded 1 bit of the used mask vector A, and added the generated mask vector to the right side, and then input the generated mask vector to the mask vector register. Output to section 2. The mask vector register unit 2 holds the generated mask vectors and used mask vectors output by the mask vector shift unit 7, and when the register is full of generated mask vectors, the mask vector register unit 2 stores the mask vectors in the memory of the vector instruction control unit 8. If there is a subsequent data operand, set the next mask vector to be used.

The above processing is repeated until there are no more data operands, and when there are no more data operands, the vector instruction control section 8 outputs the generated mask, if any, remaining in the mask vector register section 2 to the memory. Finish post-processing.

Note that in this embodiment, the mask logic operation section 6
Although the case where an AND instruction is given has been described above, the mask logic operation section 6 also has functions such as OR and exclusive OR in addition to AND.

[0016]

As explained above, the present invention has a mask vector register section for holding a mask vector, and a system that receives two data operands that are vectorized or not and determines the magnitude relationship between the two data operands. and an operand comparison section that compares and outputs the comparison result as a 1-bit mask bit, and performs a logical operation on the most significant bit of the mask vector register section and the 1 bit output from the operand comparison section and outputs a 1-bit mask vector. a mask logic operation section; a mask vector shift section that receives the contents of the mask vector register section, shifts one bit in the direction of the most significant bit, and inputs a 1-bit mask vector output from the mask logic operation section into the vacant least significant bit; By having a vector command control section that controls each section,
To reduce program processing time by supporting a mask vector generation instruction with a logical operation mask vector for generating a mask vector after logical operation of two mask vectors without executing a logical variable length operation instruction. This has the effect of making it possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

[Explanation of symbols]

1 Vector calculation device 2 Mask vector register section 3, 4 Operand storage section 5 Operand comparison section 6 Mask logic operation section 7 Mask vector shift section 8 Vector instruction control unit

Claims (1)

[Claims] Claim 1: A mask vector register section for holding a mask vector, which receives two data operands that are vectorized or not, compares the magnitude relationship between the two data operands, and converts the comparison result into a 1-bit mask. an operand comparison unit that outputs as a bit; a mask logic operation unit that performs a logical operation on the most significant bit of the mask vector register unit and the 1 bit output from the operand comparison unit and outputs a 1-bit mask vector;
a mask vector shift unit that receives the contents of the mask vector register unit, shifts one bit in the direction of the most significant bit, and inputs a 1-bit mask vector output from the mask logic operation unit to the vacant least significant bit; and controls each of the units. 1. A vector arithmetic device comprising: a vector instruction control unit.