JP3525582B2 - Bit operation circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit operation circuit for executing bit operation in a microcomputer or the like realized by an integrated circuit.

[0002]

2. Description of the Related Art For example, an arbitrary 1-bit operation in a CPU is set, reset, or a logical operation with another signal for arbitrary 1-bit data, or an arbitrary 1-bit from a plurality of 1-bit data. It is to extract data.

Conventionally, regarding the setting and resetting of the CPU, an arithmetic processing unit (hereinafter referred to as ALU) has been used.
It is common to process by a soft method. For example,
To set the least significant 1 bit "d" for 4-bit data "abcd", 4-bit data "abcd"
And the 4-bit constant “0001” may be ORed using the ALU. Similarly, if resetting, it can be processed by ANDing the 4-bit data "abcd" and the 4-bit constant "1110". In addition, in order to perform a logical operation with another signal or to extract an arbitrary 1 bit as 1-bit data, a bit selection circuit that can select each bit of the operand and a selected bit It is common to have a configuration including a logic operation circuit for performing a logic operation with other signals.

A hardware method for logically operating an arbitrary 1 bit of the operand is also considered, and an example thereof is Japanese Patent Publication No. 5-45978. As shown in FIG. 12, this is a temporary register 1 for storing the operand, a selection register 2 for holding the address data, a flip-flop 3 with a set / reset function for storing the operation result, and a bit selection for selecting an arbitrary bit. It is composed of a circuit 4, a logical operation circuit 5, and a control circuit 6 for controlling each circuit.

Here, the data length of the embodiment shown in FIG. 12 is 8 bits, and the 8-bit data is held in the temporary register 1, and the upper 3 bits are held as an address in the selection register. The bit selection circuit 4 determines the bit to be selected by decoding the address held in the selection register, extracts 1-bit data from the temporary register 1 and outputs it to the logical operation circuit 5.

Then, in the logical operation circuit 5, a logical operation is performed using the output of the flip-flop 3 with the set / reset function and the 1-bit data fetched from the temporary register 1, and the result is switched as necessary by the NMOS 7 which is a switch. , To the temporary register 1 via the bit selection circuit 4. By the processing procedure as described above, various bit operations can be performed by the logical operation circuit 5.

[0007]

However, the CPU
In the software method using the ALU, if the bit operation is limited to only set / reset, it is excellent in that it can be performed without adding a circuit, but it is a logical operation with another signal or an arbitrary 1 bit. Is difficult to extract as 1-bit data, and even if it can be implemented, it is necessary to add a circuit and make an instruction into multiple cycles. Therefore, a CP including a bit manipulation instruction
There is a problem of lowering the performance (efficiency) of U and the like.

As a hardware method, in a configuration having a bit selection circuit and a logical operation circuit for performing a logical operation on the selected bit with other signals for each bit of the data to be operated, the circuit for each bit is large. Therefore, there is a problem that the layout area increases. Particularly, in Japanese Patent Publication No. 5-45978, the temporary register 1 and the flip-flop 3 are used as constituent elements, and in view of the application that does not require data retention, the circuit becomes unnecessarily large and the layout area increases. There's a problem.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a bit operation circuit capable of suppressing an increase in the number of elements or an increase in layout area while executing a bit operation at high speed. Especially.

[0010]

According to a first aspect of the present invention, a logical operation circuit performs a predetermined logical operation for both 1 and 0 as operand data for 1-bit data given from the outside. Is executed and both logical operation data are output respectively. At this time, the bit selection circuit selects the logical operation data corresponding to 1 when the 1-bit data input from the input line is 1 and the operated data output from the logical operation circuit is 1; data selects the logic operation data corresponding to 0 you output to the output line.

Here, the address decoder selectively selects a predetermined one of the bit selection circuits based on the input address data. Then, the bit selection circuit selected by the address decoder selects the logical operation data from the logical operation circuit according to the 1-bit data input from the input line and outputs it to the output line. Therefore, a logical operation can be executed at high speed for one bit data of a plurality of bit data in one cycle.

According to the second aspect of the invention , the logical operation circuit outputs 1 and 0 as logical operation data when receiving the bit extraction instruction. At this time, the bit selection circuit selected by the address selection circuit outputs the 1-bit data input from the input line to the extraction data line. When the 1-bit data input from the input line is 1, 1 output from the logical operation circuit is selected, and when 0, 0 is selected and output.

On the other hand, the bit selection circuit not selected by the address selection circuit outputs the 1-bit data input from the input line to the output line and shuts off the extraction data line. Here, all the extracted data lines of each bit selection circuit are 1
Since it is connected to the extracted data output line of the book, it is possible to extract arbitrary 1-bit data of the plurality of bit data input from the input line from the extracted data output line.

[0014]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described with reference to FIG. FIG. 1 shows the basic configuration of the present invention. This Figure 1
Shows a bit operation circuit for a plurality of bits, and as a signal line, an input line 11 for inputting a plurality of bits of data in parallel, and an output line 12 provided corresponding to the input line 11 for outputting a plurality of bits of data in parallel. , N-bit address line 13, m for deciding the content of the selected 1-bit logical operation
A bit logical operation control line 14 and a logical operation input line 15 for inputting 1-bit data to be logically operated with the selected 1 bit are provided.

The circuits connected to the signal lines include a plurality of bit selection circuits 16 interposed between the input line 11 and the output line 12, an address recorder 17 connected to the address line 13, and a logic. A logic operation circuit 18 connected to the operation control line 14 and the logic operation input line 15 is provided.

The logical operation circuit 18 includes a logical operation input line 15
1-bit data to be input as data to be operated from and "1" and "0" as data to be operated are logical operation control line 1
The operation is performed by the logical operation determined in step 4, and the logical operation result is used as the operation result node 19 for each bit selection circuit 1
Output to 6. In this case, the operation result node 19 shows the result of the logical operation of the 1-bit data input from the logical operation input line 15 and "1", and the result of the operation 1 node, the 1-bit data and the logical operation result of "0". Computation result 0 node.

The address decoder 17 decodes n-bit address data, sets only one of the bit selection nodes connected to each bit selection circuit 16, and resets the other bit selection nodes.

When the bit selection node 20 from the address recorder 17 is set, the bit selection circuit 16 operates according to whether the 1-bit data input from the corresponding input line 11 is "1" or "0". The operation result 1 node or operation result 0 node from 18 is selected, and the selected operation result 1 node or operation result 0 node is output from the output line 12 instead of the input data from the input line 11. That is, when the input bit is "1", the operation result 1 node is output from the output line 12, and when the input bit is "0", the operation result 0 node is output from the output line 12. In this case, the bit selection circuit 16 from which the bit selection node 20 from the address recorder 17 is reset outputs the input data from the input line 11 to the output line 12.

Therefore, at the same time the logical operation circuit 18 executes the logical operation of 1-bit data as the data to be operated and "1" and "0", the bit selection circuit 16 causes the input line 1 to operate.
Since the logical result node 19 from the logical operation circuit 18 is selected and output to the output line 12 in accordance with the 1-bit data as the data to be input inputted from 1, the 1-bit data input / output operation and the logical operation operation One operation can be executed at high speed. Therefore, the logical operation for 1-bit data input from the arbitrary input line 11 can be completed in one cycle.

Next, a first embodiment of the present invention will be described with reference to FIGS.
Will be described with reference to. FIG. 2 shows a 4-bit bit operation circuit. The same parts as those shown in FIG. This bit manipulation circuit is C
It is configured as a PU logic circuit. Here, the input line 11 is generally connected to the output of the register file (the bus to which the read data is output). Further, although the output line 12 is connected to one input of the ALU, it is not unconditionally specified depending on the configuration of the CPU.

On the other hand, from the logical operation input line 15, flags (overflow, carry, negative, zero, etc.),
Alternatively, an immediate date (data directly input from the operand) is input, but it is not generally defined depending on the CPU configuration. The circuits connected to the input line 11 and the output line 12 and the data input from the logical operation input line 15 are examples, and are not limited to these.

The input line 11 selects four to input 4-bit data in parallel, the output line 12 selects four to output 4-bit data in parallel, and the address line selects 1 bit out of 4 bits. Therefore, two logical operation control lines 14 are provided to determine one logical operation content from a plurality of logical operation contents.

In this case, the address decoder 17 sets one of the four bit selection nodes 20 by decoding the 2-bit address data. When the bit selection node from the address decoder 17 is set, the bit selection circuit 16 receives the corresponding input line 1
Instead of the data from 1, the operation result node 19 from the logical operation circuit 18 is selected and output from the output line 12.

Next, each of the above circuits will be described. 3 and 4 show an example of the bit selection circuit 16. In FIGS. 3 and 4, the bit selection circuit 16 includes:
The input line 11 and the output line 12 are connected, and the bit selection node 20, the operation result 1 node 19a, and the operation result 0 node 19b are connected.

The bit selection circuit 16 is composed of a calculation result selector 21 and an output selector 22. The calculation result selector 21 includes two analog switches 2
When the input bit data from the input line 11 is "1", the operation result 1 node 19a is connected to the operation result node 25.
In the case of "0", the operation result 0 node 19b is connected to the operation result node 25.

The output selector 22 is composed of two analog switches 26 and one inverter 27, and operates when the bit selection node 20 is "1", that is, when the bit selection circuit 16 is selected. The operation result node 25 which is the output of the result selector 21 is connected to the output line 12, and the input line 11 is connected to the output line 12 when the bit selection node 20 is "0", that is, when the bit selection circuit 16 is not selected. Therefore, 1-bit data input from the input line 11 is output to the output line 12.

Therefore, the bit selection circuit 16 selected by the address decoder 17 outputs the operation result 1 node 19 when the 1-bit data input from the input line 11 is "1".
a is output to the output line 12, and when it is "0", the operation result 0 node 19b is output to the output line 12.

FIGS. 5 and 6 show an example of the address decoder 17. In FIG. 5 and FIG. 6, two address lines 13 are connected to the address recorder 17. This address recorder 17 has four 2-input N
It is composed of an OR 28 and two inverters 29. Two
The input NOR 28 sets the output to “1” only when all the inputs are “0”, and sets the outputs to “0” in all other cases. Therefore, of the 2-bit address lines 13, the upper address line 13 in the figure is used. Is "1" and the lower address line 13 is "0", only the second line from the left of the NOR 28 output lines outputs "1".

7 and 8 show an example of the logical operation circuit 18. 7 and 8, the logical operation circuit 18 is composed of an AND circuit 30 and an OR circuit 31. The AND circuit 30 has two analog switches 3
It is composed of two and one inverter 33. When the logical operation control line 14 on the upper side in the figure is "1", AND can be executed by turning on the analog switch 32. Further, the OR circuit 31 is composed of two analog switches 34 and one inverter 35,
When the logical operation control line 14 on the lower side of the drawing is "1", the OR can be executed by turning on the analog switch 34.

Here, since the input data from the input line 11 which is the other processed data to the logical operation input line 15 is "1" or "0", the logical operation circuit 18
Assumes that the input data is 1, 0, the logical operation input line 15
The 1-bit data input from and the "1" and "0" are prospectively simultaneously calculated. Therefore, the output from the logical operation circuit 18 is two, and the result assuming that the input data is "1" is the operation result 1 node 19a, and the result assuming that the input data is "0" is the operation result 0 node 19b.

In this case, since the input data from the input line 11 is assumed to be 1,0, the structure of the logical operation circuit 18 can be simplified. That is, for example, as a logical operation A
When performing ND, if the input data is assumed to be "0", the operation result is "0" regardless of the value of the other operated data, and if the input data is assumed to be "1", the other operated data is processed. The calculation data is the calculation result.

Similarly, when OR is executed as a logical operation, if the input data is assumed to be "0", the other operated data becomes the operation result, and if the input data is assumed to be "1", " 1 ”is the calculation result.

Therefore, when performing logical operation on all data in advance, the logical operation circuit 18 generally requires twice the normal operation circuit, but as described above, the logical operation is required. Since the circuit 18 can be logically simplified, the circuit scale can be suppressed to almost the same level as in the case of not looking ahead.

Next, as an example of the operation, the case of setting the 4th bit data from the input line 11 will be described. still,
FIG. 8 , which is a circuit example of the logical operation circuit 18, does not correspond to the contents of this description. When the CPU reads the instruction stored in the memory and latches it in a decoder (not shown), the decoder passes an address indicating the 4th bit of the input line to the address decoder 17, and at the same time issues an instruction to set data to the logical operation circuit 18. hand over.

Then, the address decoder 17 sets only the bit selection node 20 from the address to the bit selection circuit 16 of the 4th bit, and resets the bit selection nodes 20 of the other bits. At the same time, the logical operation circuit 18 executes two logical operations assuming that 1-bit data input from the input line 11 is “1” or “0”, respectively, according to an instruction from the logical operation control line 14. Two operation result nodes 19a and 19b are output.
In the logical operation here, two operation result nodes 19a,
Both 19b are set to "1".

Further, at the same time, the bit selection circuit 16 of the 4th bit selectively selects the operation result 1 node 19a or the operation result 0 node 19b according to the input data "1" or "0" from the input line 11. It is selected and output to the output line 12. That is, the input data from the input line 11 is "1".
In the case of, the operation result 1 node 19a is connected to the output line 12, and when the input data is “0”, the operation result 0 node 19
b is connected to the output line 12. In this case, the bit selection circuits 16 other than the 4th bit connect the input line 11 to the output line 12. With the above operation, it is possible to output from the output line 12 only the 1-bit data input to the 4th bit of the input line 11 is set.

According to the above configuration, since the address decoder 17, the logical operation circuit 18 and the bit selection circuit 16 operate simultaneously in the cycle following the cycle in which the decoder of the CPU decodes the instruction, the bit operation is performed in one cycle. It becomes possible to execute. In other words, the address decoder 17, the logical operation circuit 18, and the bit selection circuit 16 can function as a selector whose output result is determined by the data input timing.

9 to 11 show a second embodiment of the present invention, in which the same parts as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. The second embodiment is characterized in that a function of extracting the input data selected as the data to be operated among the input data from the input line 11 as 1-bit data and outputting the 1-bit data is added.

9 and 10 show the bit selection circuit 16. 9 and 10, the bit selection circuit 16 is configured by adding a 1-bit data output function. That is, an analog switch 36 is newly provided in the output selector 22 and the input data from the input line 11 is output to the 1-bit data extraction data line 37 while the analog switch 36 is turned on. Since the analog switch 36 is turned on / off according to the bit selection node 20, in the bit selection circuit 16 selected when the bit selection node 20 becomes "1", the analog switch 3
6 is turned on, and the input data from the input line 11 is output to the extracted data line 37. Further, in the bit selection circuit 16 which is not selected, the analog switch 36 is turned off and the extraction data line 37 is turned off (high impedance).

In FIG. 11, the extracted data lines 37 of each bit selection circuit 16 are all connected to the extracted data output line 38, and the extracted data output line 38 is 1-bit data.
Is output from. Therefore, the extracted data output line 38 is connected to the input line 1 corresponding to the selected bit selection circuit 16.
Since the 1-bit data input from 1 is output, any 1-bit data can be extracted from the plurality of 1-bit data input from the input line 11.

Next, as an example of the arithmetic operation, the case of extracting the 4th bit data of the input data from the input line 11 will be described with reference to FIG. Bit selection circuit 1
The circuit shown in FIG. 10 is used as 6.

When a decoder (not shown) reads an instruction to execute the data extraction of the 4th bit, the decoder reads the input line 1
An address indicating the 4th bit of 1 is passed to the address decoder 17, and an instruction to pass data is passed to the logical operation circuit 18. Then, the address decoder 17 sets only the bit selection node 20 from the address to the bit selection circuit 16 of the fourth bit, and resets the bit selection nodes 20 of the other bits. At the same time, in the logical operation circuit 18, the two operation result nodes 19a and 19b, which assume that the selected bits are "1" and "0", respectively, are set to "1" and "0" in response to the instruction from the logical operation control line 14, respectively. .

Further, the bit selection circuit 16 for the fourth bit
Selects two operation result nodes 19a and 19b according to whether the input data from the input line 11 is "1" or "0" and outputs them to the output line 12. In other words, when the input is 1, the operation result 1 node 19a on the side assuming 1 is selected and output, so that it becomes 1. When the input is 0, the operation result 0 node 19b on the side assuming 0 is selected. It is 0 because it is output. That is, it is synonymous with passing the input data from the input line 11 to the output line 12.

At this time, the bit selection circuit 16 for the fourth bit selected by the bit selection node 20 outputs the input data to the extracted data line 37 via the analog switch 36. The bit selection circuit 16 other than the 4th bit
Then, the data of the input line 11 is output to the output line 12.

As a result of the above operation, the input data from the input line 11 is output to the output line 12 as output data, and at the same time, the 1-bit data of the fourth bit is output from the extracted data output line 38.

As a method of using the 1-bit data extracted in this way, for example, a CP of 32-bit internal bus is used.
In U, assuming that a specific register represents a predetermined state of various external devices by "1" or "0", this specific register may represent the states of 32 external devices. Therefore, for example, in order to execute a specific process according to the state of the device corresponding to the 24th bit, the 1st bit data of the 24th bit is extracted from the 32bit data, and the extracted 1bit data is converted into the extracted 1bit data. Accordingly, processing is performed using an instruction such as a conditional branch. In other words, the extracted bit data can be used like a flag.

The present invention is not limited to the above embodiment, but can be modified or expanded as follows. Input line 11
Alternatively, the address decoder 17 may be omitted after providing one output line 12 and one output selection line 12 correspondingly. You may make it apply to IC other than CPU.

[Brief description of drawings]

FIG. 1 is a block diagram showing the basic configuration of the present invention.

FIG. 2 is a view corresponding to FIG. 1 showing a first embodiment of the present invention.

FIG. 3 is a block diagram showing a bit selection circuit.

FIG. 4 is an electric circuit diagram showing a configuration of a bit selection circuit.

FIG. 5 is a block diagram showing an address decoder.

FIG. 6 is an electric circuit diagram showing a configuration of an address decoder.

FIG. 7 is a block diagram showing a logical operation circuit.

FIG. 8 is an electric circuit diagram showing a configuration of a logical operation circuit.

FIG. 9 is a view corresponding to FIG. 3 showing a second embodiment of the present invention.

FIG. 10 is a view corresponding to FIG.

FIG. 11 is a view corresponding to FIG.

FIG. 12 is a view corresponding to FIG. 2 showing a conventional example.

[Explanation of symbols]

11 is an input line, 12 is an output line, 16 is a bit selection circuit,
Reference numeral 17 is an address decoder, 18 is a logical operation circuit, 37 is an extracted data line, and 38 is an extracted data output line.

Continuation of the front page (56) Reference JP-A-3-129425 (JP, A) JP-A-7-160498 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 7 / 00

Claims (2)

(57) [Claims] 1. An input line for inputting 1-bit data and 1
And an output line for outputting the bit data, the bit manipulation circuit for outputting a logical operation data logical operation and one bit data supplied from the 1-bit data and the external input from the input line to the output line, said input There are multiple lines and output lines,
The bit selection circuit corresponds to the input line and the output line.
A plurality of 1-bit data externally applied, which performs a predetermined logical operation on both 1 and 0 as the operand data and outputs both logical operation data, and an input. The bit selection circuit based on the address data
Address deco that selectively selects a predetermined one from among
And 1-bit data input from the input line in a state of being selected by the address decoder, the logical operation data output from the logical operation circuit selects the logical operation data corresponding to 1. If it is 0, the logical operation data corresponding to 0 is selected and output to the output line.
At the same time, if not selected, input from the input line 1
And a bit selection circuit for outputting bit data to the output line . 2. The logic operation circuit executes a bit extraction instruction.
When received, outputs 1 and 0 respectively as logical operation data
The bit selection circuit is selected by the address decoder.
1-bit data input from the input line when selected
To the extracted data line and input from the input line
When the 1-bit data is 1, the output from the logical operation circuit
Output 1 by selecting 1 to be applied and 0 when 0
Output to the input line, and input from the input line if not selected.
The 1-bit data to be output is output to the output line and extracted.
The output data line is cut off (high impedance).
Configured urchin, the all one extraction data lines from the bit selection circuit
The output data output line is connected to the extraction data output line.
The described bit operation circuit.