JP2003337694A - Shift circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To set an optional shift direction and improve a processing speed in a prescribed bit shift of input data. <P>SOLUTION: A shift circuit is provided with n pieces of barrel shifters 12a, 12b, 12c, 12d to 12n which are set to a different shift amount to m-bit data being input bit data and a shift control circuit 11 which controls the operation of each of barrel shifters 12a, 12b, 12c 12d to 12n. The shift control circuit 11 sets the shift directions of the m-bit data being the input bit data so that they may have optionally same direction and controls each of the barrel shifters 12a, 12b, 12c, 12d to 12n to shift an optional shift amount to the input bit data. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift circuit used in a semiconductor logic circuit, and more particularly to a shift circuit that shifts data of a bit string by an arbitrary bit length.

[0002]

2. Description of the Related Art Various circuit formats have been proposed for a shift circuit used as an arithmetic function unit in a semiconductor logic circuit.

As an example thereof, when the data is shifted in one direction of the upper bit direction (for example, left direction) or the lower bit direction (for example, right direction) with respect to the 8-bit data, a bit which is a data shift amount. A shift circuit whose length can be changed is disclosed in Japanese Patent Application Laid-Open No. 5-204595. The shift circuit is shown in FIGS. 7 (a) and 7 (b).

FIG. 7A is a schematic diagram showing the overall structure of an 8-bit barrel shifter circuit that shifts 8-bit data only in one direction, for example. The 8-bit barrel shifter circuit of FIG. 7A has 8 selectors each having a plurality of selectors.
It is composed of one selector group 111 to 118. Each of the selector groups 111 to 118 is a selector group composed of three stages of shifters. Each selector group 111 to
The input signal 102 is input to 118, and 4
The bit shift signal 105, the 2-bit shift signal 106, and the 1-bit shift signal 107 are also input, and the output signal 103 is output.

FIG. 7B shows selector groups 111 to 11 which form the 8-bit barrel shifter circuit shown in FIG. 7A.
9 is a configuration diagram of one selector group in FIG. Each selector group has the same configuration, and as shown in FIG. 7B, a selector 201 for 4-bit shift, a selector 202 for 2-bit shift, and a selector 203 for 1-bit shift are arranged horizontally. Data are provided by the selectors 201 to 203, respectively.

An input signal 204 and a 4-bit shift signal 205 are input to the selector 201, and the selector 20
The 2-bit shift signal 206 is input to 2, and the 1-bit shift signal 207 is input to the selector 203.

The selector 201 receives the 4-bit shifted signal 210, and the selector 202 receives the signal 210.
The signal 209 shifted by 2 bits is input, and the signal 208 shifted by 1 bit is input to the selector 203. The signals 208, 209 and 210 are, for example, signals from upper bits. Selector 201 to Selector 202 and Selector 202 to Selector 203
The through signal 21 that is transmitted without shifting.
4 and 215 are propagated.

Further, the selector 201 outputs a signal 211 that is the same as the input signal 204 and is shifted by 4 bits, and the selector 202 is the same as the through signal 214 and a signal 212 that is shifted by 2 bits. The same as the through signal 215, a signal 213 that shifts by 1 bit is output. The output signal 216 is output from the selector 203. Signals 211, 21
2 and 213 are output in the lower bit direction, for example.

When the input signal 204 is transmitted without being shifted, the input signal 204 and the output signal 21 are transmitted.
The selectors 201 and 2 are arranged so that the input / output direction of 6 and the propagation direction of the through signals 214 and 215 are perpendicular to each other.
03 is arranged.

As a result, the layout area of the selectors 201 to 203 of the shift circuit shown in FIGS. 7A and 7B can be reduced and high-speed operation can be achieved.

As another example, a shift circuit having a multi-stage selector type shifter and a matrix type shifter for varying the data shift amount and shifting the data only in one direction is disclosed in Japanese Patent Laid-Open No. 3-157719. It is disclosed. The shift circuit is shown in FIGS. 8 (a) and 8 (b).

FIG. 8A is a principle diagram of the shift circuit disclosed in Japanese Patent Laid-Open No. 3-157719. Figure 8
The shift circuit shown in (a) is a multi-stage selector type shifter 30.
1 and a matrix type shifter 302. The multi-stage selector type shifter 301 responds to the data D having a length of 2 ⁿ bits (n is a natural number), and the matrix type shifter 302
Responds to the output data of the multi-stage selector shifter 301.

FIG. 8B is a block diagram showing a specific structure of the shift circuit shown in FIG. 8A. Here, the data to be shifted is 2 ⁿ bits, and the shift amount is (2 ⁿ −
1) Bits, and the data shift direction is also one direction.
The portion 301 surrounded by the alternate long and short dash line is shown in FIG.
The multi-stage selector type shifter 301 of FIG.
Corresponds to 02.

The shift circuit shown in FIG. 8B has two inputs and one input.
Multi-stage selector type shifter 301 having built-in output type selectors 311 to 316, and matrix type shifter 3
It has a matrix type shifter 302 having 21 to 324 built therein.

The register 326 has a data shift amount (=
(2 ⁿ -1) bits are stored in the register 326.
The signal indicating the shift amount output from the selector 3 is input to the decoder / multiplexer 327, restored and selected in the decoder / multiplexer 327, and used as the shift control signals SC1 and SC2.
11 to 316 and the shifters 321 to 324, respectively.

The register 310 stores 2 ⁿ bits of data before shifting and outputs 2 ^{n -1} bits of data to the selector 311. The selector 311 has a function of 2 ^n-1 bit shift data 2 ^n-1 bit length in response to a shift control signal SC1 output from the decoder and multiplexer 327. Selector 312
Operates in cooperation with the selector 311 and, similarly to the selector 311, responds to the shift control signal SC1 and manipulates data of 2 ^n- bit length as a whole. The selector 313 receives the data of 2 ^n-2 bit length from the selector 311 and responds to the shift control signal SC1 with the data of 2 ^n-2 bit length.
^It has the function of shifting by ^n-2 bits. Selector 3
14 to 316 have the same function as the selector 313, and cooperate with the selector 313 to operate the shift control signal S.
In response to C1, it manipulates data of 2 ⁿ bit length as a whole.

The shifter 321 has two selectors 313 to 2
A shift control signal SC2 that receives data of ^n-2 bit length and is output from the decoder and multiplexer 327
In response to the above, it has a function of shifting data of 2 ^n-2 bits in length by 2 ^n-2 bits. The shifters 322 to 324 have the same function as that of the shifter 321.
The data of 2 ^n-2 bit length output from ˜316 is received.

The register 325 has shifters 321 to 324.
Stores the shifted data output from. Shifter 3
In each of 21 to 324, the data of 2 ^n-2 bit length discharged to the outside of the output range is merged with the output of the corresponding adjacent shifter through the bus.

As described above, in the shift circuits shown in FIGS. 8A and 8B, first, in the multi-stage selector type shifter 301, the shift represented by the geometric series of 2 with respect to the data of 2 ⁿ bit length. Of the amount, the upper part with the largest amount of data shift, that is, 2 ^n-1 bit length data and 2 ^n-2
Bit-length data is shifted in response to the shift control signal SC1. Next, in the matrix type shifter 302, the remaining lower part of the data shift amount which is smaller is shifted in response to the shift control signal SC2. This is advantageous in terms of both circuit scale and delay speed.

As still another example, a register capable of storing 2n-bit length data for n-bit length data is prepared, the bit is shifted according to the required shift amount, and the data is stored in the register. A shift circuit that changes the amount of data shift by writing and reading the data and shifts the data in only one direction is disclosed in Japanese Patent Application No. Hei 5 (1999) -135242.
No. 165602. The configuration of the shift circuit is shown in FIG.

The shift circuit shown in FIG. 9 has an input selector 4
01 and a cell array 402. The input selector 401 includes a selector 401L and a selector 401R.
The selector 401L holds the n-bit data A given from the outside, and gives the held data A to the cell array 402. The selector 401R selectively selects and holds the n-bit data A or the n-bit data B supplied from the outside similarly to the data A, and supplies the held data A or data B to the cell array 2.

The cell array 402 has a plurality of shift cells 402a, 4a, 4b depending on the bit length of the data A or the data B.
02b, 402c, ... Are cascade-connected. The shift cells 402a, 402b, 402c ... Are on the left side of the shift cells 402aL, 402bL, 402cL.
And the right shift cells 402aR, 402bR, 402
cR ... And each shift cell is composed of a selector group that shifts data by selecting the data of the shift cell in the previous stage.

As described above, in the shift circuit shown in FIG. 9, for example, in the shift cell 402a, the left shift cell 40 is
2aL shifts a predetermined amount of input data according to the shift control signal aL. Left shift cell 402aL
The shift cell 402aR on the right side connected to the shift cell 402aL on the left side according to the shift control signal aR.
Independently of, a predetermined amount of input data is shifted, and the data to be shifted out is shifted into the left shift cell 402aL. Similarly, by the shift cells 402b, 402c ... Cascaded to the shift cell 402a,
Shift-out and shift-in can be repeated to shift input data by a plurality of bits.

As a result, in the shift circuit shown in FIG. 9, the circuit structure can be downsized, the data array adjustment can be simplified and the processing speed can be improved during the shift operation.

[0025]

However, in each of the shift circuits disclosed in the above-mentioned publications, the data is shifted in one direction, so that the data can be transmitted in any direction, that is, in the upper bit direction or the lower bit direction. You cannot shift in the direction. For this reason, when shifting the data in the opposite direction to the normal direction, it is necessary to change the data bit string by software and then perform the shift to change the data bit string again.
Therefore, in the shift circuit described above, when an arbitrary shift amount is shifted with respect to the input data, since the shift direction is one direction, the time required for the calculation by the software processing is also required, and the process for shifting the input data is performed. May reduce speed.

The present invention solves such a problem, and an object thereof is to provide a shifter circuit in which a shift direction can be arbitrarily set and a processing speed is improved in a predetermined bit shift of input data. It is in.

[0027]

The shift circuit of the present invention comprises:
In a shift circuit that outputs input bit data, the shift control circuit includes at least one barrel shifter set to a different shift amount with respect to the input bit data, and a shift control circuit that controls a shift operation of the barrel shifter. The barrel shifter is controlled so that the shift direction of the input bit data is set to the same arbitrary direction, and the shift amount is shifted with respect to the input bit data. Is achieved.

Further, preferably, in the shift circuit of the present invention, the shift control circuit generates a shift control signal by an input bit string signal input from the outside, controls the barrel shifter based on the shift control signal, and inputs the bit shift signal. An arbitrary shift direction of data is set, and an arbitrary shift amount is shifted.

Further, preferably, in the shift circuit of the present invention, the shift control signal has an arbitrary shift direction and an arbitrary shift amount determined by a bit value of a specific bit in the bit string of the input bit string signal. Whether the barrel shifter shifts or not is determined by the bit value of another specific portion.

Further, preferably, in the shift circuit of the present invention, the specific bit of the input bit string signal is the most significant bit or the least significant bit.

Further preferably, in the shift circuit of the present invention, the barrel shifter, based on the shift control signal, shifts the input bit data to "upper bit direction" and "lower bit direction shift". "When,
One of the three operations of "no shift" is performed.

Further preferably, in the shift circuit of the present invention, the barrel shifter has a maximum shift amount (m / 2 bits, m = 2 ⁿ : n is an integer of 1 or more), and the shift amount is 1/2. Barrel shifters that decrease bit by bit are arranged in order, and finally, the barrel shifters are arranged so that the shift amount is 1 bit.

Further, preferably, in the shift circuit of the present invention, each barrel shifter is connected to a data selection means, and the data selection means is configured to output data based on a selection signal generated by the input bit string signal in the shift control circuit. Is output.

The operation of the above structure will be described below.

In the shift circuit of the present invention, when shifting the input bit data, the shift control circuit is controlled based on the shift control signal generated by the shift control circuit by the input bit string signal externally input to the shift control circuit. By controlling each barrel shifter, the shift direction of the input bit data and the presence / absence of the shift operation are determined, and the shift operation for the input bit data is executed. At this time, the shift direction of the input bit data is set to an arbitrary same direction and an arbitrary shift amount is shifted, so that the processing speed of the shift circuit can be improved.

Further, the shift direction and the shift amount in shifting the input bit data are changed by an input bit string signal input from the outside, which requires a calculation time by software processing when shifting the input bit data as in the conventional case. Therefore, the processing speed can be further improved.

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a specific example of the shift circuit according to the embodiment of the present invention. The shift circuit 10 shown in FIG. 1 includes a shift control circuit 11 for generating a shift control signal for controlling a data shift amount and a shift direction, and an arbitrarily set bit length (1 bit or more) of data. A barrel shifter block 12 having a plurality of barrel shifters 12a, 12b, 12c, 12d, ... Which can be shifted in a shift direction (upper bit direction or lower bit direction) is provided. In the shift control circuit 11, when various data and shift control command data including information on the shift amount and shift direction of the data are transmitted from an external processor or the like via the bus line 16, it is an input bit string signal. The shift control command data is received and a shift control signal for controlling the operation of the barrel shifter block 12 is generated. Then, the barrel shifter block 12 receives the shift control signal from the shift control circuit 11, and based on the shift control signal, executes the shift amount of an arbitrary bit length and the arbitrary shift direction for the input m-bit data. To do.

The shift control circuit 11 uses the m-bit data,
The shift control command data is received from the bus line 16 that transmits the shift control command data and the like. Shift control circuit 11
Is a first data register 13 having a data holding function.
Then, a register write signal is output. The first data register 13 to which the register write signal is input receives m-bit data (m = 2 ⁿ ) which is shift input data for the barrel shifter block 12 from the bus line 16 and outputs m
Holds bit data. The m-bit data is source data before being shifted by the barrel shifter block 12.
Further, the shift control circuit 11 outputs a shift input latch signal to the barrel shifter block 12. When the shift input latch signal is input, the barrel shifter block 12
Receives and latches m-bit data which is shift input data from the first data register 13. The barrel shifter block 12 that has received the m-bit data arbitrarily selects the input m-bit data at each barrel shifter 12a, 12b, 12c, 12d ... Based on the shift control signal from the shift control circuit 11. Shift direction and a predetermined shift amount are executed.

Each barrel shifter 12a, 12b, 12c,
12d ..., the first barrel shifter 12a having the largest shift amount is arranged on the input side of the barrel shifter block 12, and hereinafter, the second barrel shifter 12b, the third barrel shifter 12c, the fourth barrel shifter 12d ... Are arranged in ascending order, and the barrel shifter with the smallest shift amount is arranged on the output side of the barrel shifter block 12.

The first barrel shifter 12a performs a shift amount of m / 2 bits in either the upper bit direction or the lower bit direction. Hereinafter, such shift is referred to as ± (m / 2) bit shift. The + sign indicating the shift direction indicates a shift in the upper bit direction, and the − sign indicates a shift in the lower bit direction. The second barrel shifter 12b is ±
(M / 4) bit shift, the third barrel shifter 12c
The ± (m / 8) bit shift and the fourth barrel shifter 12d perform ± (m / 16) bit shift. In this way, each barrel shifter executes a shift amount of (1/2) times the shift amount of the barrel shifter adjacent to the input side thereof.

Each barrel shifter 12a, 12b, 12c,
12d ... is the first barrel shifter 1 having the largest shift amount for performing ± (m / 2) bit shift.
The second barrel shifters 12b, ± (m) that operate from 2a and then operate in the order of decreasing shift amount, and that perform ± (m / 4) bit shift subsequent to the first barrel shifter 12a.
/ 8) Third barrel shifter 12 for performing bit shift
The fourth barrel shifter 12d ... That performs c, ± (m / 16) bit shift operates. In this case, all barrel shifters each operate to perform a bit shift in the same direction.

In this way, the barrel shifter block 1
After the bit shift of the m-bit data in 2 is completed, the shifted m-bit data is transferred to the barrel shifter block 1
2 is output to the data selector 14, which is a data selection unit. Based on the shift output selector signal of the selection signal output from the shift control circuit 11 to the data selector 14, the shifted m-bit data is output to the data selector 1
The data is selected at 4, output to the second data register 15, and held in the second data register 15.

With such a configuration, the shift circuit 10 can shift the input m-bit data by a designated bit length in an arbitrary shift direction and does not require software processing at the time of shifting. The processing speed can be increased.

Here, data handled by a computer or the like is usually a power of 2 bit length data such as 8 (2 ³ ) bits or 16 (2 ⁴ ) bits. 2 like this
The exponentiation bit length data is transmitted to the shift circuit 10 via the bus lines 16 of the data bus and the address bus, and the instruction operation from the computer or the like is executed. The data transmitted to the bus line 16 is shift instruction data, shift amount data, and shift data in the data bus, and the register address data and data for shifting the barrel shifter block 12 are held in the address bus. Register address data of the latch register to

FIG. 2 is a block diagram of the shift control circuit 11 provided in the shift circuit 10 of the present invention. The shift control circuit 11 selects a register write signal generation block 11a that generates a register write signal by a data signal (input bit string signal) from a data bus that is a bus line 16 and shift output data that is shifted m-bit data. Shift output selector signal generation block 11b for generating a shift output selector signal for
And a shift input latch signal generation block 11 for generating a shift input latch signal for latching source data (shift input data) which is m-bit data before shifting.
c and a barrel shifter operation selection signal generation block that generates a barrel shifter operation selection signal for performing the shift operation (shift to the upper bit direction, shift to the lower bit direction, or output as is without shifting) 11d and.

FIG. 3 is a block diagram for explaining the operating state of the shift control circuit 11.

The shift control circuit 11 receives the data bus signal from the data bus 16a and the address bus 1 as input signals.
The address bus signal and the latch pulse signal from 6b are input. When these input signals are input to the register write signal generation block 11a, the register write signal generation block 11a detects the address of the first data register 13 by the address bus signal and the first data register 13 by the data bus signal. A register write command to the register is detected, and then a register write signal is generated by the pulse signal for latching.

Similarly, the shift output selector signal generation block 11b detects the address of the data selector 14 by the address bus signal, detects the shift output selector instruction to the data selector 14 by the data bus signal, and then the latch pulse. A shift output selector signal is generated by the signal.

Shift input latch signal generation block 11c
Detects an address of shift data latch registers 12e and 12f in a barrel shifter block 12 described later by an address bus signal, detects a shift input latch instruction to shift data latch registers 12e and 12f by a data bus signal, and then latches The shift input latch signal is generated by the use pulse signal.

Barrel shifter operation selection signal generation block 1
1d detects an address of a barrel shifter unit 12g in a barrel shifter block 12 described later by an address bus signal, detects a barrel shifter operation selection command to the barrel shifter unit 12g by a data bus signal, and then selects a barrel shifter operation selection by a latch pulse signal. Generate a signal.

As a result, the shift control circuit 11 selects the register write signal output to the first data register 13 as an output signal and the shift output data output to the data selector 14 for selecting the shift output data after the shift is completed. Then, a shift input latch signal to the shift data latch registers 12e and 12f in the barrel shifter block 12 and a barrel shifter operation selection signal for selecting a shift operation to the barrel shifter unit 12g in the barrel shifter block 12 are output.

The shift control circuit 11 receives shift control command data, which is a data bus signal, from the data bus 16a forming the bus line 16. Shift control circuit 11
When confirming that the shift control instruction data matches the content of the predetermined bit shift, the register write signal generation block 11a generates a register write signal and outputs the register write signal to the first data register 13. The first data register 13 receives and holds the m-bit data, which is the source data before shifting, from the data bus 16a based on the register write signal.

Next, the shift control circuit 11 generates a shift output selector signal in the shift output selector signal generation block 11b and outputs the shift output selector signal to the data selector 14.

Next, the shift control circuit 11 generates a shift input latch signal in the shift input latch signal generation block 11c and outputs the shift input latch signal to the barrel shifter block 12. The barrel shifter block 12 receives m-bit data which is source data (shift input data) before shifting from the first data register 13 based on the shift input latch signal from the shift control circuit 11.

Next, the shift control circuit 11 generates a barrel shifter operation selection signal in the barrel shifter operation selection signal generation block 11d and outputs the barrel shifter operation selection signal to the barrel shifter block 12. The barrel shifter block 12 performs a predetermined shift direction and shift amount shift on the pre-shift m-bit data based on the barrel shifter operation selection signal from the shift control circuit 11.

FIG. 4 is a timing chart of the register write signal, shift output selector signal, shift input latch signal, and barrel shifter operation selection signal output from the shift control circuit 11.

The latching pulse signal has a predetermined pulse width and a predetermined period, and is used for the address bus 16b and the data bus 1.
6a is input so as to correspond to each address signal and command signal. A register write address signal, a shift output selector signal, a shift input latch address signal, and a barrel shifter operation selection address signal are input in time series from the address bus 16b, and the pulse width of each address signal is greater than the pulse width of the latch pulse signal. Is also set long. At the same time, a register write command signal, a shift output selector command signal, a shift input latch command signal, and a barrel shifter operation selection command are sent from the data bus 16a with a pulse width substantially equal to that of each address signal so as to correspond to each address signal. The signals are input in time series.

First, the predetermined pulse states of the register write address signal from the address bus 16b and the register write command signal from the data bus 16a are confirmed, and the command of the register write command signal and the address of the register write address signal are checked. If it is determined that the signal contents of and are correct, the register write signal becomes active (ON) based on the latch pulse signal, and the register write signal is generated. If one of the pulse condition and the signal condition of the register write address signal and the register write command signal does not satisfy the condition, the register write signal becomes inactive (OFF).

The shift output selector signal, the shift input latch signal and the barrel shifter operation selection signal are also generated in the same procedure.

As a result, the output signal from the shift control circuit 11 is first generated as a register write signal, and then sequentially generated as a shift output selector signal, a shift input latch signal, and a barrel shifter operation selection signal.

FIG. 5 is a block diagram of the barrel shifter block 12 provided in the shift circuit 10 of the present invention. The barrel shifter block 12 includes a shift data latch register 12e that latches shift input data that is m-bit data before shifting, a shift data latch register 12f that outputs shift output data that is m-bit data after shifting, and actually shifts m bits. Barrel shifter section 12g consisting of multiple barrel shifters for shifting data
Have and.

The barrel shifter unit 12g controls the shift operation and the shift direction of the m-bit data and shifts the m-bit data to the upper bit direction, and the lower bit direction shift circuit to shift the m-bit data to the lower bit direction. It has a bit-direction shift circuit and a non-shift circuit that latches m-bit data as it is without shifting m-bit data.

The barrel shifter block 12 has shift input data, which is m-bit data before shifting, as an input signal, a shift input latch signal for latching the shift input data in the shift data latch register, and a shift operation of the shift input data. A barrel shifter operation selection signal, which is a shift control signal for controlling, is input, and shift output data, which is m-bit data after completion of predetermined bit shift, is output as an output signal.

The barrel shifter block 12 has shift input data, which is a signal from the data bus, and the shift control circuit 1.
The shift input latch signal and the barrel shifter operation selection signal, which are output signals from 1, are input to execute the shift operation. First, the shift control circuit 11 first outputs a register write signal to the first data register 13,
The data register 13 holds shift input data which is a signal from the data bus. Next, the shift control circuit 11 outputs a shift input latch signal to the shift data latch register 12e on the input side of the barrel shifter block 12, and the shift data latch register 12e on the input side outputs the first data register 1 according to the shift input latch signal.
The shift input data held in 3 is received. next,
The barrel shifter operation selection signal for controlling the shift operation and the shift direction is sent from the shift control circuit 11 to the barrel shifter unit 1.
When output to 2g, the barrel shifter unit 12g receives the shift input data latched in the shift data latch register, and based on the barrel shifter operation selection signal, each barrel shifter shifts a predetermined shift amount and shift direction with respect to the shift input data. The operation of is executed.

Usually, the bit shift of the shift input data in the barrel shifter section 12g of the barrel shifter block 12 is, as shown in FIG. 1, from the first barrel shifter 12a having a large shift amount to the fourth barrel shifter 1 having a small shift amount.
It is sequentially executed toward 2d.

For example, when the shift input data is 8-bit data (m = 8), the shift amount is first ± 4 bits (the + sign indicates the shift operation to the higher bit, the − sign indicates the shift operation to the lower bit). ) The shift operation is executed from the barrel shifter. The ± 4 bit barrel shifter is based on the barrel shifter operation selection signal that specifies the shift operation.
Either the "± 4 bit shift operation" or the "no shift operation" is selected and executed.
When "± 4 bit shift operation" is selected, the 8-bit shift input data is input to the +4 bit direction shift circuit or the -4 bit direction shift circuit, and is shifted by 4 bits in the upper bit direction or the lower bit direction. .

When the ± 4 bit shift of the 8-bit shift input data in the barrel shifter with the shift amount of ± 4 bits is completed, the shift amount of the ± 8 bit shift input data is ± 2 bits. , And the 2-bit shift operation is performed in the upper bit direction or the lower bit direction in the ± 2 bit barrel shifter. If "no shift operation" is selected in the shift operation of the barrel shifter with a shift amount of ± 4 bits, 8
The bit shift input data is input to the non-shift circuit, and is sent to the ± 2 bit barrel shifter as it is without being shifted.

Like the ± 4 bit barrel shifter, the ± 2 bit barrel shifter selects either "± 2 bit shift operation" or "no shift operation" based on the barrel shifter operation selection signal designating the shift operation. Select and execute the shift operation. When the shift operation of the 8-bit shift input data by the ± 2 bit barrel shifter is completed, the 8-bit shift input data is sent to the barrel shifter whose shift amount is ± 1 bit.

In the ± 1 bit barrel shifter, the final shift operation is performed on the 8-bit shift input data, similarly to the ± 4 bit barrel shifter and the ± 2 bit barrel shifter.

When the shift operation in the ± 1 bit barrel shifter is completed, the shift control circuit 11 shifts the shift data latch register 1 on the output side of the barrel shifter block 12.
The shift input latch signal is output to 2f, and the 8-bit shift input data shifted by the barrel shifter unit 12g is latched in the shift data latch register 12f. The shifted 8-bit shift input data latched in the shift data latch register 12f is output from the barrel shifter block 12 and input to the data selector 14 as shift output data. Data selector 14
The shift output data input to the shift control circuit 11 is
Is selected on the basis of the shift output selector signal output to the data selector 14, is output to the second data register 15, and is held in the second data register 15.

Here, after the shift operation of the ± 4 bit barrel shifter for the 8-bit shift input data is completed, the subsequent predetermined bit shift is not necessary for the 8-bit shift input data (+4 bit shift). Or -4 bit shift ends), the 8-bit shift input data is not sent to the ± 2 bit barrel shifter.
It is transmitted to the data selector 14 from the 4-bit barrel shifter. The subsequent operation is the same as above. Therefore, an extra shift operation is omitted and the shift operation is simplified.

As a result, the operation of shifting the predetermined bit for the shift input data in the barrel shifter block 12 is completed.

FIG. 6 is a block diagram illustrating a specific operation of the shift circuit 10 of the present invention.

In the present embodiment, 8-bit shift input data is set to "01001101", and this "01001101" is set.
A case of shifting "01" by 5 bits to the upper bits will be described.

The 8-bit data is composed of a bit string of 0th bit to 7th bit, the 0th bit being the least significant bit,
The 7th bit is the most significant bit.

To shift 8-bit data by a predetermined number of bits, three barrel shifters are required. As for the number of barrel shifters, when m of m-bit data satisfies m = 2 ⁿ (m: number of bits), the value of n indicates the number. Therefore, in 8 bits, n = 3 is obtained from 8 = 2 ³ , and the number of barrel shifters is determined.

In 8-bit data, the 7th most significant bit
The bit represents the shift direction, and the second bit, the first bit,
The 3-bit string of 0th bit represents the shift operation. For example, the 7th bit indicates a shift direction of the upper bit by "0" and a shift direction of the lower bit by "1". Also,
In each of the 2nd bit, the 1st bit, and the 0th bit,
"1" indicates that the shift is executed, and "0" indicates that the shift is not performed. Therefore, as shown in FIG. 6, the shift control instruction data for shifting the 8-bit data “01001101” by 5 bits to the upper bits is “0000010”.
1 ”.

First, the shift control circuit 10 receives the shift control command data "00000101" from the data bus 16a constituting the bus line 16, confirms the content of the shift control command data, and then checks the first data register 1
A register write signal is output to 3. Upon receiving the register write signal, the first data register 13 receives the shift input data "01001101" from the data bus 16a and latches the data.

Next, the barrel shifter block 12 receives the shift input data "01001101" in accordance with the shift input latch signal from the shift control circuit 11, and latches the data.

Next, the barrel shifter block 12 receives the barrel shifter operation selection signal which is the shift control signal output from the shift control circuit 11, and the +4 bit barrel shifter 17, the +2 bit barrel shifter 18 and the +1 bit barrel shifter 19 in the barrel shifter block 12 are received. Is
A predetermined bit shift operation is performed based on the barrel shifter operation selection signal. The barrel shifter operation selection signal includes contents based on "00000101" which is shift control instruction data. That is, the most significant first bit is "
It is 0 "and shifts toward the upper bit. Also, the second bit is" 1 ", the +4 (2 ² ) bit barrel shifter 17 shifts, and the first bit is" 0 ", +2.
The (2 ¹ ) bit barrel shifter 18 does not shift, the 0th bit is “1”, and the +1 (2 ⁰ ) bit barrel shifter 19 shifts and shifts by 5 bits in the upper bit direction as a whole.

The +4 bit barrel shifter 17 receives the shift input data "01001101", shifts this data by 4 bits in the upper bit direction, and outputs "11010".
000 "is generated.

Next, the generated 8-bit data "110"
10000 "is from +4 bit barrel shifter 17 to +2
It is sent to the bit barrel shifter 18. Since the +2 bit barrel shifter 18 does not shift the 8-bit data "11010000", the 8-bit data "1"
1010000 ″ is sent to the +1 bit barrel shifter 19 as it is.

The + 1-bit barrel shifter 19 receives the 8-bit data "11010000", shifts this data by 1 bit in the upper bit direction, and outputs "1010000".
0 "is generated.

The 8-bit data “10100000” generated by the + 1-bit barrel shifter 19 is output to the data selector 14 as the shift output data of the barrel shifter block 12.

The shift output data “10100000” input to the data selector 14 is the shift control circuit 1
1 to the second data register 15 selected based on the shift output selector signal output to the data selector 14.
And is held in the second data register 15.

As a result, in the shift circuit 10 shown in FIG. 6, the operation of shifting 5 bits in the upper bit direction with respect to "01001101" of the shift input data is completed. Then, “10100000” of the shift output data which is shifted by 5 bits in the upper bit direction is transmitted to the external processor or the like via the bus line 16.

In this way, the shift circuit 10 of the present invention is
Bus line 1 at a predetermined bit shift of input data
The shift direction can be set to an arbitrary direction based on the shift control command data transmitted via 6, and software processing at the time of predetermined bit shift is unnecessary, so that the processing speed can be improved.

In the present embodiment, the predetermined bit shift of 8-bit data has been described. However, even when the bit string of the shift input data is 128 bits, the number of barrel shifters in the barrel shifter block 12 is increased by 7 (128).
= 2 ⁷ ), the shift circuit 10 having the above contents can be simply obtained.

From the above description, the shift circuit of the present invention is a circuit using a transistor or the like for the shift amount desired by the user, and includes a shift control circuit, a barrel shifter,
A data selector or the like can be configured. For this reason,
Conventionally, software processing is performed to perform a shift operation in an arbitrary direction, but a shift operation in an arbitrary direction can be performed without using software processing, which has an effect of reducing processing time. Moreover, since the circuit for performing the predetermined bit shift is actually composed of the barrel shifter, the shift operation can be speeded up. Furthermore, the barrel shifter is L
Since it can be manufactured in the SI process, it can be made into one chip, and there is an effect that the circuit can be downsized.

[0091]

The shift circuit of the present invention has at least one barrel shifter set to a different shift amount for input bit data, and a shift control circuit for controlling the shift operation of the barrel shifter. The circuit controls the barrel shifter and sets the shift direction of the input bit data so that it is in the same arbitrary direction.
By shifting an arbitrary shift amount with respect to the input bit data, the shift direction can be arbitrarily set and the processing speed can be improved in the predetermined bit shift with respect to the input data.

[Brief description of drawings]

FIG. 1 is a block diagram showing a specific example of a shift circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a shift control circuit provided in the shift circuit of FIG.

FIG. 3 is a block diagram for explaining an operating state of the shift control circuit of FIG.

FIG. 4 is a timing chart of register write signals, shift output selector signals, shift input latch signals, and barrel shifter operation selection signals output from the shift control circuit.

5 is a block diagram of a barrel shifter block provided in the shift circuit of FIG.

FIG. 6 is a block diagram illustrating a specific operation of the shift circuit in FIG.

FIG. 7A is a block diagram of a conventional shift circuit, and FIG. 7B is a configuration diagram of a main part thereof.

FIG. 8A is a principle diagram of another conventional shift circuit, and FIG. 8B is a block diagram of a main part thereof.

FIG. 9 is a configuration diagram of still another conventional shift circuit.

[Explanation of symbols]

10 shift circuits 11 Shift control circuit 11a register write signal generation block 11b Shift output selector signal generation block 11c shift input latch signal generation block 11d Barrel shifter operation selection signal generation block 12 barrel shifter block 12a 1st bit barrel shifter 12b 2nd bit barrel shifter 12c 3rd bit barrel shifter 12d 4th bit barrel shifter 12e Shift data latch register 12f shift data latch register 12g barrel shifter 13 First data register 14 Data selector 15 Second data register 16 bus lines 16a data bus 16b address bus

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masaki Nakamura             22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka             Inside the company F term (reference) 5B022 AA00 BA00 DA01 FA01

Claims (7)

[Claims] 1. A shift circuit for outputting input bit data, comprising at least one barrel shifter set to a different shift amount for the input bit data, and a shift control circuit for controlling a shift operation of the barrel shifter. Then, the shift control circuit controls the barrel shifter to set the shift direction of the input bit data in the same arbitrary direction and shifts the arbitrary shift amount with respect to the input bit data. Shift circuit to let. 2. The shift control circuit generates a shift control signal according to an input bit string signal input from the outside, controls the barrel shifter based on the shift control signal, and shifts the input bit data in an arbitrary shift direction. The shift circuit according to claim 1, wherein the shift circuit is set to shift an arbitrary shift amount. 3. The shift control signal determines the arbitrary shift direction and the arbitrary shift amount according to a bit value of a specific bit in a bit string of the input bit string signal,
The shift circuit according to claim 2, wherein the shift operation of the barrel shifter is determined by a bit value of a specific portion other than the specific bit. 4. The shift circuit according to claim 3, wherein the specific bit of the input bit string signal is the most significant bit or the least significant bit. 5. The barrel shifter, based on the shift control signal, performs a "shift in a higher bit direction", a "shift in a lower bit direction", and "no shift" with respect to a shift operation of the input bit data. The shift circuit according to claim 1, wherein the shift circuit performs any one of three operations. 6. The barrel shifter is arranged such that a barrel shifter having a maximum shift amount (m / 2 bits, m = 2 ⁿ : n is an integer of 1 or more) is sequentially arranged from a barrel shifter having a shift amount reduced by 1/2 bit. The shift circuit according to claim 1, wherein the shift circuit is arranged so that the shift amount is finally a 1-bit barrel shifter. 7. The barrel shifters are each connected to a data selection means, and the data selection means outputs data based on a selection signal generated by an input bit string signal in the previous period in the shift control circuit.
The shift circuit according to.