JPH0573297A - Microcomputer - Google Patents

Abstract

PURPOSE:To make fast a microcomputer while the demand is reduced and a noise is reduced without making fast an action clock. CONSTITUTION:A controller 11 outputs a control signal C1 of an H level when an action clock T1 is an H level and a control signal C2 of an H level when an action clock T1 is an L level. Registers 4 and 6 hold the number of non- operations and the number of operations by a latch control signal LC1 based on the control signal C1 and the action clock T1 and registers 5 and 7 hold the number of non-operations and the number of operations by a latch control signal LC2 based on the control signal C2 and the action clock T1. Selectors 8 and 9 select the registers 5 and 7 when the action clock T1 is an H level and select the registers 4 and 6 when the action clock T1 is the L level. A computing element 10 performs the arithmetic operation based on the number of non-operations and the number of operations inputted from the selectors 8 and 9 and transfers the arithmetic result through a data bus DB3 to a register group 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer. With the recent demand for high speed computer systems, there is a strong demand for high speed microcomputers. In order to speed up the computer, it is indispensable to speed up the operation clock of the oscillator (clock generator), that is, the instruction cycle. However, speeding up the operation clock makes it difficult to manufacture a stable clock generator, and the power consumption of the clock generator. Also increased,
There will be much noise. Therefore, it is desired to increase the speed of the microcomputer while reducing the power consumption and the noise without increasing the operation clock speed.

[0002]

2. Description of the Related Art An outline of a conventional microcomputer 30 is shown in FIG. The controller 31 receives an operation clock T1 output from each oscillator (clock generator) (not shown) every instruction cycle, controls the register group 32, and calculates the operands and the operands respectively in the data bus DB.
1 and DB2, and outputs a control signal C0 in synchronization with the operation clock T1. The operation clock T is set in the operand number register 33 and the operand number register 34.
1 for inputting 1 and the control signal C0 of the controller 31
The D circuits 36 and 37 are connected, the operand number register 33 and the operand number register 34 hold the operand number and the operand number based on the latch control signal LC0 output from the AND circuits 36 and 37, and the retained operand numbers are retained. The calculated number and the calculated number are output to the calculator 35. The calculator 35 is the operand register 33.
Also, the operand and the operation number output from the operation number register 34 are input, a predetermined operation, for example, addition is performed, and the operation result is output to the register group 32 via the data bus DB3.

The execution of the operation in the microcomputer 30 is performed by the data bus D in the instruction cycle before the instruction cycle at the rising edge of the operation clock T1 in each instruction cycle, as shown in FIG.
The data of B1 and DB2 are latched by the operand number register 33 and the operand number register 34, and are arithmetically operated by the arithmetic unit 35, and the new operand number and arithmetic number are transferred to the data buses DB1 and DB2. Therefore, the arithmetic unit 35 is designed to perform one operation during one cycle of the operation clock T1.

[0004]

In the conventional microcomputer 30 described above, since the arithmetic unit 35 operates once during one cycle of the operation clock T1, in order to speed up the microcomputer. The operating clock of the oscillator must be speeded up. However, increasing the operating clock speed makes it difficult to manufacture a stable oscillator, resulting in an increase in power consumption of the oscillator and an increase in noise.

The present invention has been made to solve the above problems, and an object of the present invention is to speed up a microcomputer while reducing power consumption and noise without speeding up an operation clock. To do.

[0006]

In order to achieve the above object, a first aspect of the present invention relates to first and second operand count registers for holding an operand and outputting the held operand, and an operand. And a second for holding the number and outputting the held number of operations
And a first selector for selecting one of the first and second operand numbers and outputting the operand held in the register, and the first or second operand A second selector that selects one of the registers and outputs the number of operations held in that register, an operand to be selected by the first selector, and an number of operations selected by the second selector. An arithmetic unit that inputs and to perform arithmetic operations,
The arithmetic unit is controlled so that the arithmetic operation is performed in the first half and the latter half of the instruction cycle, and the first and second selectors are controlled so that one of the operand number register and the arithmetic number register is selected, respectively. A controller that controls the other operand number register and the operand number register so that the other operand number and operand number that are not selected by the first and second selectors hold another operand number and operand number, respectively. It is configured with.

The second aspect of the present invention is directed to an arithmetic unit for inputting an operand and an arithmetic number to perform arithmetic operation, and first and second units for holding the arithmetic result of the arithmetic unit and outputting the held arithmetic result. The output unit and the arithmetic unit are controlled so that arithmetic operations are performed in the first and second halves of the instruction cycle, respectively, and the first and second units are arranged so that the operation results in the first and second halves of the instruction cycle are held in different output registers. And a controller for controlling the output register of.

[0008]

In the first aspect of the invention, the operand and the operand are transferred to one operand and the operand in the first half and the latter half of the instruction cycle, and at the same time, the other operand and the operand of the other register are transferred. Since the output is selected by the first and second selectors and operated by the arithmetic unit, the arithmetic unit operates twice in one instruction cycle, and the speed of the microcomputer is increased.

In the second aspect of the invention, the arithmetic operation unit executes the arithmetic operation in the first half and the second half of the instruction cycle, and the arithmetic operation results are held in different output registers in the first half and the latter half of the instruction cycle. It is possible to output the results of two calculations, and the microcomputer speed is increased.

[0010]

【Example】

[First Embodiment] A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a microcomputer 1 of this embodiment.
The output side of the register group 2 is connected to the data buses DB1 and DB2 via a plurality of switch buffers 3, and the input side of the register group 2 is connected to the data bus DB3. The data bus DB1 is connected to the first and second operand numbers registers 4 and 5, and the data bus DB2 is connected to the first and second operand numbers registers 6 and 7. AND circuits 12 and 13 are connected to the first and second operand numbers 4 and 5, respectively, and the registers 4 and 5 are based on the latch control signals LC1 and LC2 output from the AND circuits 12 and 13, respectively. Holds the operand. Further, AND circuits 14 and 15 are connected to the first and second operation number registers 6 and 7, respectively, and the respective register 6 and
Reference numeral 7 holds the number of operations based on the latch control signals LC1 and LC2 output from the AND circuits 14 and 15.

A first selector 8 is connected to the first and second operand operand registers 4 and 5, and a second selector 9 is connected to the first and second operand registers 6 and 7. There is. An operation clock T1 (see FIG. 2) output for each instruction cycle from an oscillator (clock generator) not shown is input to the first and second selectors 8 and 9, and the operation clock T1 is supplied to each of the selectors 8 and 9. The second operand number register 5 and the second operand number register 7 are selected in the first half of the H-level instruction cycle, and the first operand number is selected in the latter half of the instruction cycle in which the operation clock T1 is the L level. The register 4 and the first operation number register 6 are selected.

An arithmetic unit 10 is connected to the first and second selectors 8 and 9, and the arithmetic unit 10 arithmetically operates based on the operands and the arithmetic numbers input from the first and second selectors 8 and 9. An operation such as addition is performed, and the operation result is transferred to the register group 2 via the data bus DB3.

The controller 11 uses the operation clock T1.
Is input, and the control signal CB1 which becomes L level when the operation clock T1 is H level and the control signal CB2 which becomes L level when the operation clock T1 is L level are output to each switch buffer 3, and the number of operands and The calculated number is transferred via the data buses DB1 and DB2, respectively. Further, the controller 11 outputs to the arithmetic unit 10 a control signal M1 designating the arithmetic mode when the operation clock T1 is at the H level and the arithmetic mode when the operation clock T1 is at the L level, and the arithmetic unit in one instruction cycle. 10 is made to perform addition processing twice.

Further, the controller 11 uses the operation clock T1.
The control signal C1 which becomes H level when is at H level and the control signal C2 which becomes H level when the operation clock T1 is at L level are output.

The AND circuits 12 and 14 receive the control signal C1 of the controller 11 and the operation clock T1, and when both signals C1 and T1 are at the H level, the latch control signal L is generated.
It outputs C1. Also, AND circuit 1
3 and 15 input the operation clock bar T1 inverted by the inverter 16 and the control signal C2 of the controller 11 and output the latch control signal LC2 when both signals C2 and T1 are at the H level. Is becoming

Therefore, in the microcomputer 1, as shown in FIG. 2, in the first half of each instruction cycle in which the rising edge of the operation clock T1 is input,
First operand number register 4 and first operand number register 6
The operands and operands are stored in
The second operand number register 5 and the second operand number register 7 are selected by the first and second selectors 8 and 9, respectively. Then, the arithmetic unit 10 executes an arithmetic operation based on the operand of the operand register 5 and the operand of the operand register 7.

In the latter half of each instruction cycle when the falling edge of the operation clock T1 is input, the second operand number register 5 and the second operand number register 7 hold the operand number and the operand number, respectively. At the same time, the first and second selectors 8 and 9 select the first operand number register 4 and the first operand number register 6, respectively.
Then, the arithmetic unit 10 executes an arithmetic operation based on the operand of the operand register 4 and the operand of the operand register 6.

As described above, in this embodiment, the operation clock T
Even if 1 is not speeded up, the operation can be performed twice in the first half and the second half of each instruction cycle, and the microcomputer 1 can be speeded up. Also, the operation clock T1
Since it is not necessary to increase the speed, it is possible to reduce power consumption and noise.

[Second Embodiment] Next, a second embodiment will be described with reference to FIGS. FIG. 3 shows a microcomputer 20.
The output side of the register group 2 in this embodiment is connected to the data buses DB1 and DB2, and the input side is connected to the data bus DB3. The arithmetic unit 21 is connected to the data buses DB1 and DB2, and the arithmetic unit 21 performs arithmetic operation, for example addition, on the basis of the operand number A and the arithmetic number B transferred from the register group 2 via both data buses DB1 and DB2. I am supposed to do it.

The controller 26 inputs an operation clock T1 (see FIG. 4) output for each instruction cycle from an oscillator (clock generator) not shown, and the operation mode and the operation clock T1 when the operation clock T1 is at H level.
Control signal M1 designating the operation mode when L is at L level
Is output to the arithmetic unit 21 to cause the arithmetic unit 10 to perform addition processing twice in one instruction cycle.

Further, the controller 26 uses the operation clock T1.
Outputs a control signal CB1 which becomes L level when is at H level, and outputs the operation clock T
When 1 is L level, the control signal CB2 which becomes L level is output to the switch buffer 25. or,
The controller 26 outputs a control signal C1 which becomes H level when the operation clock T1 is H level to the AND circuit 27, and outputs a control signal C2 which becomes H level when the operation clock T1 is L level to the AND circuit 28. It is like this.

The AND circuit 27 inputs the control signal C1 of the controller 26 and the operation clock T1 and outputs both signals C1 and C1.
When both T1 are at the H level, the latch control signal LC1 is set to the first
To the output register 22 of. Further, the AND circuit 28 inputs the operation clock bar T1 inverted by the inverter 29 and the control signal C2 of the controller 26. When both the signals C2 and T1 are at the H level, the latch control signal LC2 is set to the second level. To the output register 23.

First and second output registers 22 and 23 are connected to the output side of the computing unit 21, and each output register 2
2 and 23 are connected to the data bus DB3 via switch buffers 24 and 25, respectively. The first output register 22 receives the latch control signal LC1 from the AND circuit 27.
The second output register 23 holds the calculation result of the calculator 21 based on the
The calculation result of the calculator 21 is held based on C2.

The switch buffer 24 is a controller 26.
When the control signal CB1 input from the
Of the calculation result held in the output register 22 of the switch buffer 25 is transferred to the register group 2 via the data bus DB3, and the switch buffer 25 receives the control signal CB input from the controller 26.
2 is at the L level, the calculation result held in the second output register 23 is transferred to the register group 2 via the data bus DB3.
It is supposed to be transferred to.

Therefore, in the microcomputer 20, as shown in FIG. 4, the arithmetic unit 21 performs two arithmetic operations in the first half and the second half of each instruction cycle in which the rising edge and the falling edge of the operation clock T1 are input. For example, addition is executed.

In the first half of each instruction cycle, the operation result of the arithmetic unit 21 is held in the first output register 22 and the operation result held in the second output register 23 is registered via the data bus DB3. Transferred to group 2. In the latter half of each instruction cycle, the operation result of the arithmetic unit 21 is held in the second output register 23, and the operation result held in the first output register 22 is stored in the register group 2 via the data bus DB3. Transferred.

As described above, also in this embodiment, the operation can be performed twice in the first half and the second half of each instruction cycle without increasing the operation clock T1, and the microcomputer 20 can be increased in speed. Also, the operation clock T
1 does not need to be speeded up, so power consumption and noise can be reduced.

[0029]

As described in detail above, according to the present invention,
There is an excellent effect that the speed of the microcomputer can be increased while reducing the power consumption and the noise without increasing the speed of the operation clock.

[Brief description of drawings]

FIG. 1 is a block diagram showing a microcomputer of a first embodiment.

FIG. 2 is a timing chart showing the operation of the first embodiment.

FIG. 3 is a block diagram showing a microcomputer of a second embodiment.

FIG. 4 is a timing chart showing the operation of the second embodiment.

FIG. 5 is a block diagram showing a conventional microcomputer.

FIG. 6 is a timing chart showing the operation of the conventional example.

[Explanation of symbols]

 4 1st operand number register 5 2nd operand number register 6 1st operand number register 7 2nd operand number register 8 1st selector 9 2nd selector 10, 21 arithmetic unit 11, 26 controller 22 First output register 23 Second output register

Claims (2)

[Claims] 1. A first and second operand number register (4, 5) for holding an operand and outputting the retained operand.
One of the first and second operation number registers (6, 7) that holds the operation number and outputs the held operation number, and either the first or second operand number register (4, 5) To select the first selector (8) for outputting the operand to be held in the register and the first or second operand register (6, 7) to select that register. A second selector (9) for outputting the held operation number, an operand to be selected by the first selector (8) and an operation number selected by the second selector (9) are input. And an arithmetic unit (10) for performing arithmetic operation and an arithmetic unit (10) for performing arithmetic operation in the first half and the latter half of the instruction cycle, and one operand number register and one arithmetic number register are selected respectively. When the first and second selectors (8, 9) are controlled as Moni,
The other operand number register and the operand number so that the other operand number and the operand number register not selected by the first and second selectors (8, 9) hold another operand number and operand number, respectively. Controller for controlling registers (11)
A microcomputer comprising: 2. An arithmetic unit (21) for inputting an operand and an arithmetic number to perform an arithmetic operation, and first and second output registers for retaining an arithmetic result of the arithmetic unit and outputting the retained arithmetic result. (22, 23) and the arithmetic unit (21) is controlled so that arithmetic operations are performed in the first half and the second half of the instruction cycle, respectively, and
A controller (26) for controlling the first and second output registers (22, 23) so that the operation results in the first half and the second half of the instruction cycle are held in different output registers.
A microcomputer comprising: