JPH06314253A - Data transfer circuit - Google Patents

Abstract

PURPOSE:To promote the efficiency of a BUS by transferring data without using the BUS in respect of data transfer between circuits to execute the data transfer frequently. CONSTITUTION:An exclusive data line 6 and a selection circuit 7 are installed in an interval between, for instance, a RAM 1 and an arithmetic circuit 2 where the data transfer is executed frequently. Thus, at the same time as the data transfer from the RAM 1 to the arithmetic circuit 2 is executed, the data transfer can be executed between other units, i.e., a register 3 and the register 4 as well. Besides, at the same time as the data transfer from the RAM 1 to the arithmetic circuit 2 is executed, the result of arithmetic operation can be transferred from the arithmetic circuit 2 to the register 3 or the register 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a data transfer circuit,
In particular, it relates to a data transfer circuit including a dedicated data line and a selection circuit.

[0002]

2. Description of the Related Art Conventionally, a data transfer circuit of this type has a BUS.
It is used for the purpose of transferring the data of the access unit to a plurality of other BUS access units.

FIG. 3 is a block diagram showing an example of a conventional data transfer circuit. RAM1 is a random access memory. The arithmetic circuit 2 is a circuit that performs various arithmetic operations. The registers 3 and 4 are registers for storing data.

Next, the operation will be described. The data output from the RAM 1 is frequently transferred to the arithmetic circuit 2 through the BUS 5. The arithmetic circuit 2 performs various arithmetic operations on the plurality of data and outputs the result of the arithmetic operation to the register 3 through the BUS 5.
Alternatively, it is stored in the register 4. RAM when data is transferred from the arithmetic circuit 2 to the register 3 or the register 4.
1 to suspend the data transfer from 1 to the arithmetic circuit 2 or RA
This is performed after the data transfer from M1 to the arithmetic circuit 2 is completed. Also, when data is transferred from the register 3 to the register 4 via the BUS 5 during data transfer from the RAM 1 to the arithmetic circuit 2, the data transfer from the RAM 1 to the arithmetic circuit 2 is temporarily interrupted or the data is transferred from the RAM 1 to the arithmetic circuit 2. Perform after data transfer is completed.

[0005]

In this conventional data transfer circuit, data transfer between each BUS access unit is performed only by BUS. Therefore, when the data transfer between the first BUS access unit and the second BUS access unit is frequently performed, it is necessary to perform the first B access in order to perform the data transfer between the other BUS access units.
Suspend the data transfer between the US access unit and the second BUS access unit. Or the first BUS
There has been a problem that the data transfer between the access unit and the second BUS access unit must be completed until the data transfer is completed.

[0006]

In order to solve the above-mentioned problems, in the data transfer circuit of the present invention, a first BUS access unit and a second BUS access unit which frequently transfer data are provided between the first BUS access unit and the second BUS access unit. It has a dedicated data line connected to the output of the first BUS access unit, and a selection circuit which outputs the selected data to the second BUS access unit after selecting which of the dedicated data line and the BUS is connected.

[0007]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
RAM1 is a random access memory. The dedicated data line 6 is a dedicated data line for transferring the data of the RAM 1 to the arithmetic circuit 2. The selection circuit 7 is a selection circuit that selects the dedicated data line 6 and the BUS 5. The arithmetic circuit 2 is a circuit that performs various arithmetic operations using the output of the selection circuit 7 as input data. The registers 3 and 4 are registers for storing data.

Next, the operation of FIG. 1 will be described. RAM
When the arithmetic circuit 2 operates on the data of 1, the RAM 1
Is output to the selection circuit 7 through the dedicated data line 6. The selection circuit 7 selects the dedicated data line 6 and outputs the data on the dedicated data line 6 to the arithmetic circuit 2. The arithmetic circuit 2 performs an operation based on the data. At the same time as the data transfer from the RAM 1 to the arithmetic circuit 2, the data transfer between the registers 3 and 4 via the BUS 5 is performed. As an operation other than the above, it is also possible to output the data of the register 3 or the register 4 to the BUS 5 and select the BUS 5 by the selection circuit 7 so that the operation circuit 2 operates the data.

FIG. 2 is a block diagram showing another embodiment of the present invention. In FIG. 2, a dedicated data line 8 different from the dedicated data line 6 is provided. The output of the RAM 1 is input to the selection circuit 7 through the dedicated data line 6. The selection circuit 7 selects the dedicated data line 6 and outputs the data on the dedicated data line 6 to the output circuit 9. At the same time as data transfer from the RAM 1 to the output circuit 9, the arithmetic circuit 2 and the register 3
Data transfer via BUS5 is performed between the two. As an operation other than the above, the data in the RAM 1 is input to the arithmetic circuit 2 via the BUS 5, the arithmetic operation is performed, and the arithmetic result is passed through the exclusive data line 8 and the exclusive data line 8 is selected by the selection circuit 7 to output the data. It is also possible to output to the output circuit 9.

[0010]

As described above, the data transfer circuit according to the present invention includes the first BUS access unit and the second BU.
By having a dedicated data line and a selection circuit between the S access units, data transfer between other BUS access units can be performed without interrupting the data transfer between the first BUS access unit and the second BUS access unit. It Further, since the other BUS access units do not need to wait for data transfer via the BUS until the data transfer between the first BUS access unit and the second BUS access unit is completed, the data transfer which takes 2 steps takes 1 You can do it in steps. Therefore, it has the result that the data transfer amount can be increased up to twice.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 RAM 2 arithmetic circuit 3, 4 register 5 BUS 6, 8 dedicated data line 7 selection circuit 9 output circuit

Claims (1)

[Claims] 1. A first and a second unit interconnected via a bus, a dedicated data line derived separately from the first unit, and data from either the dedicated data line or the bus. And a selection circuit for selectively outputting to two units.