JPH05282161A - Information processor - Google Patents

Abstract

PURPOSE:To easily change an interruption condition for an information proces sor and to stop the processor based upon an internal state. CONSTITUTION:When data stored in the processor and selected by a data selecting part 1 satisfy a condition specified by expected value information set up by an expected value register 3-1 and mask information set up in a mask register 4-1, a data comparator 5-1 outputs a coincidence detection signal. In response to the coincidence detection signal, an interruption generating circuit 11 generates an interruption to a processor and a clock control part 14 stops a clock. When coincidence detection signals are outputted from all data comparators 5-1 to 5-m, an output signal from an AND gate 7 becomes '1', the circuit 11 generates an interruption to the processor and the control part 14 stops the supply of clocks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, it is possible to easily change an interrupt condition for a processor and to stop the information processing apparatus on the condition of an arbitrary state or sequence of hardware. And an information processing device capable of

[0002]

2. Description of the Related Art A conventional information processing apparatus generates an interrupt to a processor when a specific logical condition is detected by hardware. For this reason, it is necessary to change the logic of the hardware when changing the interrupt condition when changing the specifications of the device or when debugging.

Further, in the information processing apparatus, the clock is stopped at the time of a test or the like to stop the operation of the apparatus, but in the conventional information processing apparatus, the program counter of the processor has a predetermined address. When it reaches, the clock is stopped.

[0004]

As described above, in the conventional information processing apparatus, when changing the interrupt condition, it is necessary to change the hardware, so that it is costly and troublesome. There is. In particular,
LS if the interrupt logic is configured inside the LSI
It is necessary to recreate I, which is very costly and troublesome.

Further, since the conventional information processing apparatus stops the clock when the value of the program counter reaches a predetermined address, the program can be debugged efficiently, but it is directly related to the program. There is a problem that it is difficult to test the hardware efficiently because the clock cannot be stopped based on the hardware state or sequence.

An object of the present invention is to provide an information processing apparatus capable of easily changing an interrupt condition for a processor and stopping hardware on condition of an arbitrary state or sequence.

[0007]

According to the present invention, the state of a device which is an interrupt condition can be easily changed.
(A) A data select unit in which output data of each unit of the information processing apparatus is collected by n bits and a plurality of data input units are input;
A first expected value register in which expected value information of bit configuration is set, a first mask register in which mask information of n bit configuration is set, and data of n bit configuration selected by the data select unit, The expected value information of n-bit configuration set in the first expected value register and the first expected value information
Request signal output means for outputting a request signal and a request signal is output from the request signal output means when the condition indicated by the mask information of n-bit configuration set in the mask register is satisfied. Thus, an interrupt generation circuit for interrupting the processor is provided.

Further, according to the present invention, in order to enable the information processing device to be in a freeze state when a specific part of the information processing device is in a specific state, (B) the output data of each part of the information processing device is n bits. A data select unit that receives a plurality of data, a first expected value register in which expected value information having an n-bit configuration is set, and a first mask register in which mask information having an n-bit configuration is set. The data of the n-bit configuration selected by the data select unit is the expected value information of the n-bit configuration set in the first expected value register and the n-bit configuration of the n-bit configuration set in the first mask register. When the condition represented by the mask information is satisfied, a request signal output means for outputting a request signal and a request signal output from the request signal output means are provided. It is provided with a clock control unit that stops the clock.

Further, according to the present invention, the sequence as the interrupt condition can be easily changed, and the device can be put into the freeze state when the device performs a specific sequence. Therefore, (A), (B) In addition to the configuration of (C)
The second to mth expected value registers in which the expected value information of the n-bit configuration is set, the second to mth mask registers in which the mask information of the n-bit configuration is set, and the data selection unit output. First to (m-1) th data holding registers for sequentially shifting data having an n-bit structure are provided, and the request signal output means outputs the data having an n-bit structure output from the data select unit as the first data. Satisfying the conditions indicated by the expected value information of the n-bit configuration set in the expected value register and the mask information of the n-bit configuration set in the first mask register,
In addition, the n-bit structured data held in the first to (m-1) th data holding registers and the n-bit structured expected value information set in the second to m-th expected value registers and the When the condition indicated by the mask information having the n-bit configuration set in the second to mth mask registers is satisfied, the request signal is output.

[0010]

In the configuration (A), the n-bit configuration data selected by the data select section is set in the n-bit configuration expected value information set in the first expected value register and the mask register. The request signal output means outputs the request signal when the condition represented by the mask information having the n-bit structure is satisfied. This causes the interrupt generation circuit to interrupt the processor.

In the configuration (B), the n-bit configuration data selected by the data select section is set in the n-bit configuration expected value information set in the first expected value register and the mask register. The request signal output means outputs the request signal when the condition represented by the mask information having the n-bit structure is satisfied. As a result, the clock control unit stops the clock.

In the configuration of (C), the n-bit configuration expected value information and the first mask register in which the n-bit configuration data output from the data select section is set in the first expected value register. Which satisfies the condition indicated by the mask information of the n-bit configuration set in the above, and the data of the n-bit configuration held in the first to (m-1) th data holding registers is Expected value information of n-bit configuration set in the m-th expected value register and n set in the second to m-th mask registers
The request signal output means outputs a request signal when the condition indicated by the mask information of the bit structure is satisfied. As a result, the interrupt generation circuit interrupts the processor, and the clock controller stops the clock.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a data selection section 1, a data selection register 2 and
m expected value registers 3-1 to 3-m, m mask registers 4-1 to 4-m, and m data comparison circuits 5-
1-5-m and (m-1) data holding registers 6-
1 to 6- (m-1) and AND gates 7, 10, 13
, Mode selector 8, interrupt enable register 9,
Interrupt generation circuit 11 and freeze enable register 12
And a clock control unit 14.

A plurality of pieces of output data from the internal registers, arithmetic circuits, logic circuits, etc. of the information processing apparatus are collected in n-bit units and input to the data selection unit 1. Then, the data selection unit 1 responds to the value of the data selection register 2 by
One of a plurality of input n-bit data is selected.

Expected value information having an n-bit structure is set in each expected value register 3-1 to 3-m.

Mask information having an n-bit structure is set in each of the mask registers 4-1 to 4-m. In the present embodiment, "0" indicates the mask.

Data holding registers 6-1 to 6- (m-
In 1), the data of the n-bit structure output from the data selection unit 1 is sequentially shifted in synchronization with the clock in synchronization with the clock.

In the data comparison circuit 5-1, the data of the n-bit structure selected by the data selector 1, the expected value information of the n-bit structure set in the expected value register 3-1, and the mask register 4-. The mask information having the n-bit configuration set to 1 is input.

Then, the data comparison circuit 5-1 corresponds to the bit (n bits of the data selected by the data selector 1 and the n bits of the expected value information set in the expected value register 3-1). However, all the bits are compared by comparing with a bit instructed to be masked by the mask information set in the mask register 4-1 (ie, a bit in which the corresponding mask information is “0”). Match, at least one bit matches, or an odd number of bits match,
The coincidence detection signal which is the output signal is set to "1". still,
In what case the coincidence detection signal is set to "1" is determined by the operator's instruction.

FIG. 2 is a block diagram showing a configuration example of the data comparison circuit 5-1. The n number of coincidence detection circuits 21-1 and 21-2.
1-n and n AND gates 22-1 to 22-n, 2
4-1 to 24-n, 25-1 to 25-n, n gate circuits 23-1 to 23-n, an AND circuit 26, an OR circuit 27, and an exclusive OR circuit 28. , A logical operation circuit 29, a selector 30, a NOR gate 31, and OR gates 32 to 34.

The coincidence detection circuits 21-1 to 21-n are set in the data R (1) to R (n) of the n-bit configuration selected by the data selector 1 and n set in the expected value register 3-1. Bit configuration expected value information E (1) to E
When the corresponding bit with (n) matches, the output signal is set to "1".

The AND gates 22-1 to 22-n respectively output signals from the coincidence detection circuits 21-1 to 21-n and mask information M (1) to M having an n-bit configuration set in the mask register 4-1. Logically AND corresponding bit with (n).

Each of the gate circuits 23-1 to 23-n has a logic of an inversion of mask information M (1) to M (n) having n bits and an output signal of the AND gates 22-1 to 22-n. Take the sum.

The AND gates 24-1 to 24-n respectively AND the corresponding bits of the output signals of the AND gates 22-1 to 22-n and the mask information M (1) to M (n) having an n-bit structure. Take

The AND gates 25-1 to 25-n respectively AND the corresponding bits of the output signals of the AND gates 22-1 to 22-n and the mask information M (1) to M (n) having an n-bit structure. Take

The AND circuit 26 includes gate circuits 23-1 and 23-2.
The logical product of the output signals of 3-n is calculated.

The OR circuit 27 includes AND gates 24-1 to 24-1.
Take the logical sum of the output signals of 24-n.

The exclusive OR circuit 28 is an AND gate 25.
Exclusive-OR the output signals of -1 to 25-n.

The logical operation circuit 29 includes the above-mentioned circuits 26 to 26.
A logical operation different from 28 is performed.

The NOR gate 31 has mask information M (1) to M (n) of n-bit configuration set in the mask register 4-1.
When (n) is all "0", that is, when masking is instructed for all bits, the output signal is set to "1".

The OR gates 32 to 34 take the logical product of the output signal of the NOR gate 31 and the output signals of the logical sum circuit 27, the exclusive logical sum circuit 28, and the logical operation circuit 29.

The selector 30 selects one of the output signals of the AND circuit 26 or gates 32 to 34.

The data comparison circuits 5-2 to 5-m also have the same configuration as the data comparison circuit 5-1 and n bits held in the data holding registers 6-1 to 6- (m-1), respectively. Configuration data, expected value information of n-bit configuration set in expected value registers 3-2 to 3-m, and mask information of n-bit configuration set in mask registers 4-2 to 4-m. Enter.

The AND gate 7 serves as each data comparison circuit 5-1.
The logical product of the coincidence detection signals output from ~ 5-m is calculated.

The mode selector 8 selects one of the output signal of the AND gate 7 and the coincidence detection signal output from the data comparison circuit 5-1.

The interrupt enable register 9 is AND gate 1
By controlling 0, it is controlled whether or not the output signal of the mode selector 8 is supplied to the interrupt generation circuit 11.

The interrupt generation circuit 11 is an AND gate 10.
When the signal from is added, an interrupt request is output to the processor while arbitrating with other interrupt factors.

The freeze permission register 12 controls the AND gate 13 to control whether or not the output signal of the mode selector 8 is supplied to the clock controller 14.

The clock control unit 14 collectively manages the clock inside the device, and when the signal from the AND gate 13 is applied, the clock supplied to the register inside the device is stopped and the device is brought into a frozen state. ..

The data selection register 2, the expected value registers 3-1 to 3-m, the mask registers 4-1 to 4-m, the interrupt enable register 9, the freeze enable register 12, the mode selector 8, The selector 30 is controlled by a processor (not shown) or a diagnostic control unit according to an instruction given by an operator using a keyboard or the like.

Next, the operation of this embodiment will be described.

First, a method of setting an interrupt condition for the processor will be described.

When the operator sets the interrupt condition for the processor, first, the operator sets a mode (mode A) in which an interrupt is generated when a specific part of the device enters a specific state, or the specific part is specified. When a sequence (1) is performed, a mode instruction for instructing whether to set the mode for generating an interrupt (mode B) is input from a keyboard (not shown) or the like.

The processor selects the mode A according to the mode instruction.
When it is instructed to switch to mode B, the mode selector 8 is caused to select the coincidence detection signal output from the data comparison circuit 5-1. When it is instructed to switch to mode B, the mode selector 8 outputs the output of the AND gate 7. Select a signal.

Next, the operator inputs a data selection instruction for selecting one of a plurality of n-bit structured data input to the data selection section 1 from a keyboard or the like.

When the data selection instruction is input, the processor sets the corresponding value in the data selection register 2. As a result, the data selection unit 1 selects the data selected by the data selection instruction from among the input data of a plurality of n bits.

Thereafter, when the operator is instructing the mode A, the expected value information of the n-bit configuration and the mask register 4 to be set in the expected value register 3-1 from the keyboard or the like.
Input the mask information of n-bit configuration set to -1.

As a result, the processor sets the input expected value information and mask information in the expected value register 3-1 and the mask register 4-1.

After that, the operator uses the AND circuit 26 and the OR gates 32 to 3 in the selector 30 in the data comparison circuit 5-1.
A selection instruction for instructing which of the four output signals should be selected is input.

For example, a bit (mask register 4-1) to be compared with the n-bit structured data output from the data selector 1 and the n-bit structured expected value information set in the expected value register 3-1. If the comparison match signal output from the data comparison circuit 5-1 is to be "1" when all the bits that are not masked by the mask information set in 1) match, the output of the AND circuit 26 A selection instruction for selecting a signal, and a comparison instruction for selecting the output signal of the OR gate 32 when it is desired to set the comparison match signal to “1” when at least one bit matches,
The comparison match signal is set to "1" when an odd number of bits match.
If desired, the selection instruction for selecting the output signal of the OR gate 33 is input.

When the selection instruction is input, the processor causes the selector 30 to select one of the output signals of the AND circuit 26 and the OR gates 32 to 34 according to the selection instruction.

When the mode B is instructed, the operator has a sequence of j (2.ltoreq.j.ltoreq.m) clocks,
That is, if the continuous j-clock state is set as the interrupt condition, the expected value information of n-bit configuration to be set in the j expected value registers 3-1 to 3-j is input from the j keyboard and the like. The mask information of n-bit configuration set in each mask register 4-1 to 4-m is input from m keyboards or the like. However, in this case, the mask register 3-
The mask information to be set to (j + 1) to 3-m is set so that all bits indicate a mask, that is, "0".

As a result, the processor outputs the expected value information for the expected value registers 3-1 to 3-j and the mask information to the mask registers 4-1 to 4-m, which are input, to the expected value registers 3-1 to 3-j, Mask registers 4-1 to 4-m
Set to.

After that, the operator operates each data comparison circuit 5-1.
Input a selection instruction for ~ 5-j from a keyboard or the like.

As a result, the processor causes the selector 30 in each of the data comparison circuits 5-1 to 5-j to cause the AND circuit 26,
Select one of the output signals of the OR gates 32-34.

In the case of permitting the interrupt according to the interrupt condition set as described above, the operator inputs the interrupt permission instruction from the keyboard or the like.

As a result, the processor sets "1" in the interrupt enable register 9 to enable the interrupt.

Thereafter, when mode A is set, the following operation is performed.

The data select section 1 selects one of a plurality of data of n-bit configuration sequentially output from each section of the device in synchronization with the clock according to the value of the data selection register 2.

The data of the n-bit structure selected by the data selector 1 is added to the data comparison circuit 5-1.

A data comparison circuit 5 having the structure shown in FIG.
The match detection circuits 21-1 to 21-n in -1 are the data R (1) to n (n) of the n-bit configuration selected by the data selector 1.
When R (n) and the expected value information E (1) to E (n) of the n-bit configuration set in the expected value register 3-1 match, the output signal is set to "1".

The output signals of the coincidence detection circuits 21-1 to 21-n are applied to one input terminal of AND gates 22-1 to 22-n.

Mask information M (1) to M (n) having an n-bit configuration set in the mask register 4-1 is added to the other terminals of the AND gates 22-1 to 22-n. The gates 22-1 to 22-n output the logical product of both.

The output signals of the AND gates 22-1 to 22-n are the one input terminals of the gate circuits 23-1 to 23-n,
It is applied to one input terminal of AND gates 24-1 to 24-n and one input terminal of AND gates 25-1 to 25-n.

Mask information M (1) to M (n) having an n-bit configuration set in the mask register 4-1 is added to the other input terminals of the gate circuits 23-1 to 23-n, The gate circuits 23-1 to 23-n have mask information M
Inversion of (1) to M (n) and AND gate 22
Outputs the logical sum of the output signals of -1 to 22-n.

Therefore, in the output signals of the gate circuits 23-1 to 23-n, when the corresponding data R (1) to R (n) and the expected value information E (1) to E (n) match. And, when the corresponding max information M (1) to M (n) indicates a mask (in the case of "0"), it becomes "1".

The AND circuit 26 includes the gate circuits 23-1 to 23-1.
The logical product of the output signals of 23-n is calculated and output to the selector 30. Therefore, the output signal of the AND circuit 26 excludes the bits designated to be masked by the max information M (1) to M (n), and the data R (1) to R (n) and the expected value information E ( It becomes "1" when all of 1) to E (n) match and when masking of all bits is instructed by the mask information.

The output signals of the AND gates 22-1 to 22-n are applied to one input terminal, and the other input terminal of the AND gates 24-1 to 24-n is set in the mask register 4-1. The mask information M (1) to M (n) having the n-bit configuration is added. Therefore, in the output signals of the AND gates 24-1 to 24-n, the corresponding mask information M (1) to M (n) does not indicate a mask, and the corresponding data R (1) to R (n). And expected value information E
It becomes "1" only when (1) to E (n) match.

The OR circuit 27 includes AND gates 24-1 to 24-1.
Take the logical sum of the output signals of 24-n. Therefore, the output signal of the logical sum circuit 27 is 1 except for the bit instructed to be masked by the mask information M (1) to M (n).
Even in bits, data R (1) to R (n) and expected value information E
It becomes "1" when there is a bit that matches (1) to E (n).

The OR gate 32 takes the logical sum of the output signal of the OR circuit 27 and the output signal of the NOR gate 31. Therefore, the output signal of the OR gate 32 is the mask information M (1)-
There is a bit that matches the data R (1) to R (n) and the expected value information E (1) to E (n) even in one bit except for the bit designated to be masked by M (n). “1” when the masking is performed and when mask information M (1) to M (n) indicates to mask all bits.
become.

The output signals of the AND gates 22-1 to 22-n are applied to one input terminal. The other input terminals of the AND gates 25-1 to 25-n are set in the mask register 4-1. The mask information M (1) to M (n) having the n-bit configuration is added. Therefore, in the output signals of the AND gates 25-1 to 25-n, the corresponding mask information M (1) to M (n) does not indicate the mask, and the corresponding data R (1) to R (n). And expected value information E
It becomes "1" only when (1) to E (n) match.

The exclusive OR circuit 28 is an AND gate 25.
Exclusive-OR the output signals of -1 to 25-n. Therefore, the output signal signal of the exclusive OR circuit 28 is the data R (1) to R (n) and the expected value except for the bits instructed to be masked by the mask information M (1) to M (n). When there is an odd number of bits that match the information E (1) to E (n), the value becomes "1".

The OR gate 33 takes the logical sum of the output signal of the exclusive OR circuit 28 and the output signal of the NOR gate 31. Therefore, the output signal of the OR gate 33 is the mask information M
Bits that match the data R (1) to R (n) and the expected value information E (1) to E (n) except for the bits designated to be masked by (1) to M (n) It becomes "1" when there is an odd number of bits and when the mask information M (1) to M (n) indicates to mask all bits.

The logical operation circuit 29 is an AND gate 22-1.
22-n and the mask information M (1) to M (n) set in the mask register 4-1 are subjected to a predetermined logical operation.

The OR gate 34 takes the logical sum of the output signal of the logical operation circuit 29 and the output signal of the NOR gate 31. Therefore, the output signal of the OR gate 34 is obtained when the output signal of the logical operation circuit 29 is "1" and the mask information M (1) to M (M).
It becomes "1" when it is instructed to mask all bits by (n).

Of the output signals of the AND circuit 26 and the OR gates 32 to 34, the one selected by the selector 30 is output from the data comparison circuit 5-1 as a match detection signal.

Since the mode of the coincidence detection signal output from the data comparison circuit 5-1 is set to the mode A,
It is applied to one terminal of the AND gate 10 via the mode selector 8.

The output signal of the interrupt enable register 9 is added to the other terminal of the AND gate 10, and the content thereof is "1". Therefore, the coincidence detection signal output from the data comparison circuit 5-1. Is set to "1",
The output signal of the AND gate 10 becomes "1". When the output signal of the AND gate 10 becomes "1", the interrupt generation circuit 11 arbitrates with other interrupt factors and interrupts the processor.

Therefore, the n-bit structured data output from the data selection unit 1 is the n-bit structured expected value information set in the expected value register 3-1 and the n-bit structured data set in the mask register 4-1. When the conditions indicated by the bit configuration mask information and the control signal for the selector 30 are met, an interrupt is issued to the processor.

Next, the operation when the mode B is set will be described.

Data holding registers 6-1 to 6- (m-
1) sequentially shifts the data of n-bit configuration, which is sequentially output from the data selection unit 1 in synchronization with the clock, in synchronization with the clock signal.

The data comparison circuit 5-1 outputs the data of the n-bit structure output from the data select section 1, the expected value information of the n-bit structure set in the expected value register 3-1, and the mask register 4-1. The same operation as described above is performed according to the mask information having the n-bit configuration set to 1 and the control signal for the selector 30, and the coincidence detection signal is output.

The remaining data comparison circuits 5-2 to 5-n have n-bit data held in the data holding registers 6-1 to 6- (m-1) and the expected value register 3-2.
Expected value information of n-bit configuration set to 3-m,
Based on the mask information of the n-bit configuration set in the mask registers 4-2 to 4-m and the control signal for the selector 30, the same operation as the data comparison circuit 5-1 is performed and the coincidence detection signal is output. ..

In mode B, as described above, mask information in which all bits are "0" (mask information in which all bits indicate masking) is set in the mask registers 4- (j + 1) to 4-m. Data comparison circuit 5-
The coincidence detection signals output from (j + 1) to 5-m are always "1". That is, when all bits of the mask information are "0", the output signals of the AND circuit 26, the NOR gate 31, and the OR gates 32 to 34 shown in FIG. 2 are all "1", so that the data comparison circuit 5- (j + 1). The coincidence detection signal output from ~ 5-m is always "1".

The AND gate 7 serves as each data comparison circuit 5-1.
The logical product of the coincidence detection signals output from ~ 5-m is calculated.
Therefore, the output signal of the AND gate 7 is the continuous j-clock data output from the data select unit 1.
The expected value information set in the expected value registers 3-1 to 3-j, the mask information set in the mask registers 4-1 to 4-m, and the selector 30 in the data comparison circuits 5-1 to 5-j. It becomes "1" when it matches the condition indicated by the control signal for.

Since the mode of the output signal of the AND gate 7 is set to the mode B, it is applied to one input terminal of the AND gate 10 via the mode selector 8.

The output signal of the interrupt enable register 9 is added to the other terminal of the AND gate 10, and the content thereof is "1". Therefore, the coincidence detection signal output from the data comparison circuit 5-1. Is set to "1",
The output signal of the AND gate 10 becomes "1".

In the same manner as described above, when the output signal of the AND gate 10 becomes "1", the interrupt generation circuit 11 arbitrates with another interrupt factor and interrupts the processor.

Therefore, the continuous j clocks of data output from the data select section 1 are stored in the expected value register 3
The expected value information set in -1 to 3-j, the mask information set in the mask registers 4-1 to 4-j, and the control signal for the selector 30 in the data comparison circuits 5-1 to 5-j. When the conditions shown are met, an interrupt to the processor will occur.

Next, the operation when the clock is stopped to bring the information processing apparatus into the freeze state when a specific portion of the information processing apparatus enters a specific state will be described.

In this case, as described above, the operator selects one of a plurality of n-bit data input to the data select section 1 and a mode instruction for instructing the mode A from the keyboard or the like. Selection instruction for selecting, the expected value of the n-bit configuration set in the expected value register 3-1, the mask information of the n-bit configuration set in the mask register 4-1, and the selector in the data comparison circuit 5-1. Three
A selection instruction for instructing which of the output signals of the AND circuit 26 and the OR gates 32 to 34 should be selected is input to 0.

As a result, the processor sets the mode selector 8 to the state in which the coincidence detection signal which is the output signal of the data comparison circuit 5-1 is selected, sets the value according to the data selection instruction in the data selection register 2, and outputs the expected value. Register 3-1
The expected information of the n-bit configuration input to the mask register 4-1 is set, the mask information of the n-bit configuration input to the mask register 4-1 is set, and the selector 30 is caused to select the output signal of the circuit selected by the selection instruction.

After that, the operator inputs a freeze permission instruction from the keyboard or the like.

As a result, the processor sets "1" in the freeze permission register 12 and permits the device to be frozen by the output signal of the mode selector 8.

Thereafter, the expected value information of the n-bit configuration set in the expected value register 3-1 from the data select section 1, the mask information of the n-bit configuration set in the mask register 4-1 and the data comparison circuit. When n-bit structured data satisfying the condition indicated by the control signal to the selector 30 in 5-1 is output, the coincidence detection signal output from the data comparison circuit 5-1 becomes "1".

In mode A, since the mode selector 8 selects the coincidence detection signal output from the data comparison circuit 5-1, the coincidence detection signal output from the data comparison circuit 5-1 is the AND gate 13 output. It is added to one input terminal.

At this time, since the output signal of the freeze permission register 12 applied to the other input terminal of the AND gate 13 is "1", the coincidence detection signal output from the data comparison circuit 5-1 is By becoming "1",
The output signal of the AND gate 13 becomes "1".

When the output signal of the AND gate 13 becomes "1", the clock control unit 14 stops the clock supplied to the register inside the information processing apparatus and freezes the apparatus.

Therefore, the expected value information of the n-bit configuration set in the expected value register 3-1 from the data select section 1, the mask information of the n-bit configuration set in the mask register 4-1 and the data comparison circuit 5 are provided. N satisfying the condition indicated by the control signal for the selector in -1
When the bit-structured data is output, the information processing device is in a freeze state.

After that, the operator reads the internal state of the information processing apparatus by a shift path (not shown) and uses the read information for the hardware test.

Next, the operation when the clock is stopped to bring the information processing apparatus into the freeze state when the state of the specific portion of the information processing apparatus performs the specific sequence will be described.

In this case, the operator uses a keyboard or the like to instruct the mode to be set to the mode B, and to select one of a plurality of n-bit-structured data input to the data select section 1. Data selection instruction, expected value information of n-bit configuration set in expected value registers 3-1 to 3-j, and mask information set in mask registers 4-1 to 4-m.

As a result, the processor causes the mode selector 8 to select the output signal of the AND gate 7, sets the value according to the data selection instruction in the data selection register 2, and inputs it to the expected value registers 3-1 to 3-j. The set expected value information of the n-bit configuration is set, and the mask information of the n-bit configuration input to the mask registers 4-1 to 4-m is set.

After that, the operator inputs a freeze permission instruction from a keyboard or the like.

As a result, the processor sets "1" in the freeze permission register 12 and permits the information processing apparatus to enter the freeze state by the output signal of the mode selector 8.

After that, the data of the n-bit structure output from the data selection unit 1, the data holding registers 6-1 to 6-1.
The data of n-bit configuration held in 6- (j-1) is the expected value register 3-1 to 3-j, the mask register 4
−1 to 4-m and the condition indicated by the control signal of the selector 30 in each of the data comparison circuits 5-1 to 5-j, that is, the continuous j clocks output from the data select unit 1 are satisfied. When the data of 1) satisfies the above condition, each of the data comparison circuits 5-1 to 5-j sets the coincidence detection signal to "1".

When all the coincidence detection signals output from the j data comparison circuits 5-1 to 5-j become "1", the coincidence detection signals output from the data comparison circuits 5- (j + 1) to 5-m. Is always "1" as described above,
The output signal of the AND gate 7 becomes "1".

In mode B, since the mode selector 8 selects the output signal of the AND gate 7, the output signal of the AND gate 8 is added to one input terminal of the AND gate 13.

At this time, since the output signal of the freeze permission register 12 applied to the other input terminal of the AND gate 13 is "1", the coincidence detection signal output from the data comparison circuit 5-1 is By becoming "1",
The output signal of the AND gate 13 becomes "1".

When the output signal of the AND gate 13 becomes "1", the clock control unit 14 stops the clock supplied to the register inside the information processing device and freezes the device.

Therefore, the continuous j clocks of data output from the data selection unit 1 are transferred to the expected value register 3-.
Expected value information of n-bit configuration set in 1 to 3-j, n set in mask registers 4-1 to 4-m
Bit configuration mask information and data comparison circuits 5-1 to 5-1
When the condition indicated by the control signal for the selector 30 within -j is satisfied, the information processing device enters the freeze state.

[0113]

As described above, according to the present invention, the data of the n-bit structure output from the data select section is the first.
When the condition indicated by the expected value information of the n-bit configuration set in the expected value register and the mask information of the n-bit configuration set in the first mask register is satisfied, Since the interrupt is generated and the contents of the first expected value register and the first mask register can be easily changed, it is possible to easily change the state of the device as an interrupt condition. effective.

Further, according to the present invention, the n-bit structured data output from the data select section is set in the first expected value register and the n-bit structured expected value information and the first mask register. When the condition indicated by the mask information of n-bit structure is satisfied,
Since the clock of the device is stopped, there is an effect that a hardware test or the like can be efficiently performed.

Further, according to the present invention, the n-bit structured data output from the data select section is set in the first expected value register and the n-bit structured expected value information and the first mask register. The condition represented by the mask information of the n-bit structure is satisfied, and the data of the n-bit structure held in the first to (m-1) th data holding registers is the second to mth expected values. Expected value information of n-bit configuration set in the register and the second
~ When the condition indicated by the mask information of the n-bit configuration set in the mth mask register is satisfied, an interrupt is issued to the processor,
Since the clock of the device is stopped, there is an effect that the sequence that becomes the interrupt condition can be easily changed, and an effect that the hardware test and the like can be efficiently performed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a data comparison unit.

[Explanation of symbols]

1 ... Data selection part 2 ... Data selection register 3-1 to 3-m ... Expected value register 4-1 to 4-m ... Mask register 5-1 to 5-m ... Data comparison circuit 6-1 to 6- (m -1) ... Data holding registers 7, 10, 13, 22-1 to 22-n, 24-1 to 24
-N, 25-1 to 25-n ... AND gate 8 ... Mode selector 9 ... Interrupt enable register 11 ... Interrupt generation circuit 12 ... Freeze enable register 14 ... Clock control unit 21-1 to 21-n ... Match detection circuit 23- 1 to 23-n ... Gate circuit 26 ... AND circuit 27 ... OR circuit 28 ... Exclusive OR circuit 29 ... Logical operation circuit 30 ... Selector 31 ... NOR gate 32-34 ... OR gate

Claims (3)

[Claims] 1. A data select unit for inputting a plurality of output data of each unit of the information processing apparatus by n bits, a first expected value register in which expected value information having an n-bit structure is set, and n. A first mask register in which mask information of bit configuration is set, and n-bit configuration expected value information in which the data of n-bit configuration selected by the data selector is set in the first expected value register. And a request signal output means for outputting a request signal when the condition indicated by the mask information of the n-bit configuration set in the first mask register is satisfied, and the request signal output means from the request signal output means. An information processing apparatus comprising: an interrupt generation circuit that interrupts the processor by outputting 2. A data select unit for inputting a plurality of output data of each unit of the information processing apparatus by n bits, a first expected value register in which expected value information having an n-bit configuration is set, and n. A first mask register in which mask information of bit configuration is set, and n-bit configuration expected value information in which the data of n-bit configuration selected by the data selector is set in the first expected value register. And a request signal output means for outputting a request signal when the condition represented by the mask information of n-bit configuration set in the first mask register is satisfied, and the request signal from the request signal output means. An information processing apparatus, comprising: a clock control unit that stops a clock when the clock is output. 3. The second to mth expected value registers in which n-bit expected value information is set, the second to mth mask registers in which n-bit expected mask information is set, and the data select. A first to (m-1) th data holding register that sequentially shifts the data of the n-bit configuration output from the unit, the request signal output unit having the n-bit configuration output from the data select unit. The data satisfies the conditions indicated by the expected value information of the n-bit configuration set in the first expected value register and the mask information of the n-bit configuration set in the first mask register, and The n-bit structured data held in the 1st to (m-1) th data holding registers and the n-bit structured expected value information set in the 2nd to mth expected value registers and the previous 3. The request signal is output when the condition indicated by the mask information of the n-bit configuration set in the second to mth mask registers is satisfied. Information processing device.