JPH10143354A - Dsp, and maximum and minimum value detector suiting it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the detection of the maximum and minimum values efficient in a DSP(digital signal processor), to reduce the number of program steps, and to reduce the power consumption. SOLUTION: The maximum and minimum value detector 20 is provided independently of an arithmetic block which executes processing such as addition, subtraction, sum of product, shift, etc. A controlling part 21 of the detector 20 controls and sets write paths of data and numbers so that the maximum or minimum value may be written to a register R1, the next maximum or minimum value to a register R2, the number of data on the register R1 to a register R3, the number of data on the register R2 to a register R4 respectively by using selectors S1 to S4. A comparator 23 decides the size relation between data of the registers R1 and R2 and data that is inputted through an inputting part 22 and supplies the result to the part 21. Because an operation controlled by the part 21 can be carried out with one piece of data in one basic cycle, processing is further accelerated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a DSP (Digital Signal Processor) architecture.

[0002]

2. Description of the Related Art A DSP generally has a function of repeatedly performing addition, subtraction, multiplication and accumulation, and the like at high speed. However, it is difficult to perform high-speed maximum / minimum value detection processing required in the field of a voice codec or the like only by addition / subtraction or product-sum operation. That is, in order to execute the maximum value / minimum value detection processing or the like by a combination of addition and subtraction or the product-sum operation, even if the program is devised, several instruction steps are required for each input data. Is a burden on the user, and causes an increase in power consumption.

[0003]

SUMMARY OF THE INVENTION One of the objects of the present invention is to execute a speech codec or the like by configuring a DSP so as to detect a maximum value and / or a minimum value without using an adder / subtracter or a product-sum unit. An object of the present invention is to enable a large-scale program to be executed at high speed and with low power consumption. Another object of the present invention is to appropriately achieve the above object by enabling detection of a maximum value and / or a minimum value in one basic cycle per data. Also,
One of the objects of the present invention is to make it possible to detect not only the maximum value and / or the minimum value but also the number of the data having the maximum value and / or the data having the minimum value. An object of the present invention is to enable the maximum value detection, the minimum value detection, the initial setting, and the like to be selectively executed in response to an external command.

In order to achieve such an object, the D
SP is a first operation block for obtaining at least one of a sum, a difference, a product sum, and a shift value of input data sequentially input, and a second operation block for detecting a maximum value or a minimum value from the input data. And the following. By providing the second operation block having such a function in the DSP separately from the first operation block,
Since the detection of the maximum value or the minimum value can be executed without using the first operation block, the processing amount of the DSP related to the detection of the maximum value or the minimum value is reduced, so that the load on the processing capacity is reduced and the power consumption is reduced. Can be suppressed.

[0005] Further, as the above-mentioned second operation block,
For example, a first register for temporarily storing past input data, a comparator for detecting a magnitude relationship between new input data and past input data on the first register, and a maximum value in view of the detected magnitude relationship. Maximum value data writing means for storing data having a value in the first register. Alternatively, in place of the maximum value data writing means used in the maximum value detector, a minimum value including minimum value data writing means for storing data having a minimum value in the first register in view of the detected magnitude relation. A detector can be used. When the maximum value or minimum value detector having such a configuration is used as the above-described second arithmetic block, the processing for one input data is completed in one basic cycle of the maximum value or minimum value data writing unit. , DS according to the present invention
The effect in P, for example, the reduction in the number of processing steps when executing a large-scale program becomes more conspicuous, so that power consumption,
The number of program steps and the program capacity can be greatly reduced. That is, the maximum value or minimum value data writing means performs the input / determination of the magnitude relationship detected by the comparator and the writing of data to the first register based on the result in a total of one basic cycle, for example. Since it can be executed in each half cycle, the above-described effects can be obtained.

Further, the second operation block can be realized as a maximum value minimum value detector having both functions of the maximum value detector and the minimum value detector. In this case, it is preferable to provide data write path control means. The data writing path control means operates the maximum value data writing means when the maximum value detection is instructed, and operates the minimum value data writing means when the minimum value detection is instructed. By employing such a configuration, the operation mode in the second operation block can be switched from outside.

Preferably, the maximum value detector, the minimum value detector or the maximum value minimum value detector according to the present invention comprises: a counter unit for assigning a number to each of sequentially input data by counting; A second register for temporarily storing the number of past input data, and a first register for temporarily storing a number corresponding to data on the first register on the second register.
Number writing means for updating a number on the second register in synchronization with writing of data to the register. With this configuration, it is possible to detect not only the maximum value and the minimum value but also the number of the input data having the maximum value and the minimum value in one basic cycle. Further, the timing of writing data or a number from the counter unit to the first or second register is given in synchronization with the timing of the counting, so that the data on the first register and the data on the second register are given. Can always be maintained in correspondence with the number.

[0008] The maximum value detector, the minimum value detector or the maximum value minimum value detector according to the present invention is preferably the first value detector.
Alternatively, an initial setting path control means for storing new input data or an output of the counter unit in an initial setting destination register when initial setting of data or a number in at least one of the second registers is designated. Providing such an initialization path control means makes it possible to initialize desired data or numbers on the first or second register. In addition, the maximum value detector, the minimum value detector, or the maximum value minimum value detector according to the present invention is preferably the first value detector.
Alternatively, an output selector for selectively outputting data or a number stored in the second register is provided. By providing such an output selector, it becomes possible to output data or numbers on the first or second register in response to an external request.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. The embodiment described below is merely an example, and any modification of a property that can be easily implemented by those skilled in the art based on the disclosure of the present application should be recognized as belonging to the technical scope of the present invention.

FIG. 1 shows a DSP according to an embodiment of the present invention.
The functional configuration of is shown. In the DSP shown in FIG. 1, the four buses A to D are added to an adder / subtractor 10a, a sum-of-products 10b, a shift calculator 10c, and a maximum value / minimum value detector 20 by an input selector S
By _AB and S _CD, it has a structure to selectively connect. Therefore, the data supplied via the buses A to D is selectively supplied to the adder / subtracter 10a, the product-sum device 10b, the shift calculator 10c, and the maximum / minimum detector 20 to obtain the sum, difference, and product of the input data. A sum, shift value, or maximum or minimum value is calculated. Latch sections L1 to L4 are provided at the subsequent stage of the adder / subtracter 10a, the sum of products 10b, the shift calculator 10c, and the maximum / minimum value detector 20, respectively. Latch section L
1 to L4 latch output data from the corresponding one of the adder / subtracter 10a, the product-sum unit 10b, the shift calculator 10c, and the maximum / minimum value detector 20, and supply the latched data to a subsequent circuit (not shown).

The features of the DSP shown in FIG.
Adder / subtracter 10a, sum-of-products 10b, and shift calculator 10c
Is provided with a maximum value / minimum value detector 20, which is a second operation block, independently of the first operation block 10 composed of. That is, since the maximum / minimum value detector 20 is provided as an arithmetic block independent of the first arithmetic block 10, the first arithmetic block 10 is used to perform addition / subtraction or product-sum operation for maximum / minimum value detection. As a result, there is a problem that the processing load of the first operation block 10 is increased.
It does not. Further, as described later, the maximum value / minimum value detector 20 is configured to be able to execute the processing of detecting the maximum value or the minimum value in one basic cycle for one input data. For example, a large-scale program executed by an audio codec, for example,
It is possible to reduce tens of thousands of program steps in total, so that power consumption and program capacity can be significantly reduced.

FIG. 2 shows an example of the configuration of the maximum value / minimum value detector 20 usable in this embodiment. In this figure, four registers (reg) R1 to R4 and selectors (sel) S1 to S4 corresponding to them are used. The register R1 is a register for temporarily storing the maximum or minimum value of the past input data, and the register R2 is a register for temporarily storing the next larger or smaller value. The registers R3 and R4 are registers for storing numbers given to data on the registers R1 and R2, respectively. The selectors S1 and S2 constitute, together with the control unit 21, means for controlling and setting a data write path to the registers R1 and R2, and the selectors S1 and S4, together with the control unit 21, provide access to the registers R3 and R4. A means for controlling and setting the number writing path is realized. Further, the input unit 22
It has a function of supplying input data supplied from the input selection unit S _AB or S _CD to the comparator 23, the selectors S1 to S4, the counter unit 24, and the like. The comparator 23 includes a register R1
And the data on R2 and the data supplied from the input unit 22 are compared, and the magnitude relation is detected and reported to the control unit 21. The counter unit 24 performs counting at a predetermined speed, and counts the resulting count value to the selector S1 or S1.
4, while temporarily storing the data in the register R3 or R4, the timing of the selection operation is given to the selectors S1 to S4 in synchronization with the counting timing. Output selector S
0 is, for example, in response to a command from the control unit 21,
Any one of the data on 1 to R4, that is, the maximum value,
The minimum value or the count value of the counter unit 24 is selectively output.

In the maximum / minimum value detector 20 shown in FIG. 2, specifically, the maximum value is detected by the following procedure.

First, when input data is supplied to the input selector from the buses A to D via S _AB or S _CD , the input unit 22 supplies input data to be subjected to maximum value detection to the comparator 23. The comparator 23 outputs the input data to the register R1.
And data on R2, thereby detecting the magnitude relationship between these three types of data. The control unit 21 sets the register R1 based on the magnitude relation detected by the comparator 23.
And a signal to R2 to enable writing, and a signal to selectors S1 and S2 to set a data write path. For example, when the comparator 23 detects that the input data given from the input unit 22 to the comparator 23 has the maximum value among the three types of data, the control unit 21 sets The data write path is set using the selectors S1 and S2 so that the data is transferred and stored in the register R2, and the data supplied from the input unit 22 to the comparator 23 is stored in the register R1. When the comparator 23 detects that the data from the input unit 22 is the second largest data,
The control unit 21 sets a data write path so that the data input from the input unit 22 to the comparator 23 is stored in the register R2. Then, from the input unit 22 to the comparator 23
When the comparator 23 detects that the input data supplied to the comparator 23 has the smallest value among the three types of data, the control unit 21 transmits the data so that the contents of the registers R1 and R2 are maintained as they are. Set the write path. By performing such a procedure, the register R
The data having the largest value among the data input so far is stored in 1 and the data having the next largest value is stored in the register R2.

The control unit 21 controls and sets the number writing path simultaneously with the control and setting of the data writing path.
The settings are also running. That is, control of the number writing path using the selectors S3 and S4 so that the number corresponding to the data on the register R1 is always stored on the register R3 and the number corresponding to the data on the register R2 is always stored on the register R4. -Execute the setting. This control / setting is similar to the control / setting procedure of the data write path, and thus the description thereof is omitted here, but it will be easily and uniquely understood by those skilled in the art. In understanding, it should be noted that the latest input data number is given by the counter unit 24.

The control section 21 supplies a signal to the output selector S0 in order to selectively supply data or numbers in the registers R1 to R4 to a subsequent stage. Output selector S0
Selectively outputs one or several data or numbers from the registers R1 to R4 in response to this signal. As a result of such processing, it becomes possible for a subsequent circuit to selectively receive information such as a maximum value and a number corresponding thereto.

The control unit 21 executes the above-described maximum value detection operation in accordance with a control signal instructing the maximum value detection. When the control signal instructing the minimum value detection is given, the control unit 21 executes the minimum value detection procedure instead of the above-described maximum value detection procedure. Regarding the specific contents of the minimum value detection procedure, in the above description of the maximum value detection procedure, descriptions such as “maximum value” and “large” should be read as “minimum value” and “small”. When a control signal for instructing initialization is given, the control unit 21 performs, for example, an initialization operation such as directly writing or setting data supplied from the input unit 22 to the registers R1 to R4 and the counter unit 24. Is executed. As described above, in the maximum / minimum value detector 20 shown in FIG.
It is possible to switch between three types such as minimum value detection and initial setting.

Although the maximum value minimum value detector 20 shown in FIG. 2 detects the second data from the largest or the smallest and the number thereof, the number of selector registers is increased. This makes it possible to detect the third and subsequent data or their numbers.
In addition, when it is not necessary, the components related to the number detection may be omitted.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a functional configuration of a DSP according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a configuration of a maximum value / minimum value detector usable in this embodiment.

[Description of Signs] 10 first operation block, 20 maximum value minimum value detector,
21 control unit, 22 input unit, 23 comparator, 24 counting unit, S0 to S4 selector, R1 to R4 register.

Claims (8)

[Claims] 1. A first method for determining at least one of a sum, a difference, a product sum, and a shift value of input data sequentially input.
A DSP comprising: an operation block; and a second operation block that detects a maximum value or a minimum value from the input data. 2. A first register for temporarily storing past input data, a comparator for detecting a magnitude relationship between new input data and past input data on the first register,
Maximum value data writing means for storing data having the maximum value in view of the detected magnitude relation in the first register;
A maximum value detector used as the second operation block in the DSP according to claim 1. 3. A first register for temporarily storing past input data, a comparator for detecting a magnitude relationship between new input data and past input data on the first register,
Minimum value data writing means for storing data having a minimum value in view of the detected magnitude relation in the first register;
A minimum value detector used as the second operation block in the DSP according to claim 1. 4. A maximum value detector according to claim 2, a minimum value data writing means for storing data having a minimum value in view of the detected magnitude relationship in a first register, and a maximum value detection command is issued. Sometimes the maximum value data writing means
2. The DSP according to claim 1, further comprising data write path control means for operating the minimum value data writing means when the minimum value detection is instructed, and being used as a second operation block in the DSP according to claim 1. Value minimum detector. 5. A counter unit for assigning a number to each successively inputted input data by counting, a second register for temporarily storing the number of past input data, and a second register corresponding to data on the first register. 2. A number writing means for updating a number in the second register in synchronization with writing of data to the first register so as to be temporarily stored in the second register. 5. The detector according to claim 2, wherein the detector is used as a block. 6. The detector according to claim 5, wherein the counter section gives a timing of writing data or a number to the first or second register in synchronization with the timing of the counting. 7. An initial setting for storing new input data or an output of the counting section in a register of an initial setting destination when an initial setting of data or a number to at least one of the first and second registers is instructed. 7. The detector according to claim 5, further comprising a setting path control unit. 8. The maximum value / minimum value detector according to claim 5, further comprising an output selector for selectively outputting data or a number stored in the first or second register.