JPH11119976A - Data dividing parallel shifter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data dividing parallel shifter, capable of shortening shift processing time. SOLUTION: A shift circuit 1 performs in parallel the shift of input data with no division, the generation of code expansion data through a code expansion data generating circuit 2, and the generation of a mask signal through a mask signal generating circuit 3, the shift data of the shift circuit 1 or the code expansion data are selected based on the mask signal, and the respective field of input data divided into plural fields are shifted in parallel so that a code can be expanded into prescribed bits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a data division parallel shifter that performs data division and shift processing in relation to arithmetic processing of a microprocessor.

[0002]

2. Description of the Related Art In an arithmetic processing unit of a processor for performing data processing, there is a processing method for dividing data into a plurality of fields and collectively operating each data as a technique for improving data processing efficiency. For example, 64-bit data is divided into four data in 16-bit units, and an addition instruction is to simultaneously perform four additions.

[0003] This is more effective in fields such as image processing and audio processing than traditional scientific and business calculations.
These operations require addition, subtraction, multiplication, division, and logical operations, as well as shift processing. In the normal shift process, a logical shift (logical) that fills a portion vacated by the shift with 0 is performed.
shift) and arithmetic shift (Arith) for sign extension
(mechanical shift). In order to be able to divide the data into a plurality of fields and perform the shift process, it is necessary to perform a process of switching which part is sign-extended according to the mode of division. For example, 32 bit data is converted to a 32 bit mode, a (16 bit × 2) mode, (8
The results when the rightward operation shift is performed by 3 bits in each of the (bit × 4) modes are shown below.

[0004]

[Table 1] bit31 bit0 Original data 110 11011 001 10101 001 00100 100 10100 32bit mode 111 11011 011 00110 101 00100 100 10010 16x2mode 111 11011 011 00110 000 00100 100 10010 8x4 mode 111 11011 000 00110 000 00100 111 10010 The underlined part is the sign extension part. That is, in the 32-bit shift mode, the bit 31 is sign-extended. In the (16 bits × 2) mode,
The sign extension of the upper 16 bits extends bit 31 and the lower 16 bits extend bit 15. (8 bits x
4) In the mode, bits 31 to 24 extend bit 31; bits 23 to 16 extend bit 23; bits 15 to 8 extend bit 15; Expands bit 7. In the logical shift, the underline is expanded to zero.

Next, the configuration of the shift circuit will be described. The shift processing in the right direction will be described for clarity.

First, an ordinary shifter having no division function will be described. FIG. 5 shows a normal 32-bit rightward shift circuit. In FIG. 5, in the 32-bit shifter,
1-bit, 2-bit, 4-bit, 8-bit, and 16-bit bit shift circuits 101 to 105 are connected in multiple stages. Each shift circuit is constituted by a simple selection circuit. The shift circuit is configured by stacking these selection circuits in multiple stages. The 1-bit shift circuit 101 outputs the data one bit to the left when performing a shift, and outputs the data as it is when not performing a shift. A selection signal for outputting the next data or outputting the data as it is is generated from the least significant bit of the shift amount and a signal indicating the left / right shift direction. That is, when 1 is set in the least significant bit of the shift amount, 1-bit shift is performed, and when it is 0, there is no need to perform the shift, and the data is directly output downward. In the 2-bit shift circuit 102, a choice is made whether to output 2-bit left data or to output the data as it is. The selection signal of the 2-bit shift circuit 102 is the value of the second bit from the lower order of the shift amount. A shift operation of an arbitrary shift amount from 0 bit to 31 bits is performed depending on whether each shift circuit is operated according to the shift amount signal. For example, in a 3-bit shift, a 1-bit shift and 2
The bit shift circuits 101 and 102 perform the shift, and the other bit shift circuits 103, 104 and 105 do not perform the shift.

If the field is not divided, the sign extension process applies the leftmost value of the original data to the port where there is no corresponding left data in each shift circuit,
In the case of a logical shift, this is realized by extending 0.

[0008] The data used for sign extension is a control signal indicating whether to perform an operation shift or a logical shift, and is generated in advance in a sign extension data generation circuit. For example, in the 1-bit shift circuit 101, there is no data on the left side to be taken by the leftmost selection circuit. Therefore,
By inserting the sign extension data from the sign extension data generation circuit into the port, if one bit shift occurs, the selection circuit outputs the sign extension data.

The sign extension data is, for example, as shown in FIG.
To 112. In such a configuration, in the operation shift in which the operation shift signal is at the high level, the bit 31 of the original data is set to 3 when shifting by 32 bits.
Output as sign extension data of all 2 bits, (16
In the bit × 2) mode, the upper bit 31 to the bit 1
The bit 31 of the original data is output as sign extension data up to bit 6 and the bit 15 of the original data is output as sign extension data from the lower bits 15 to bit 0. In the (8 bits × 4) mode, the bits 31 to 24 are output as the original data. Bit 23 of the original data from bit 23 to bit 16
And bits 15 to 8 are bits 1 of the original data.
5 from bit 7 to bit 0, bit 7 of the original data
Is output. On the other hand, the operation shift signal
When ic) is a low level logical shift, 0 is output as sign extension data for all bits.

When the (16-bit shift × 2) mode and the (8-bit shift × 4) mode are added to the circuit shown in FIG. 5, how to perform the sign extension process becomes a problem. To add the sign extension function, as shown in FIG. 7, by inserting a sign extension selection circuit 113 for performing sign extension or performing normal shift between the stages of the bit shift circuits 101 to 105. It can be carried out.

In the (16 bits × 2) mode, the 16-bit shift circuit 105 controls all the sign extension selecting circuits to select sign extension. The 8-bit shift circuit 104 controls the sign extension selection circuit 113 from bit 15 to bit 8 of the same circuit to select sign extension. Similarly, in the 4-bit shift circuit 103, bit 15
To the bit 4, the 2-bit shift circuit 102 converts the bits 15 to 2 to the 1-bit shift circuit 10.
In the case of 1, the control is performed so that the bit extension from the bit 15 to the bit 1 is selected.

In (8 bits × 4 mode), the 16-bit shift circuit 105 and the 8-bit shift circuit 104
Control is performed so that all sign extension selection circuits 113 select sign extension. In the 4-bit shift circuit 103, control is performed such that a coding extension circuit of bits 23 to 20; bits 15 to 12; and bits 7 to 4 selects code extension data. In the 2-bit shift circuit 102, control is performed such that the sign extension selection circuits 113 of bits 23 to 18, bits 15 to 10, and bits 7 to 2 select sign extension data. 1
In the bit shift circuit 101, bit 23 to bit 1
Control is performed so that the sign extension selection circuit 113 of bit 7, bit 15 to bit 9 and bit 7 to bit 1 selects sign extension data.

As described above, by inserting the sign extension selection circuit 113 between the respective bit shift circuits, the data field can be divided and shifted in parallel. However, since the sign extension selection circuit 113 is realized by a selector as in the case of the shift circuit, the number of stages of the circuit is twice as large as that of a normal shift circuit, and the processing speed is extremely slow. Also, although the description has been made of the provision of the sign extension data generation circuit, in this case, the delay time for generating the sign extension data by the circuit is added to the entire delay time as it is. As a method that does not use the sign extension data generation circuit, it is conceivable to add a selection circuit for selecting which data to use as sign extension data in each sign extension selection circuit 113 according to a mode. The use of the data generation circuit causes a speed delay and an increase in circuit scale.

In a normal shift circuit, it is necessary to pass five stages through a selection circuit for a 32-bit shift, but this is replaced by a two-input selection circuit with a selection function for speed improvement. Using a four-input selection circuit, for example, one-bit shift and two-bit shift are input to the selection circuit in one stage, and the selection from the left three bits, one bit, and no shift is performed, and processing for two stages is performed at a time. It is also possible to build a circuit in the system. However, when a parallel shift function is added to the circuit, the number of code extension selection circuits per bit is tripled, and the circuit configuration becomes difficult. Further, in a barrel shifter that can perform both leftward shift and rightward shift, the same sign extension selection circuit is required twice, and the circuit configuration becomes more difficult in both area and speed.

[0015]

As described above,
In a conventional data division parallel shifter that shifts divided data in parallel, when performing sign extension processing, a selector twice as large as a normal shift circuit that does not perform sign extension is required, and the configuration is enlarged. In addition, the processing speed was reduced. Further, the generation time for generating a code to be expanded in advance is added to the operation time of the entire shift circuit, which further reduces the processing speed.

Accordingly, the present invention has been made in view of the above, and an object of the present invention is to provide a data division parallel shifter capable of shortening the processing time of the data division parallel shift processing including the sign extension. The purpose is to provide.

[0017]

To achieve the above object, according to the first aspect of the present invention, input data is divided into a plurality of fields, and input data of each of the divided fields is simultaneously shifted. In a data division parallel shifter that extends a sign or 0 to a predetermined bit, a shift circuit that shifts the input data by a predetermined shift amount without dividing the input data, and the input data divided according to a mode in which the input data is divided. A sign extension data generation circuit that generates sign extension data or 0 extension data corresponding to each field of the input data, and an input data shifted by the shift circuit according to a shift amount of the input data and a mode of dividing the input data. Generating a mask signal for selecting the sign extension data generated by the sign extension data generation circuit A mask signal generation circuit and input data shifted by the shift circuit according to the mask signal generated by the mask signal generation circuit or code extension data generated by the sign extension data generation circuit, and a code is extended. An output selection circuit for outputting a shift result of input data is provided.

According to a second aspect of the present invention, in the data division parallel shift circuit according to the first aspect, the shift circuit comprises:
The mask signal generation circuit includes a barrel shifter that shifts input data in both the upper direction and the lower direction of the input data. The mask signal generation circuit adds a shift direction to a shift amount of the input data and a mode for dividing the input data. Is generated.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a data division parallel shifter according to an embodiment of the present invention.

In FIG. 1, the data division parallel shifter
A normal shift circuit 1 having no division shift function, a sign extension data generation circuit 2 for generating sign extension data corresponding to the division mode, and a mask for determining the extent of sign extension by decoding the shift amount A shift signal processing circuit is provided which includes a mask signal generation circuit 3 for generating a signal, and a selection circuit 4 for selecting data normally shifted by the mask signal from the mask signal generation circuit 3 or sign extension data of the sign extension data generation circuit 2. By performing the sign extension data generation and the mask signal generation in parallel, the field division parallel shift function is realized only by adding the delay of the final stage to the delay of the normal shift processing.

The data division parallel shifter of this embodiment
The shifter has a 32-bit shift mode, a (16-bit × 2) shift mode, and an (8-bit × 4) shift mode, and performs an arithmetic right shift and a logical right shift. Although the shift circuit 1 shown in FIG. 1 shows a barrel shifter capable of shifting in both the left and right directions, the barrel shifter in FIG. The control signal indicating the shift direction is deleted.

The shift circuit 1 is also used in the description of the conventional example.
The shift circuit shown in FIG. 5 is used. Similarly, the sign extension data generation circuit 2 uses the sign extension data generation circuit shown in FIG. 6 used in the description of the conventional example.

Next, the mask signal generation circuit 3 which is a feature of the present invention will be described.

In this embodiment, 32 is assumed.
The division mode of the input data of bits is 32 bits, 16 bits.
There are three modes: bit × 2 and 8-bit × 4. Therefore, first, an 8-bit mask signal, which is the minimum unit of division, is
Generated from the lower 32 bits of the shift amount and further masked with the upper 2 bits of the shift amount and all 8 bits for each of the four 8-bit fields from the three mode signals, or masked with an 8-bit mask signal, A configuration for generating a 32-bit mask signal by selecting whether or not to mask all the bits is easy as a circuit.

FIG. 2 shows an 8-bit mask signal generation circuit 8 for generating a mask signal in units of 8 bits from the lower 3 bits of the shift amount. In FIG. 2, a mask signal generation circuit 8 is a kind of decoder, and includes a NAND gate (NAND) 5 receiving a shift amount or an inversion shift amount, a series-connected transistor 6 that is controlled to be conductive by an output of the NAND 5, An inverter 7 that receives a signal of each series connection point of the transistor 6 and outputs an 8-bit mask signal Mask0 to Mask7 is provided.

In such a configuration, when the values of the lower three bits M2, M1 and M0 of the shift amount are determined, only the output of the NAND 5 corresponding to the same value becomes 0, and this NA
The gate of the transistor 6 to which the output of the ND5 is connected is closed. The other NAND 5 outputs 1 and the transistor 6 to which each output is connected is turned on. For this reason, all nodes between the transistors 6 on the left side of the closed transistor 6 are 0, and each node on the right side is 1.
The inverter 7 connected to each node outputs 1 on the left side and 0 on the right side of the closed transistor 6. For example, M2
If 1,0 is 011, the fourth NAND from the left
Only the output of 5 becomes 0. Therefore, from Mask7 to Ma
The input node of the inverter 7 up to sk5 becomes 0, and M
The input node of the inverter 7 from the ask4 to the mask0 is 1. As a result, Mask7 to Mask0 are 11
10,000.

Next, the generation logic of the mask signal higher than the 8-bit unit will be described. Possible states of the mask signal in units of 8 bits include a state in which all 8 bits are masked, a state in which it is determined whether or not to be masked by the output of the 8-bit mask signal generation circuit 8, and a state in which all 8 bits are not masked The following three states can be taken. For example, if the shift amount is 0
In the 32-bit mode at 1011, the mask signal is 11111111 11100000 00000000 00000000. The state in which all the 8 most significant bits are masked, the state in which the second most significant 8 bits use the mask signal of the 8-bit mask signal generation circuit 8, the third and least significant 8 bits
All bits are unmasked. With the same shift amount, the mask signal in the case of the (16 bits × 2) mode is 11111111 11100000 11111111 11100000. M4 and M3, which are the upper two bits of the shift amount, and shift mode signals mode32, mode16, and mode
Output Mask of 8, 8-bit mask signal generation circuit 8
An equation for generating a mask signal mask [31: 0] from [7: 0] is shown below. In the following equation,
| Indicates a logical sum, & indicates a logical product, and b indicates signal inversion.

[0029]

[Equation 1] if (M4 | M3) masks [31:24] = 11111111; elseif (M4b & M3b) maska [31:24] = Mask [7: 0]; else masks [31:24] = 00000000; endif if ((M4 & (mode32 | mode16)) | ((M4 | M3) & mode8)) masks [23:16] = 11111111; elseif ((M4 | M3) & mode32 | M3 & mode16 | M4b & M3b & mode8) masks [23:16] = Mask [7: 0]; else masks [23:16] = 00000000; endif if ((M3 & M4) & mode32 | (M3 | M2) & (mode16 | mode8) masks [15: 8] = 11111111; elseif ((M4 & mode32) | (M3b & M4b) & (mode16 | mode8)) mask [15: 8] = Mask [7: 0]; else masks [15: 8] = 00000000; endif if ((M4 & mode16) | ( M3 | m4) & mode8) masks [7: 0] = 11111111; elseif ((M3 & M4 & mode32) | (M3 & mode16) | (M4b & M3b & mode8)) maska [7: 0] = Mask [7: 0]; else masks [7: 0] = 00000000; The condition of the if statement in the above expression becomes the logic of the selection signal,
In accordance with this selection signal, all 8 bits are all 1 or M by the multiplexer 9 of the mask signal generation circuit 3 shown in FIG.
Selection of ask [7: 0] or all 0 is performed, and the result is output from the mask signal generation circuit 3.

The shift circuit 1 outputs shift data, and the sign extension data generation circuit 3 outputs sign extension data.
According to the mask signal generated by the mask signal generation circuit 3, if the mask signal is 1, sign extension data is selected, and if the mask signal is 0, shift data is selected in the final stage output selection circuit 4 in each bit unit to obtain a final output. .

The shift circuit 1, the sign extension data generation circuit 2, and the mask signal generation circuit 3 can perform processing completely independently up to the final output selection circuit 4. For this reason, the delay of the circuit does not become the cumulative addition of each other's delay as shown in the conventional example, but is the maximum delay among the shift circuit 1, the sign extension data generation circuit 2, and the mask signal generation circuit 3. ,
Only the delay of the final stage output selection circuit 4 is added. Also within the mask signal generation circuit 3, the 8-bit mask signal generation circuit 8 and the logic circuit that generates the higher-order selection signal can be processed in parallel. Therefore, the shift circuit 1 of the present embodiment can perform the shift processing with a delay time that adds the delay of the output selection circuit 4 at the last stage to the normal shift circuit, and can perform the data division parallel shift processing as compared with the conventional case. Processing time can be reduced.

Next, an embodiment of the present invention will be described.

In this embodiment, the mask signal generation circuit 3
The shift circuit 1 is substantially the same as the above-described embodiment except for the configuration described above, and the shift circuit 1 can use the conventional barrel shifter used in the embodiment shown in FIG. In the shift circuit of only rightward shift shown in FIG. 1, a two-input selection circuit for determining whether shift data from the left or data is passed as it is, whereas the barrel shifter of this embodiment employs an input shift from the right. A three-input selection circuit that can select data is used. In other words, the 1-bit shift circuit selects one of three data: one bit right adjacent data, one bit left adjacent data, and no shift data. The right shift circuit uses a seven-input selection circuit instead of a three-input selection circuit in the barrel shifter in the same way as using a four-input selection circuit to perform two stages of processing at one time.

In the sign extension data generation circuit, the sign bit of the normal data is the MSB, and is the leftmost bit in this embodiment. For this reason, in the case of a leftward shift, a portion which becomes blank due to the shift is usually padded with zeros. Therefore, only the logical shift is performed in the leftward direction, and the sign extension data generation circuit can use the one used in the above embodiment as it is.

The mask signal generation circuit requires an additional circuit in order to cope with switching in the left and right shift directions. The 8-bit mask signal generation circuit requires, for example, a shift amount of lower three bits as shown in FIG. An exclusive OR gate (EXOR) 10 for receiving any one bit of M0 to M2 and a switching signal for switching the left / right shift direction;
NAND 11 receiving the output of OR 10 or its inverted signal
A transistor 12 connected in series by controlling the output of the NAND 11, an inverter 13 for inverting the output of the series connection point of the transistor 12, a buffer 14 receiving the output of the series connection point of the transistor 12, Select the output of the inverter 13 or the output of the buffer 14 based on the switching signal of
It is provided with a selector 15 for outputting sk0 to Mask7, inverts and inputs shift amount data by a left / right shift switching signal, and also inverts and shifts the output by one bit. Thus, when the three least significant bits of the shift amount are 011, Mask [7: 0] = 11100000 in the rightward shift, and Mask [7: 0] = 00000111 in the leftward shift.

In the same manner as in the above embodiment, the mask signal generation circuit higher than the 8-bit unit selects any one of the three outputs of all 1, all 0 and the output of the 8-bit mask signal generation circuit. is there. However, the logic of the selection control signal needs to be changed as in the case of the 8-bit mask signal generation circuit. Although various embodiments are conceivable,
Basically, it suffices that the upper and lower parts are line-symmetric. That is, at the time of shifting rightward, a selection signal for generating a mask signal of bits [31:24] is used for bits [7: 0], and a selection signal used for bits [23:16] is used for bits [15: 8].
It should be used for.

The selection of the shift data of the barrel shifter 1 or the sign extension data generated by the sign extension data generation circuit 2 is the same as that of the output selection circuit 4 of the above embodiment.

In this embodiment, the same effects as those of the above embodiment can be obtained in any of the left and right shift directions of the input data.

In the above embodiment, the input data is 3
2 bits, division mode 32 bits, (16 bits ×
2), (8 bits × 4), but there is no restriction on the number of bits of input data or the division mode. For example, for a 64-bit input data, the division mode is 64 bits, (32 bits × 2) , (16 bits × 4) and (8 bits × 8), the above-described embodiment can be extended and implemented in the same manner.

[0040]

As described above, according to the present invention, data shift processing, sign extension data generation,
Since the mask signal for determining the number of bits to be subjected to the sign extension is generated in parallel, the data is stored in a plurality of fields by increasing the delay of the selection circuit by one stage in addition to the delay of the conventional shift circuit. The function of dividing and shifting simultaneously can be realized, and the processing time of data division parallel shift processing including sign extension can be shortened.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a data division parallel shifter according to one embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of an 8-bit mask signal generation circuit.

FIG. 3 is a diagram illustrating a configuration of a mask signal generation circuit.

FIG. 4 is a diagram showing a configuration of an 8-bit mask signal generation circuit of a data division parallel shifter according to an embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a 32-bit rightward shift circuit having no function of separating input data.

FIG. 6 is a diagram illustrating a configuration of a sign extension data generation circuit.

FIG. 7 is a diagram showing a configuration of a conventional data division parallel shifter.

[Description of Signs] 1 shift circuit 2 sign extension data generation circuit 3 mask signal generation circuit 4 output selection circuit 5, 7, 10, 11 logic gate 6, 12, 13 transistor 8 8-bit mask signal generation circuit 9 selector 14 buffer

Claims (2)

[Claims] 1. A data division parallel shifter that divides input data into a plurality of fields and simultaneously shifts input data of each of the divided fields to extend a sign or 0 to predetermined bits. A shift circuit that shifts the input data by a predetermined shift amount without performing the operation, and sign extension data that generates sign extension data or 0 extension data corresponding to each field of the divided input data according to a mode of dividing the input data. Generating a mask signal for selecting the input data shifted by the shift circuit or the sign extension data generated by the sign extension data generation circuit according to a shift amount of the input data and a mode for dividing the input data; A mask signal generation circuit that generates An output selection circuit that selects the input data shifted by the shift circuit according to the mask signal or the sign extension data generated by the sign extension data generation circuit, and outputs a shift result of the sign-extended input data. Characteristic data division parallel shifter. 2. The shift circuit includes a barrel shifter that shifts input data in both an upper direction and a lower direction of the input data, and the mask signal generation circuit divides the input data shift amount and the input data. 2. The data division parallel shifter according to claim 1, wherein a mask signal is generated by adding a shift direction to the mode to be shifted.