JPS63245568A - Picture converter - Google Patents

Abstract

PURPOSE:To easily change a design for the high speed of a processing by applying an arithmetic processing to a picture element selected from an original picture element and defining the arithmetic result to be the picture element of a converted picture. CONSTITUTION:Document information obtained by scanning an original by a picture reading part 100 is converted to a binary picture consisting of (m)X(n) picture elements. This binary picture is written in a picture memory 200 under the control of a writing circuit 201 and read from the memory 200 under the control of a reading circuit 202. The binary picture of this memory 200 is defined to be an original picture and a picture converter 300 forms an enlarged/ reduced converted picture. Then, the converted picture is written in an output buffer 400 under the control of a writing circuit 401, read under the control of a reading circuit 402 and displayed on a display part 500, for instance, a CRT display device.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention relates to an image conversion device, which performs arithmetic processing on some pixels selected from an original image, and calculates the result of the arithmetic operation. The present invention relates to an image conversion device that converts an original image into a target image by using pixels of the converted image.

(Prior Art) Conventionally, image conversion devices such as image scaling circuits determine the pixel value after conversion according to a certain calculation algorithm from the position of the pixel after conversion and information on surrounding pixels, and The image is converted into an image (converted image).

However, if this method is implemented using hardware, the calculation processing becomes quite complex and requires a long processing time.

Therefore, so-called vibe line processing may be performed in the arithmetic unit.

FIG. 9 shows an example of a vibe line process having three stages of registers. In this vibe line processing, a plurality of calculation units 1, 3
, 5.7 are connected by registers 2, 4.6 having the required number of data lines, thereby realizing the arithmetic algorithm by dividing it into multiple stages. In this case, the entire arithmetic vibration line section can operate at the same processing speed as the arithmetic section having the slowest operation time among the nasal performance sections 1, 3, and 5.7, and the arithmetic processing speed is increased.

However, with the above method, when trying to speed up processing by changing the number of stages in the calculation pipeline section by reviewing the calculation algorithm or replacing the elements that make up each calculation section, the independence between each calculation section Because of the low level of power, it was necessary to make major design changes to the circuit configuration and its control method.

(Problems to be Solved by the Invention) In this invention, since the independence of each arithmetic unit that performs pipeline processing is low, when trying to speed up processing by reviewing the arithmetic algorithm, etc., the arithmetic pipeline unit This eliminates the disadvantages of requiring large-scale modifications to the number of stages and operating clock signals, and makes it easier to review calculation algorithms and change elements, making it possible to make design changes to speed up processing. It is an object of the present invention to provide a highly versatile image conversion device that can easily perform image conversion.

[Configuration of the Invention (Means for Solving Problems) The image conversion device of the present invention includes a plurality of calculation units,
Image conversion is performed by operating the registers that connect these calculation units in parallel to perform calculation processing on some pixels selected from the original image, and using the calculation results as pixels of the converted image. The image conversion apparatus is provided with a control means that can arbitrarily set the number of stages of the registers and the operation time between each calculation section.

(Operation) This invention performs arithmetic processing on several pixels selected from an original image by operating a plurality of arithmetic units and registers that connect these arithmetic units in parallel, and performs arithmetic processing on several pixels selected from an original image. In an image conversion device that performs image conversion by using the result as a pixel of a converted image, the number of register stages and the operating time between each calculation unit can be set arbitrarily, thereby increasing the independence of each calculation unit. However, design changes such as the circuit configuration and its control method can be easily realized with minimal modifications.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 8 shows the configuration of an image processing apparatus to which the present invention is applied. This image processing device includes an image reading section 100
, an image memory 200, an image conversion device 300, an output buffer 400, a display section 500, and a CPU 600 as an information processing unit that manages and controls the entire device. That is, in response to the supply of control signals from the CPU 600 via the CPU bus 601, desired processing such as image enlargement/reduction is executed.

For the image reading section 100, a document reading mechanism used in facsimile machines, copying machines, etc. can be used as is. Here, the image reading unit 100 converts document information obtained by scanning a document into a binary image consisting of m×n picture elements. This binary image is stored in the image memory 2 under the control of the write circuit (W) 201.
00 and read out from the image memory 200 under the control of the readout circuit (R) 202.

The image conversion device 300 creates an enlarged/reduced converted image using the binary image in the image memory 200 as an original image.

This converted image is written to the output buffer 400 under the control of the write circuit (W) 401 and read out under the control of the read circuit (R) 402, and is displayed on the display section 500.
, for example displayed on a CRT display device.

FIG. 1 shows an example of the configuration of an image conversion device 300.
It has a pipeline configuration with stages of registers. That is, the arithmetic units 301, 302, 30 divided into four stages
3,304.3 stages of registers 305, 306, 307,
Pixel selection section 308, calculation control section 309, configuration setting section 31
Consists of 0.

The calculation units 301, 302, 303, and 304 are combinational circuits or storage elements for realizing a desired calculation algorithm, respectively.

The registers 305, 306, and 307 are latch circuits or flip-flop circuits each having the number of signal lines necessary for transferring data between adjacent arithmetic units.

The pixel selection unit 308 selects original pixels in a 4×4 area centered on the converted pixel from the binary image in the image memory 200, for example, and outputs the selected original pixels to the calculation unit 301. In this case, if the arithmetic algorithm requires it, it may be possible to output a larger area of original pixels, or to output not only the original pixel information, but also multiple small areas where the converted pixel is smaller than the original pixel. It may also be possible to output information about which area within .

The arithmetic control unit 309 performs line No. 1. 2, a pixel selection unit 308 and each calculation unit 301, 302,
In addition to controlling the operation timing of 303 and 304,
Writing to the subsequent output buffer 400 is controlled via line l.

As shown in FIG. 2, under the control of the configuration setting section 310, the arithmetic control section 309 sets the number of stages of registers in the arithmetic pipeline section by switching it to four stages: ro, 1, 2, and 3J. 309A, and a cycle setting unit 309B that variably sets the calculation time between adjacent registers within the range of 4 cycles of 1°2.3.4J of the basic operation clock of the image conversion device 300.Number of stages setting Section 309A
is composed of flip-flop circuits 311, 312, 313, 314 with a clock enable function, a selector 318, and an AND circuit 320, and the first data of each line sent from the pixel selection section 308 is required for passing through the pipeline section. The data input enable signal EN3 to the output buffer 400 is delayed by the amount of time.

The cycle setting section 309B includes JK flip-flop circuits 315, 316, 317, a selector 319, an AND circuit 322, and a NOT circuit 321, and the cycle setting section 309B includes the flip-flop circuits 311, 312, 312, . A signal CKE for inhibiting the clock operation of 313 is generated. In this case, an output enable signal EN1 at the output section of the pixel selection section 308, a clock enable signal E to each register 305, 306, and 307 constituting the pipeline section.
N2 and the EN3 are both operated in synchronization with the rising edge of the basic clock, and the flip-flop circuit 3
11 to 317 and pipeline section registers 305 to 30
7 are all operated by the basic clock.

Further, the number of register stages and the number of operation cycles of the pipeline section are determined by setting signals sl and s from the configuration setting section 310.
2. Selector 31 at a ratio of 4 to 1 due to s3 and 64
8,319 is operated. That is, the number of register stages and the number of operation cycles are as shown in Tables 1 and 2 below, respectively, when the setting signal s 1 r
It is determined by some combination of s 2 + s 3 +s4.

In addition, in this embodiment, the register 305°306.30
However, if a register without a clock enable input is used, the AND of EN2 and the basic clock may be used as the clock operation of the register. Furthermore, it is possible to easily widen the setting range of the number of register stages and the number of operating cycles using a similar circuit, or it is possible to set only either the number of register stages or the number of operating cycles using a similar circuit. This is possible.

The configuration setting unit 310 receives setting signals sl, s2 . This is the part to set s3 and s4. For example, as shown in FIG.
1,82°s3. s4, each setting signal sl.

s2. s3. It is composed of a latch circuit or flip-flop circuit 310a having a port prepared corresponding to s4, and an address decoder 310b. in this case,
It can be controlled from the CPU 600 and does not require any changes to the hardware. Further, as a simple method, for example, as shown in FIG. 4, the boss Pi, P2. P
3°P4 and jumpers Jl, J2. J3. J4 or, as shown in FIG. 5, switch SWI.

SW2. SW3. SW4 and resistors R1, R2, R3゜R4
It is also possible to configure the configuration setting section 310 with the following.

With the above configuration, the number of register stages in the arithmetic pipeline section and the operating cycle relative to the basic clock can be easily changed, so if the number of register stages is increased or decreased due to a review of the arithmetic algorithm or circuit configuration, or when configuring the arithmetic section. By replacing the element with a faster one,
Setting signals sl, s2. s3. This can easily be done by simply changing the combination settings of s4.

Next, the operation of the above configuration will be explained with reference to FIG. 6, focusing on the operation of the image conversion device 300 with respect to the combination of the number of register stages and the operation cycle. For example, document information on a document is read as a binary image by the image reading unit 100 under the control of the CPU 600 and supplied to the image conversion device 300 via the image memory 200.

In this image conversion device 300, a converted image is created using a binary image as an original image. That is, in response to the supply of ENI (output enable signal) from the image memory 200, the pixel selection unit 308 selects, for example, an original pixel within a 4×4 area centered on the converted pixel, and selects the original pixel in the arithmetic pipeline unit. It is output to the calculation unit 301. Then, the calculation pipeline section performs the following operations according to the operation timing under the control of the calculation control section 309 based on the setting signals s 1 , s 2 + s 3 , and s 4 from the configuration setting section 310.
After performing various processes corresponding to the calculation algorithm, the pixels are transferred to the output buffer 400.

In this case, each enable signal EN1, EN2, . The operation of the output pixel of EN3 and the pixel selection section 308 is as shown in FIG. For example, the number of register stages is set to "0" and the number of cycles is set to "1", that is, the setting signals sl, s2. s3. When both s4 are set to "0", ENI (output enable signal) is activated in synchronization with the rising edge of the first basic clock, and EN3 (data input enable signal) is activated in synchronization with the rising edge of the next basic clock. It is operated. Then, by the operation of ENI, pixels are sequentially output from the pixel selection section 308 to the calculation section 301 in response to the rising edge of the basic clock.

These pixels are sequentially stored in the output buffer 400 in synchronization with the rising edge of the basic clock by the operation of EN3. As a result, pixels are directly transferred from the calculation unit 301 to the output buffer 400, and the
The period from 05 to 307 is operated in one cycle of the basic clock.

For example, the number of register stages is "3" and the number of cycles is "1".
That is, the setting signal sl.

s2 are both rlJ, s3. When both s4 are set to "0", ENI is operated in synchronization with the rising edge of the first (first) basic clock. Further, EN2 is operated in synchronization with the rising edge of the next (second) basic clock. Furthermore, EN3 is operated in synchronization with the rise of the fifth basic clock. Then, by the operation of ENI, pixels are sequentially output from the pixel selection section 308 to the calculation section 301 in response to the rising edge of the basic clock. These pixels are sequentially transferred to subsequent registers in synchronization with the rising edge of each basic clock by the operation of EN2. Then, by the operation of EN3, the signals are sequentially stored in the output buffer 400 in synchronization with the rising edge of the basic clock. As a result, each register 305, 306, 307
During this period, each operation is performed in one cycle of the basic clock.

Furthermore, for example, the number of register stages is "1" and the number of cycles is "4".
", that is, the setting signals s1 are rOJ, s2 is rlJ, s3 . When s4 are both set to "1",
4 in synchronization with the rising edge of the first (first) basic clock.
ENI is operated every cycle. Next, in synchronization with the rising edge of the fifth basic clock, EN is activated every four cycles.
2 is operated. Furthermore, EN3 is operated every four cycles in synchronization with the rising edge of the tenth basic clock. Then, first, due to the operation of ENI, the basic clock 4
The pixel selection unit 3 sequentially responds to the rising edge of each cycle.
Pixels are output from 08 to the calculation unit 301. This pixel is transferred to the subsequent register 305 in synchronization with the rise of every four cycles of the basic clock by the operation of EN2.

Then, by the operation of EN3, the output buffer 40 is sequentially
Stored to 0. As a result, pixels are transferred from the calculation unit 302 to the output buffer 400, and the registers 305 are each operated in four cycles of the basic clock.

For example, the number of register stages is "2" and the number of cycles is "3".
In other words, the setting signal s1 is rlJ, and s2 is
0'', s3 is set to rlJ, and s4 is set to ``0'',
ENI is operated every three cycles in synchronization with the rising edge of the first (1') basic clock. Next, E
N2 is activated. Further, EN3 is operated every three cycles in synchronization with the rise of the tenth basic clock. Then, by the operation of ENI, pixels are sequentially output from the pixel selection section 308 to the calculation section 301 in response to the rising edge of the basic clock every three cycles. Due to the operation of EN2, this pixel is sequentially transferred to the subsequent register 3 in synchronization with the rise of every 3 cycles of the basic clock.
Transferred to 05°306. Then, by the operation of EN3, the data are sequentially stored in the output buffer 400 in synchronization with the rising edge of the basic clock every three cycles. As a result, pixels are transferred from the calculation unit 303 to the output buffer 400, and the registers 305 and 306 are each operated in three cycles of the basic clock.

The converted image created by the arithmetic pipeline processing as described above is read from the output buffer 400 and displayed on the display unit 500.

As described above, the number of register stages in the operation vibe line section and the operation time between adjacent registers can be independently and variably controlled at integral multiples of the basic operation clock.

In other words, it is possible to easily adapt to various configurations of the arithmetic vibe line section in order to increase the processing speed by changing the number of arithmetic stages by reviewing the arithmetic algorithm or by changing the circuit and its constituent elements to faster elements. . This increases the independence of the arithmetic unit and makes it possible to easily change the circuit configuration and its control with minimal modification.

Therefore, design changes for speeding up processing can be easily made, and the versatility of the device can be improved.

Furthermore, by making the number of register stages and the number of operation cycles easily variable, the present invention works most effectively when a plurality of circuits and elements having different processing times operate in parallel and exclusively. For example, FIG. 7 shows an example of the configuration of the calculation section 301, which is composed of a ROMA 350, a ROMB 551, and a selector 352. The calculation algorithm in this calculation unit 301 is based on two parts of the original image under certain conditions.
The area of X2 is referred to, and if not, the area of 4×4 is referred to. Also, ROMA350. R
The OMB 51 stores in advance the results of target calculations.

Here, for example, the size of ROMB551 is made larger than that of ROMA350, and the basic clock cycle is increased to 100.
ns,, ROMA 350° and ROMB 551 access times are 70 ns and 120 ns, respectively (however, when the arithmetic units 302, 303, 304 after register 305
It is assumed that each stage can be processed in 100 ns, and other delays and setup times are sufficiently small. ), when the ROMA 350 is selected, the calculation unit 30
1 can operate in one cycle of the basic clock, but R
Two cycles are required when OMB551 is selected. In such a case, in the conventional method, the number of cycles between registers could not be changed during operation, so it was necessary to fix the number of cycles to two. However, according to this invention, the number of operation cycles between registers is
Notes that can be set from 00, ROMA350 or RO
Whichever MB551 is selected, processing can be performed at the highest processing speed that is optimal for the operating time, and throughput can be improved. Therefore, when the arithmetic unit is configured in parallel with high-speed elements and low-speed elements, processing can be performed with the optimum operating time for each.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to easily respond to changes in calculation algorithms, changes in elements, etc., and to easily make design changes to speed up processing. Therefore, it is possible to provide an image conversion device with high performance.

4. Brief description of the drawings Fig. 1 is a block diagram schematically showing the configuration of an image conversion device that is an embodiment of the present invention, Fig. 2 is a circuit configuration diagram schematically showing the arithmetic control section, and Fig. 3 5 to 5 are block diagrams schematically showing the configuration setting section, FIG. 6 is a diagram shown to explain an example of the operation of pipeline processing, FIG. 7 is a block diagram showing an example of the calculation section, and FIG. FIG. 9 is a block diagram schematically showing an image processing apparatus to which the present invention is applied, and FIG. 9 is a block diagram shown to explain the outline of pipeline processing.

100... Image reading unit, 200... Image memory, 3
00... Image conversion device, 301, 302, 303°3
04... Arithmetic section, 305, 306, 307... Register, 308... Pixel selection section, 309... Arithmetic control section, 310... Configuration setting section, 310a... Latch circuit, 310b.・Address decoder, 311, 312
゜313.314...Flip-flop circuit, 315
゜316.317...JK flip-flop circuit, 3
18.319...Selector, 400...Output buffer, 500...Display section, 600...CPU.

Applicant's agent: Patent attorney Takehiko Suzue Figure 3 Figure 4

Claims (2)

[Claims] (1) Multiple arithmetic units and registers that connect these arithmetic units are operated in parallel to perform arithmetic processing on some pixels selected from the original image, and the results of the arithmetic operations are converted into a converted image. What is claimed is: 1. An image conversion device that performs image conversion by converting pixels into pixels, characterized in that the image conversion device is provided with a control means that can arbitrarily set the number of stages of the register and the operation time between each arithmetic unit. (2) Image conversion according to claim 1, wherein the control means can variably set the operation time between each calculation unit within a range of an integral multiple of the basic operation clock signal period in the image conversion device. Device.