CN104485933A - Digital pulse width modulation device used for switching power supply digital controller - Google Patents
Digital pulse width modulation device used for switching power supply digital controller Download PDFInfo
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Abstract
The invention provides a digital pulse width modulation device used for a switching power supply digital controller. The digital pulse width modulation device comprises a first-grade intercepting unit, a first filtering unit, a second-grade intercepting unit, a second filtering unit, a concatenation arithmetic unit and a basic digital pulse width modulator, wherein the first-grade intercepting unit is used for carrying out primary intercepting on an input n-bit digital signal and quantifying the input n-bit digital signal to an m1-bit first-grade intercepting signal; the first filtering unit is used for filtering the first-grade intercepting signal and generating a first-grade output signal; the second-grade intercepting unit is used for carrying out secondary intercepting on a residual (n-m1)-bit allowance signal after the treatment of the first-grade intercepting unit, and quantifying the residual (n-m1)-bit allowance signal into an m2-bit second-grade intercepting signal; the second filtering unit is used for filtering the second-grade intercepting signal and generating a second-grade output signal; the concatenation arithmetic unit is used for summing the first-grade output signal and the second-grade output signal to obtain concatenation output; the basic digital pulse width modulator is used for converting the concatenation output into a standard digital pulse signal. According to the digital pulse width modulation device, the system has low power consumption and the high resolution ratio is kept.
Description
Technical field
The present invention relates to Switching Power Supply digitial controller circuit structure design field, particularly a kind of digital pulsewidth modulation device for Switching Power Supply digitial controller.
Background technology
Along with improving constantly of integrated circuit technology level, the performance of power management processor analog controller can not correspondingly improve, and this becomes a large bottleneck of restriction battery life.And for the digitial controller of low power consumption switch power supply (SMPS), its chip area and power consumption can reduce with the raising of integrated circuit technology level, make the advantage of digitial controller manifest.In addition, compared with analog controller, digitial controller allows to realize the complex control algorithm that some analog controllers cannot realize, such as, the nonlinear algorithm of numeric field can the convergence rate of accelerating power source transducer reply disturbance, and power managed bus protocol can realize local and the system integration, efficiency of the practice respectively and monitor and important parameter automatic tuning.Moreover, digitial controller has a lot of clear superiority, and such as, the change of digitial controller to technique, voltage, temperature is insensitive, numerically controlled code reusable, is easy to be transplanted to more produce under advanced technologies, can expedite product Time To Market.
But the marketization of switch-oriented power supply digitial controller is still subject to the restriction of existing device performance and technology, can not contend with analog controller well.One of them main restricting factor cannot improve the resolution of digital pulse width modulator (DPWM) exactly effectively, and keeps rational power consumption.In high-frequency and low-consumption SMPS, digitial controller can improve system output performance, but basic DPWM makes system cloud gray model power consumption greatly increase, and counteracts the advantage of digitial controller.
For improving the resolution of DPWM, improve the performance of Switching Power Supply digitial controller, external existing some technology solve this problem, can be divided into following three classes: based on the method for delay cell, based on the method for shake and the method for hardware assist.
Controllable delay unit based on CMOS inverter can produce the interval being less than reference clock cycle.This interval can be used for improving the resolution of DPWM.First delay cell introduced in the design of PWM by the people such as Dancy.Based on this design, there is again some improving one's methods afterwards.Such as, mixing DPWM, fractional delay line DPWM, differential vibrating ring DPWM etc.DPWM power consumption based on delay cell is very low, but comparatively large by process-voltage-temperature variable effect, and high-resolution DPWM can not ensure the good linearity and chip occupying area is larger.
Based on the outer hardware resource of sheet, the digital dock administration module in such as programmable gate array (FPGA), or phase-locked loop (PLL), can realize the multiplication of clock frequency.Utilize the Clock management module in FPGA, especially advanced phase offset techniques, can produce the clock that frequency is very high.The method is applicable to pcb board level designer, can not compatible on-chip power supply.The people such as Qiu propose a kind of method that PLL utilizing two locking frequencies close produces the higher-order of oscillation, namely so-called bilateral along modulation method.Two PLL that the method utilizes frequency of oscillation to be 100MHz and 101MHz compare, and then comprehensive frequency synthesis is the clock of 10100MHz.But the PLL that design has close locking frequency like this inherently has challenge very much.The realization of this PLL must by means of extra correcting circuit, and need to ensure very high conformity of production.
Method based on shake is that a kind of multicycle is on average to produce equivalent high-resolution algorithm in essence.This kind of multiply periodic average effect realizes at the filter stage of Switching Power Supply.Look-up table (LUT) and delta-sigma are two main implementations of dither method.The people such as Peterchev propose a kind of ripple based on look-up table (LUT) and optimize DPWM, and give ripple value prediction method.Method based on LUT is easy to digital integration, and can be embedded in control algolithm comprehensive under appointment integrated circuit technology in the lump.But, follow the tracks of slowly based on the method for shake to some specific input, can to potential risks such as operation with closed ring cause convergence slow, unstable.
In sum, prior art all can ensure the effective resolution improving DPWM under the prerequisite that hardware is feasible, but the respective limitation all having performance or realize aspect.Propose a kind of can power solution requires in perfect compatible digital PwrSoC and sheet DPWM, become a problem demanding prompt solution of digital power design.
Summary of the invention
The present invention aims to provide a kind of digital pulsewidth modulation device for Switching Power Supply digitial controller, can keep high-resolution while keeping system has low-power consumption.
The invention provides a kind of digital pulsewidth modulation device for Switching Power Supply digitial controller, comprising:
First order cut position unit, for carrying out first time cut position to the n position digital signal of input, is quantified as m by the n position digital signal of input
1the first order cut position signal of position, wherein m
1be less than n;
First filter unit, for carrying out filtering to first order cut position signal, produces first order output signal;
Second level cut position unit, for remaining n-m after first order cut position cell processing
1position residual signal carries out second time cut position, and by this remaining n-m
1position residual signal is quantified as m
2the second level cut position signal of position, wherein m
2be less than n-m
1;
Second filter unit, for carrying out filtering to second level cut position signal, produces second level output signal;
Concatenation operation device, for adding and become the juxtaposition output of noise shaping according to high-order and the juxtaposed method of low level by first, second grade of output signal;
Basic digital pulse width modulator, for exporting the digital pulse signal of the standard that is converted to by juxtaposition.
Alternatively, described first order cut position unit comprises: first adder, the first truncator and the first delayed-trigger, wherein,
Described first truncator is used for carrying out cut position to the input of the first truncator;
Described first delayed-trigger is used for by the output negative feedback of the first truncator to first adder, as the input of first adder;
Described first adder be used for will the n position digital signal of input and the first delayed-trigger negative feedback to the signal plus of first adder, the output of generation is as the input of the first truncator.
Alternatively, described second level cut position unit comprises: second adder, the second truncator and the second delayed-trigger, wherein,
Described second truncator is used for carrying out cut position to the input of the second truncator;
Described second delayed-trigger is used for by the output negative feedback of the second truncator to second adder, as the input of second adder;
Described second adder is used for described remaining n-m
1position residual signal and the second delayed-trigger negative feedback are to the signal plus of second adder, and the output of generation is as the input of the second truncator.
Alternatively, the transfer function of described first filter unit is H
1=1.
Alternatively, described second filter unit comprises the 3rd adder and the 3rd delayed-trigger, second level cut position signal passes to the positive input terminal of the 3rd adder, second level cut position signal passes to the negative input end of the 3rd adder through the 3rd delayed-trigger, and the output of the 3rd adder is as the output of the second filter unit.
Compared with prior art, the present invention is by the method for employing twice cut position error of calculation, effectively under the system of guarantee has the condition of low-power consumption, meet high resolution requirement, while making second-order noise shaping have very fast convergence rate, the stability of single order delta-sigma can be reached.The complete compatible with digital design flow of integrated circuit of the present invention, under making the present invention can be aggregated into FPGA or appointment integrated circuit technology.The present invention greatly can reduce the clock frequency of DPWM in digitial controller, and makes that numerically controlled DC-DC Switching Power Supply realizes high switching frequency, low-power consumption becomes possibility.
Accompanying drawing explanation
By reading the detailed description done non-limiting example done with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
Fig. 1 is the booster type Unisolated switch power supply based on MASH delta-sigma DPWM digitial controller that the present invention proposes;
Fig. 2 is delta-sigma Error Feedback topology example figure of the prior art;
Fig. 3 is the second order MASH delta-sigma DPWM that proposes of the present invention and basic DPWM schematic diagram;
Fig. 4 is the hardware implementing line map example of the second order MASH delta-sigma DPWM that proposes of the present invention and basic DPWM;
Fig. 5 is the hardware implementing line map example of the basic DPWM that the present invention proposes.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiments of the invention are described in detail.
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
Disclosing hereafter provides many different embodiments or example is used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts of specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the present invention can in different example repeat reference numerals and/or letter.This repetition is to simplify and clearly object, itself does not indicate the relation between discussed various embodiment and/or setting.
Invention broadly provides a kind of digital pulsewidth modulation device of switch-oriented power supply digitial controller, as shown in Figure 3, this structure comprises: first order cut position unit 201, for carrying out first time cut position to the n position digital signal of input, and input signal is quantified as m
1the first order cut position signal of position, wherein m
1be less than n; First filter unit 205, for carrying out filtering to first order cut position signal, produces first order output signal; Second level cut position unit 203, for remaining n-m after first order cut position cell processing
1position residual signal carries out second time cut position, and is m by this signal quantization
2the second level cut position signal of position, wherein m
2be less than n-m
1; Second filter unit 207, for carrying out filtering to second level cut position signal, produces second level output signal; Concatenation operation device 209, for adding and become the juxtaposition output of noise shaping according to high-order and the juxtaposed method of low level by first, second grade of output signal; Basic digital pulse width modulator 210, for exporting the digital Pulse Wide Modulator of the standard that is converted into by juxtaposition.
Wherein, described first order cut position unit 201 comprises: first adder, the first truncator and the first delayed-trigger, wherein,
Described first truncator is used for carrying out cut position to the input of the first truncator;
Described first delayed-trigger is used for by the output negative feedback of the first truncator to first adder, as the input of first adder;
Described first adder be used for will the n position digital signal of input and the first delayed-trigger negative feedback to the signal plus of first adder, the output of generation is as the input of the first truncator.
Wherein, described second level cut position unit 203 comprises: second adder, the second truncator and the second delayed-trigger, wherein,
Described second truncator is used for carrying out cut position to the input of the second truncator;
Described second delayed-trigger is used for by the output negative feedback of the second truncator to second adder, as the input of second adder;
Described second adder is used for described remaining n-m
1position residual signal and the second delayed-trigger negative feedback are to the signal plus of second adder, and the output of generation is as the input of the second truncator.
Wherein, the transfer function of described first filter unit 205 is H
1=1.
Wherein, described second filter unit 207 comprises the 3rd adder and the 3rd delayed-trigger, second level cut position signal passes to the positive input terminal of the 3rd adder, second level cut position signal passes to the negative input end of the 3rd adder through the 3rd delayed-trigger, and the output of the 3rd adder is as the output of the second filter unit 207.The transfer function of the second filter unit 207 is H
2=1-z
-1.
Wherein, described basic digital pulse width modulator 210 comprises counter, comparator and R-S trigger, can the digital Pulse Wide Modulator of driving power pipe for generating.
The course of work of this digital pulsewidth modulation device is as follows:
A. the n position signal of input carried out to cut position and produces first order cut position signal, filtering is carried out to first order cut position signal, producing first order output signal;
B. to remaining n-m after first time cut position
1position residual signal carries out second time cut position, and produces second level cut position signal, carries out filtering to second level cut position signal, produces second level output signal;
C. the amplitude limit value of the signal produced after first time cut position and second level cut position signal are carried out difference operation, produce cut position error;
D. first order output signal and second level output signal are carried out juxtaposition, the juxtaposition producing noise shaping exports, and juxtaposition is exported the digital pulse signal of the standard that is converted into.
Wherein, the output signal of the described first order is V
1z (), cut position error is E
1z (), the output signal of the second level is V
2z (), cut position error is E
2(z), then:
Wherein, the signal transfer function of every grade is 1, and the noise transfer function of every grade is 1-H
ez (), U (z) is first order input signal.
Wherein, the transfer function of the described digital pulsewidth modulation method based on MASH structure can be expressed as:
V(z)＝H
1·V
1(z)+H
2·V
2(z)
＝H
1·U(z)+H
1·(1-H
e(z))·E
1(z)+H
2·(-E
2(z))+H
2·(1-H
e(z))·E
2(z)，
Wherein, H is supposed
1(1-H
e)=H
2, then first order cut position error E can be eliminated
1the impact of (z).
Wherein, H is set
1=1, H
2=1-H
e(z), and H
e(z)=z
-1, then this noise shaping equation can be expressed as the second-order noise shaping equation of standard, as follows:
V(z)＝U(z)+(1-z
-1)
2E
2(z)
Known by the above-mentioned course of work, compared with prior art, the present invention is by the method for employing twice cut position error of calculation, effectively under the system of guarantee has the condition of low-power consumption, meet high resolution requirement, while making second-order noise shaping have very fast convergence rate, the stability of single order delta-sigma can be reached.The complete compatible with digital design flow of integrated circuit of the present invention, under making the present invention can be aggregated into FPGA or appointment integrated circuit technology.The present invention greatly can reduce the clock frequency of DPWM in digitial controller, and makes that numerically controlled DC-DC Switching Power Supply realizes high switching frequency, low-power consumption becomes possibility.
Below in conjunction with several specific embodiment, the solution of the present invention is described in detail.
First, briefly introduce Error Feedback structure of the prior art, as shown in Figure 2, circuit is made up of the digital cut position unit of a digital slicer 40,42, digital feedback filtering unit 44 and two digital adders 48 and 46.May be there is the situation higher than digital full scale in the input signal Y (z) 53 of truncator (quantizer) 42, namely occur that reversion is overflowed.This situation mainly occurs in the quick decline causing exporting V (z) 54 mistake after Y (z) 53 overflows.Clipping unit 40 can limit its amplitude before signal 52 is saturated.It is as follows to there is shortcoming in this method: (1) high-order delta-sigma structure latent instability problem.Second order delta-sigma DPWM can bring latent instability under being operated in high frequency state; (2) the method part have employed the method based on delay cell, easily affects by extraneous factor, and the true resolution of DPWM is reduced.
Fig. 1 shows a specific embodiment of the present invention, is structural frames Figure 100 of a non-isolation type DC-DC boost converter (Boost Converter).MASH delta-sigma DPWM10 is main body of the present invention, is combined the pulse width modulating signal 32 that can be produced driving power metal-oxide-semiconductor 28 by Dead Time rectifier 14 and power transistor driver with basic DPWM 12.The present invention is based on inductance 36, electric capacity 38, power tube to 28 and the boost converter of load 24.The outputting analog signal of voltage divider 26 is quantized into digital signal by the analog to digital converter 20 of 10.Analog to digital converter 20 is another important component parts 110 based on digitial controller, and quantized analog signal transfers in other processing unit of controller with the form of 10 position digital signals 35.Parts 110 produce the unit of quantization error and quantification delay as one, need to be placed in whole closed-loop system to take in.The selection of analog to digital converter 20 resolution is determined by the performance such as output ripple of boost converter.And the effective resolution 32 of the digital pulse width modulator that MASH delta-sigma DPWM 10 and basic DPWM 12 forms is greater than the effective resolution of analog to digital converter 20, namely the figure place of signal 30 is higher than the figure place of signal 35, just can ensure that the output 34 of boost converter 100 can not produce limit collar oscillatory occurences.The output 35 of analog to digital converter compares with the digital ramp signal 18 of identical figure place, and the difference obtained can be delivered to certain control algolithm 16 and compensate computing, and the numeral that generation true resolution is 11 30 exports.This 11 bit digital offset 30 can regulate with the change of boost converter output voltage 34, to meet the performance requirement of Switching Power Supply transient state and stable state.
Fig. 4 shows an alternative embodiment of the invention, is the DPWM of an effective resolution 11.If input figure place n=11 in Fig. 4, gained high number of significant digit m at the corresponding levels after first order cut position in MASH structure
1=4, gained high number of significant digit m at the corresponding levels after the cut position of the second level
2=2.11 bit digital that control algolithm generates export and produce high 4 bit digital outputs by first order single order delta-sigma error feedback circuit 301.Remaining 7 signals are fed in second level delta-sigma error feedback circuit 303.Two cut position signals produce 4 and 2 output signals each via post-filtering unit 305 and 307.These two signals pass through also circuits 309 and produce the digital signal of 6, produce PWM export by basic DPWM 310.
According to signal transfer function and noise transfer function characteristic, and entire system second-order noise forming characteristics, H is set herein
1=1, H
2=1-z
-1.Need to illustrate, after first order cut position, gained high number of significant digit at the corresponding levels is high 4 MSBs, the i.e. m that MASH delta-sigma DPWM always exports
1=M '
1=4.In like manner, after the cut position of the second level, gained high number of significant digit at the corresponding levels is low 2 LSBs, the i.e. m that MASH delta-sigma DPWM always exports
2=M '
2=2.Accordingly, the signal being sent to basic DPWM input is reduced to 6.
The hardware implementing figure of basic DPWM as shown in Figure 5.This part is made up of basic counter-comparator-type DPWM.The output signal of 6 second order MASH delta-sigma DPWM is fed to this part, by a digital comparator, is f with a staircase frequency
sys=2
6f
scounter export and compare, generated the pwm signal of standard by the reset of the R-S trigger of a standard and set function.This pwm signal controls the turn-on and turn-off of power tube, and is realized the shaping of noise by the filter segment of DC-DC, and its equivalent resolution is 11.But system clock is by 2
11f
sbe reduced to 2
6f
s, dramatically reduce the clock comprehensive pressure in hardware synthesis process, and reduce power consumption.
This programme is verified simultaneously in 0.35 μm of CMOS technology and Virtex-II Pro XC2VP30FPGA, and both experimental results all meet the requirement of system to DPWM resolution, can reach 11 effective resolutions.The model set up according to embodiment of the present invention and test result meet very well.
Although describe in detail about example embodiment and advantage thereof, being to be understood that when not departing from the protection range of spirit of the present invention and claims restriction, various change, substitutions and modifications can being carried out to these embodiments.For other embodiments, those of ordinary skill in the art should easy understand maintenance scope in while, this fast transient response method also can be used for other digital control circuits.
Claims (5)
1., for a digital pulsewidth modulation device for Switching Power Supply digitial controller, it is characterized in that, comprising:
First order cut position unit (201), for carrying out first time cut position to the n position digital signal of input, is quantified as m by the n position digital signal of input
1the first order cut position signal of position, wherein m
1be less than n;
First filter unit (205), for carrying out filtering to first order cut position signal, produces first order output signal;
Second level cut position unit (203), for remaining n-m after first order cut position cell processing
1position residual signal carries out second time cut position, and by this remaining n-m
1position residual signal is quantified as m
2the second level cut position signal of position, wherein m
2be less than n-m
1;
Second filter unit (207), for carrying out filtering to second level cut position signal, produces second level output signal;
Concatenation operation device (209), for adding and become the juxtaposition output of noise shaping according to high-order and the juxtaposed method of low level by first, second grade of output signal;
Basic digital pulse width modulator (210), for exporting the digital Pulse Wide Modulator of the standard that is converted to by juxtaposition.
2. digital pulsewidth modulation device according to claim 1, is characterized in that, described first order cut position unit (201) comprising: first adder, the first truncator and the first delayed-trigger, wherein,
Described first truncator is used for carrying out cut position to the input of the first truncator;
Described first delayed-trigger is used for by the output negative feedback of the first truncator to first adder, as the input of first adder;
Described first adder be used for will the n position digital signal of input and the first delayed-trigger negative feedback to the signal plus of first adder, the output of generation is as the input of the first truncator.
3. digital pulsewidth modulation device according to claim 1, is characterized in that, described second level cut position unit (203) comprising: second adder, the second truncator and the second delayed-trigger, wherein,
Described second truncator is used for carrying out cut position to the input of the second truncator;
Described second delayed-trigger is used for by the output negative feedback of the second truncator to second adder, as the input of second adder;
Described second adder is used for described remaining n-m
1position residual signal and the second delayed-trigger negative feedback are to the signal plus of second adder, and the output of generation is as the input of the second truncator.
4. digital pulsewidth modulation device according to claim 1, is characterized in that, the transfer function of described first filter unit (205) is H
1=1.
5. digital pulsewidth modulation device according to claim 1, it is characterized in that, described second filter unit (207) comprises the 3rd adder and the 3rd delayed-trigger, second level cut position signal passes to the positive input terminal of the 3rd adder, second level cut position signal passes to the negative input end of the 3rd adder through the 3rd delayed-trigger, and the output of the 3rd adder is as the output of the second filter unit (207).
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