CN103607174B - A kind of multichannel sinusoidal signal generator and multichannel Sine Wave Signal Generation - Google Patents
A kind of multichannel sinusoidal signal generator and multichannel Sine Wave Signal Generation Download PDFInfo
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- CN103607174B CN103607174B CN201310626708.3A CN201310626708A CN103607174B CN 103607174 B CN103607174 B CN 103607174B CN 201310626708 A CN201310626708 A CN 201310626708A CN 103607174 B CN103607174 B CN 103607174B
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Abstract
The invention discloses a kind of multichannel sinusoidal signal generator and multichannel Sine Wave Signal Generation, it is possible to directly produce the sinusoidal signal of dozens or even hundreds of passage, the amplitude of each signal, frequency, initial phase all can numeral be arranged；Whole or several channel signals synchronization can be realized, phase contrast can be set between homogenous frequency signal.Wave generator circuit is made up of single programmable logic device and multi-channel analog unit；Each analogue unit is controlled by amplitude control signal, phase frequency control signal, public fundamental frequency square-wave signal；The control line of PLD driving N channel analogue unit is minimum for 2N+1 bar.The wave generator circuit of the present invention does not use memorizer, DAC, analog multiplier, and only with 1 PLD, N number of analog multichannel switch, N number of four high guaily unit, N number of double operational, hardware cost is low, analog circuit is simple.It is particularly suitable for the application scenario of one or more features such as requirement port number numerous, Channel Synchronous, channel separation.
Description
(1) technical field
The present invention relates to a kind of multichannel sinusoidal signal generator, particularly relate to up to dozens or even hundreds of, need the multichannel sinusoidal signal generator of the features such as synchronization.
(2) background technology
Sinusoidal signal generator is most basic signal generator, because it can produce the sinusoidal signal of amplitude, frequency, phase variable, it is widely used in comparatron usually used as driving source, in application scenarios such as power system simulation, sonar excitation, medical diagnosiss, need application multichannel sinusoidal signal, sometimes also needing to keep between signal synchronized relation and certain phase relation, this is accomplished by using multichannel sinusoidal signal generator.
Existing multichannel function/arbitrary waveform generator can serve as multichannel sinusoidal signal generator and uses, also there is interchannel synchronous characteristic, the wave generator circuit of each passage includes digital circuit and analog circuit two parts, the digital circuit of each passage can share a piece of PLD, and the analog circuit of each passage is then independent.Its digital circuits section is with higher rate to artificial circuit part output waveform data, and numerical portion at least needs signal line more than 10 to be connected with each tunnels analogy circuit.Being limited by the usable pins number of PLD, memory resource and components and parts hardware cost, the port number of function/Arbitrary Waveform Generator is usually no more than 4 tunnels, it is impossible to meet the application scenario that needs port number is numerous.
Can also becoming sinusoidal signal after SPWM that digital logic system produces is filtered, the connection of such analog circuit and digital circuit only has 1 signal line, controls extremely simple.SPWM is compared by the sinusoidal signal that the triangular wave that frequency is relatively high is relatively low with frequency to produce.If directly producing SPWM signal by Digital Logic, to there is the problem of three aspects: first, the frequency of the triangular wave that Digital Logic produces can not be too high, and this frequency just directly determining sinusoidal signal is relatively low, and the sinusoidal signal frequency after analog filtering is lower；Second, in a sine wave period, generation is repeatedly changed by SPWM signal condition, produces shake, and when amplitude is less, shake will have a strong impact on waveform quality；3rd, SPWM signal demand uses sinusoidal wave data, it is necessary to take memory resource, and this seriously restricts again the increase of sinusoidal signal port number in turn.Due to three of the above reason, the mode that the SPWM signal directly produced by Digital Logic produces sinusoidal signal through analog filter is seldom applied in engineering.
To sum up, existing multi channel signals method for generation cannot directly produce the signal of more than ten passages with the technology of realization, when port number increases, it is necessary to multiple programmable logic device parallels work, this can cause again the output signal cannot the problem of true synchronization because of clock not homology.
(3) summary of the invention
It is an object of the invention to provide a kind of sinusoidal signal that can directly produce to realize dozens or even hundreds of passage, the amplitude of each channel signal, frequency, initial phase all can numeral be arranged, the multichannel sinusoidal signal generator that interchannel signal can synchronize.
The object of the present invention is achieved like this, its signal generating circuit is made up of single programmable logic device and analogy signal processing unit, PLD is built-in interface circuit, clock generating circuit and control logic generating unit, interface circuit connects microprocessor respectively and controls logic generating unit, clock generating circuit connects external crystal-controlled oscillation respectively and controls logic generating unit, control logic generating unit and include parameter latch, digital controlled oscillator and data comparator, interface circuit Connecting quantity latch, parameter latch connects digital controlled oscillator and data comparator respectively, clock generating circuit, interface circuit connects digital controlled oscillator respectively, data comparator connects clock generating circuit, digital controlled oscillator and data comparator connect analogy signal processing unit respectively.
The present invention also has so some technical characteristics:
1, described interface circuit includes MPI unit and latch, and microprocessor connects MPI unit, and MPI unit connects latch, and latch connects control logical block；
2, described clock generating circuit includes digital phase-locked loop multiplier unit, even frequency division unit sum counter frequency unit, external crystal-controlled oscillation connects digital phase-locked loop multiplier unit, digital phase-locked loop multiplier unit connects even frequency division unit sum counter frequency unit respectively, and even frequency division unit sum counter frequency unit connects control logical block respectively；
3, described analogy signal processing unit includes the first order alternative analog switch being sequentially connected with, active low-pass filter unit, second level alternative analog switch, first order differential amplifier, first order passive low pass filtering unit, third level alternative analog switch, second level differential amplifier and second level passive low pass filtering unit, control logical block and connect first order alternative analog switch and third level alternative analog switch, clock generation unit connects third level alternative analog switch, second level passive low pass filtering unit output homophase is required final output after amplifying.
The model of PLD of the present invention and encapsulation can be determined according to the port number of sinusoidal signal and parameter index.The numerical portion of signal generating circuit is without using memory resource, and analog portion is without using DAC and analog multiplier.
Another object of the present invention is to provide a kind of multichannel Sine Wave Signal Generation, its signal generating circuit includes a PLD and multichannel analog signals converter unit composition, PLD is built-in interface circuit, clock generating circuit and some roads control logical block, each analogue signal converter unit only with analog multichannel switch, four high guaily unit, each 1 of double operational, do not use DAC and analog multiplier；Its step includes:
(1) universal serial bus of microprocessor is converted to internal parallel bus by interface circuit, to arrange the amplitude of each passage sinusoidal signal, frequency, initial phase；Interface circuit latches Channel Synchronous control word SYN, global synchronization SRST signal and is directly controlled by microprocessor；
(2) clock generating circuit produce system clock Fsys, Fsys even frequency division produce public fundamental frequency square-wave signal FBAS, the clock array Fout produced by Fsys binary counter frequency dividing；
(3) each control logical block produces amplitude control signal PWM, phase frequency control signal FSET；In each control logical block, array Fout compares with amplitude word, and the output (less than or equal to logical relation) of data comparator is amplitude control signal PWM；The parameter that arranges of the digital controlled oscillator with phase place preparatory function is frequency word and phase place word, and work clock is Fsys, resets and is controlled by global synchronizing signal SRST and channel synchronous signal SYN, and namely the highest order output of digital controlled oscillator be phase frequency control signal FSET；The difference that sinusoidal signal frequency is phase frequency control signal FSET and fundamental frequency square-wave signal FBAS frequency that analog converting unit produces；
(4) each analog converting unit is controlled by its exclusive amplitude control signal PWM, phase frequency control signal FSET and public fundamental frequency square-wave signal FBAS, produce sinusoidal signal, PLD drives the minimum control line of N road analogue signal converter unit to be 2N+1 bar, and the model of PLD and encapsulation can be determined according to port number and signal index；
(5) amplitude of every road sine wave, frequency, initial phase can be independently arranged；All passages can be realized or multiple interchannel sinusoidal signal synchronizes；When any two channel signals are with frequency, after Synchronization Control, the phase contrast of two signals is identical with the difference of corresponding initial phase word；
(6), after analogue signal converter unit increases isolation DC-DC power source chip and high speed photo coupling/magnetic coupling, it may be achieved the electrical isolation of analogue signal converter unit, the application scenario of electrical isolation is met；Multichannel is isolated sinusoidal signal series connection use, the waveshape signal of wide variation can be produced, the complicated wave form signal of multi-components superposition can be produced, harmonic signal can be produced.
In the programmable logic device, the universal serial bus from microprocessor is converted to internal parallel bus BUS to the present invention by interface circuit, to arrange each channel signal parameter；Interface circuit arranges each channel reset control bit SYN, microprocessor the global reset signal SRST introduced also by latch.Clock generating circuit produces following three kinds of clock signals: one is system clock Fsys, and two is the fundamental frequency square wave FBAS obtained after even frequency division by Fsys, and three is Fsys clock array Fout out after binary counter divides.As used the digital phase-locked loop resource of FPGA to improve Fsys frequency, it is possible to the corresponding frequency range improving output sinusoidal signal.
In the programmable logic device, multi-channel control logic unit circuit is identical, and each control logical block produces amplitude control signal PWM and phase frequency control signal FSET.Microprocessor arranges amplitude word, frequency word, phase place word；Clock array Fout compared with amplitude word, data comparator be amplitude control signal PWM less than or equal to output, amplitude word determines sinusoidal signal amplitude and resolution thereof；Frequency word and phase place word arrange parameter as two of the digital controlled oscillator with initial phase preparatory function, the work clock of digital controlled oscillator is Fsys, the highest order output of digital controlled oscillator is phase frequency control signal FSET, frequency word determines frequency and the resolution thereof of output sinusoidal signal, and phase place word determines initial phase and the resolution of output sinusoidal signal；Each digital controlled oscillator controlling logical block can through the fully synchronized reset of SRST, it is also possible to be separately provided one or more reset SYN, so can realize that the multichannel sinusoidal signal of output is fully synchronized or a few roads synchronize.Phase frequency control signal FSET frequency should be not less than the frequency of fundamental frequency square wave FBAS, and both differences are the frequency of output sinusoidal signal.In order to improve the waveform quality of output sinusoidal signal, the positive and negative pulse width error of requirement phase frequency control signal FSET is little, pulse jitter is little, the requirement of sinusoidal signal waveform quality defines the difference of the upper frequency limit of phase frequency control signal FSET, the upper frequency limit of phase frequency control signal FSET and fundamental frequency square wave FBAS frequency and is sinusoidal signal frequency range.
All analogy signal processing units are identical, each analogy signal processing unit and control logical block one_to_one corresponding, analogue signal converter unit is controlled by the amplitude control signal PWM of its correspondence, phase frequency control signal FSET and public fundamental frequency square wave FBAS, produces intended sinusoidal signal through analog circuit conversion.Amplitude control signal PWM drives 2 inputs of first order alternative analog switch to connect benchmark and ground respectively, and switch common port signal obtains a DC voltage VDC being directly proportional to PWM pulsewidth after active low-pass filter.Fundamental frequency square-wave signal FBAS drives the public termination VDC of second level alternative analog switch, 2 outputs of switch connect two inputs of first order differential amplifier respectively, the output of this differential amplifier through first order passive low pass filter after signal be SINL, SINL homophase amplify after be SINF signal.Phase frequency control signal FSET drives the public termination SINF of third level alternative analog switch, 2 outputs of switch connect 2 inputs of second level differential amplifier, and the output of this differential amplifier filters through second level passive low pass, homophase is required sinusoidal signal SIN after amplifying.Structural parameters and the function of two grades of differential amplifiers are identical, with alternative analog switch with the use of, it is achieved the multiplying of switch common port signal and switching drive signal, it is achieved analog multiplier function；Two-stage passive low ventilating filter all adopts 9 rank passive low pass elliptic filters, and passband external spectrum signal high-decibel is decayed.Analogy signal processing unit circuit topological structure is simple, it is easy to accomplish.
Ultimate principle according to signal conversion: the frequency of SIN is the difference of the frequency of phase frequency control signal FSET and fundamental frequency square-wave signal FBAS；The amplitude of SIN and the amplitude proportional of DC voltage VDC, be namely directly proportional to amplitude word；After two homogenous frequency signals synchronize, the phase contrast between sinusoidal signal is identical with corresponding two phase frequency control signal FSET phase contrasts, namely identical with the difference of corresponding two phase place words.
Beneficial effects of the present invention has:
1. multichannel sinusoidal signal generator of the present invention, is not take up memory resource (can realize by single CPLD), says and be prone to extended channel number from logical resource inside its digital logic system；PLD drives the control line producing N channel sinusoidal signal minimum for 2N+1 bar, without outside extended menory resource, says and be prone to expansion port number the pin resource of PLD.The CPLD of monolithic low cost can provide the control controlling several passages, and the Large Copacity FPGA of many pin package then provides the control signal controlling passages up to a hundred.
2. multichannel sinusoidal signal generator of the present invention, its analogue signal converter unit circuit is simple, Jin Yong tri-road alternative analog switch, four high guaily unit, each 1 of double operational, it is not necessary to using waveform conversion DAC, amplitude to arrange DAC, analog multiplier, such analog circuitry system device cost is low；And digital logic system adopts single programmable logic device, its cost is on a declining curve, and a kind of multichannel sinusoidal signal generator hardware cost that therefore present invention narrates is relatively low.
3. multichannel sinusoidal signal generator of the present invention, when each interchannel sinusoidal signal is with frequency, starts synchronous reset and controls, and multichannel sinusoidal signal generator is exactly a heterogeneous sinusoidal signal generator.
4. controlling owing to every passage sinusoidal signal is only limited by PWM, FSET, FBAS logical signal, it is easy to realize the electrical isolation of multi channel signals, upgrading becomes multichannel isolation sinusoidal signal generator, meets the application scenario of electrical isolation.Multichannel isolation sinusoidal signal generator exports use of can connecting, to produce the waveshape signal of wide variation, to form the complicated wave form signal of multi-components superposition, it is also possible to forming harmonic signal, application is more extensive.
5. multichannel sinusoidal signal generator of the present invention, when the changeless application-specific of the amplitude of each sinusoidal signal, frequency, phase place, can be decided to be constant by the pulsewidth word of each digital control logic unit, frequency word, phase place word.Reducing the resource requirement to FPGA/CPLD on hardware, eliminate the microprocessor system including keyboard & display, the hardware cost of signal generator is substantially reduced, and debugging work load is substantially reduced.
(4) accompanying drawing explanation
Fig. 1 is the multichannel function/arbitrary waveform generator structured flowchart of prior art.
Fig. 2 is the multichannel sinusoidal signal generator universal architecture block diagram of the present invention.
Fig. 3 is the 56 passage sinusoidal signal generator the general frame implementing the present invention.
Fig. 4 is that the single channel shown in Fig. 3 controls logical block theory diagram.
Fig. 5 is the theory diagram of the analogue signal converter unit shown in Fig. 3.
Fig. 6 is the 120 passage sinusoidal signal generator the general frame implementing the present invention.
Fig. 7 is the 10 passage sinusoidal signal generator the general frame implementing the present invention.
(5) detailed description of the invention
Three kinds of better embodiment of the present invention are introduced below in conjunction with accompanying drawing.
Embodiment one:
In conjunction with Fig. 3,56 passage sinusoidal signal generation circuit of the present invention are made up of monolithic FPGA device EP2C8Q208 and 56 identical analogue signal converter units of circuit.FPGA in Fig. 2 is built-in interface circuit, clock system circuit for generating, control logical block that 56 line structures are identical.External crystal-controlled oscillation frequency is 40MHz, is 280MHz system clock Fsys through digital phase-locked loop frequency multiplication；FBAS is Fsys frequency after even number is the fundamental frequency square wave of 140kHz, through many pin outputs of FPGA to meet the driving requirement of 56 passages after FBAS buffering.Its operation principle is discussed in detail at Summary.
Fig. 4 is the control logical block theory diagram in Fig. 3, and its operation principle is discussed in detail at Summary, and each control logical block produces amplitude control signal PWM and phase frequency control signal FSET.Microprocessor arranges 16Bit amplitude word, 40Bit frequency word, 12Bit phase place word；Between phase frequency control signal FSET normal operating frequency range 140kHz ~ 240kHz, each passage sinusoidal signal frequency range is in 100kHz.
Fig. 5 is the analogy signal processing unit theory diagram in Fig. 3, and its operation principle is discussed in detail at Summary, and each analogue signal converter unit is controlled by exclusive PWM, FSET and public FBAS, is transformed into intended sine wave.The relevant feature of analogue unit is as follows: three road alternative analog switches are recommended to adopt 74HC4053, and four high guaily unit is recommended to adopt TL084, and double operational is recommended to adopt TL082；2 grades of passive low ventilating filters all adopt 9 rank low-pass elliptic filter, and the first order filter passband frequency producing SINL signal is 150kHz, it is achieved the band connection frequency of the second level wave filter of signal difference frequency is 110kHz.
Embodiment two:
In conjunction with Fig. 6,120 passage sinusoidal signal generation circuit of the present invention are made up of monolithic FPGA device EP2C20F484 and 120 identical analogue signal converter units of circuit.FPGA in Fig. 5 is built-in interface circuit, clock system circuit for generating, control logical block that 120 line structures are identical, through many pins outputs of FPGA to meet the driving requirement of 120 passages after FBAS buffering.Each control logical block with analog converting Elementary Function index with consistent with the first embodiment.
Embodiment three:
In conjunction with Fig. 7,10 passage sinusoidal signal generation circuit of the present invention are made up of single CPLD device EPM1270T144 and 10 identical analogue signal converter units of circuit.
CPLD in Fig. 7 is built-in interface circuit, clock generating circuit, control logical block that 10 line structures are identical.50MHz external crystal-controlled oscillation frequency immediate system clock Fsys, does not use digital phase-locked loop；Fsys is fundamental frequency square wave FBAS after 2048 divide.Each control logical block produces amplitude control signal PWM and phase frequency control signal FSET.Microprocessor arranges each channel parameters: 16Bit amplitude word, 36Bit frequency word, 12Bit phase place word, and phase frequency control signal FSET normal working frequency is variable within the scope of 20kHz on FBAS frequency base, and each passage produces sinusoidal signal frequency range in 20kHz.Analogue signal converter unit.The relevant feature of analog circuit is as follows: three road alternative analog switches are recommended to adopt ADG1433, and four high guaily unit is recommended to adopt AD8513, and double operational is recommended to adopt AD8512；2 passive low ventilating filter structural parameters are identical, it is recommended that adopt 9 rank low-pass elliptic filter, and passband frequency range is 22kHz.
Above-described it is only specific embodiments of the invention, the protection domain being not intended to limit the present invention, all any amendments within present invention spirit and principle, equivalent replacement, improvement etc., should be included within protection scope of the present invention.
Claims (5)
1. a multichannel sinusoidal signal generator, it is characterized in that it is made up of single programmable logic device and analogy signal processing unit, PLD is built-in interface circuit, clock generating circuit and control logical block, interface circuit connects microprocessor respectively and controls logical block, clock generating circuit connects external crystal-controlled oscillation respectively and controls logical block, control logical block and include parameter latch, digital controlled oscillator and data comparator, interface circuit Connecting quantity arranges circuit, parameter setting circuit connects digital controlled oscillator and data comparator respectively, clock generating circuit, interface circuit connects digital controlled oscillator respectively, data comparator connects clock generating circuit, digital controlled oscillator and data comparator connect analogy signal processing unit respectively.
2. a kind of multichannel sinusoidal signal generator according to claim 1, it is characterized in that described interface circuit includes MPI unit and latch, microprocessor connects MPI unit, and MPI unit connects latch, and latch connects logic control element.
3. a kind of multichannel sinusoidal signal generator according to claim 2, it is characterized in that described clock generating circuit includes digital phase-locked loop multiplier unit, even frequency division unit sum counter frequency unit, external crystal-controlled oscillation connects digital phase-locked loop multiplier unit, digital phase-locked loop multiplier unit connects even frequency division unit sum counter frequency unit respectively, and even frequency division unit sum counter frequency unit connects logic control element respectively.
4. a kind of multichannel sinusoidal signal generator according to claim 3, it is characterized in that the first order alternative analog switch that described analogy signal processing unit includes being sequentially connected with, active low-pass filter unit, second level alternative analog switch, first order differential amplifier, first order passive low pass filtering unit, third level alternative analog switch, second level differential amplifier and second level passive low pass filtering unit, logic control element connects first order alternative analog switch and third level alternative analog switch, clock generation unit connects second level alternative analog switch, second level passive low pass filtering unit output homophase is required final output after amplifying.
5. a kind of multichannel Sine Wave Signal Generation of a kind of multichannel sinusoidal signal generator according to claim 1, its signal generating circuit includes a PLD and multichannel analog signals converter unit composition, PLD is built-in interface circuit, clock generating circuit and some roads control logical block, it is characterised in that it comprises the following steps:
(1) universal serial bus of microprocessor is converted to internal parallel bus by interface circuit, to arrange the amplitude of each passage sinusoidal signal, frequency, initial phase；Interface circuit latches Channel Synchronous control word SYN, global synchronization SRST signal by microprocessor control；
(2) clock generating circuit produce system clock Fsys, Fsys even frequency division produce public fundamental frequency square-wave signal FBAS, the clock array Fout produced by Fsys binary counter frequency dividing；
(3) each control logical block produces amplitude control signal PWM, phase frequency control signal FSET；In each control logical block, array Fout compares with amplitude word, and the output of data comparator is amplitude control signal PWM；The input of the digital controlled oscillator with phase place preparatory function is frequency word and phase place word, and work clock is Fsys, resets and is controlled by global synchronizing signal SRST and channel synchronous signal SYN, and namely the highest order output of digital controlled oscillator be phase frequency control signal FSET；The difference that sinusoidal signal frequency is phase frequency control signal FSET and fundamental frequency square-wave signal FBAS frequency that analog converting unit produces；
(4) each analog converting unit is controlled by its exclusive amplitude control signal PWM, phase frequency control signal FSET and public fundamental frequency square-wave signal FBAS, produce sinusoidal signal, PLD drives the minimum control line of N road analogue signal converter unit to be 2N+1 bar, and the model of PLD and encapsulation can be determined according to port number and signal index；
(5) amplitude of every road sine wave, frequency, initial phase can be independently arranged；All passages can be realized or multiple interchannel sinusoidal signal synchronizes；After any two channel signals are with frequency, after Synchronization Control, the phase contrast of two signals is identical with the difference of corresponding initial phase word；
(6), after analogue signal converter unit increases isolation DC-DC power source chip and high speed photo coupling/magnetic coupling, it may be achieved the electrical isolation of analogue signal converter unit, the application scenario of electrical isolation is met；Multichannel is isolated sinusoidal signal series connection use, the waveshape signal of wide variation can be produced, the complicated wave form signal of multi-components superposition can be produced, harmonic signal can be produced.
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| CN104811193A (en) * | 2015-04-20 | 2015-07-29 | 电子科技大学 | Phase adjustable multi-channel clock signal synthesizing device |
| CN106656048B (en) * | 2016-08-16 | 2023-08-18 | 嘉兴市纳杰微电子技术有限公司 | High linearity sine wave generator followed by multiplying clock multiple |
| CN106327973A (en) * | 2016-08-22 | 2017-01-11 | 中国电子科技集团公司第四十研究所 | Multi-channel low-frequency signal generating and conditioning teaching experiment circuit and method |
| CN108226586A (en) * | 2017-12-20 | 2018-06-29 | 中国航天科工集团八0厂 | A kind of method for generating sophisticated signal needed for test simulation circuit unit |
| CN108449084B (en) * | 2018-02-11 | 2020-06-30 | 中国科学院高能物理研究所 | Method and system for multi-channel phase automatic correction of digital BPM (Business Process management) sampling data |
| CN109367569B (en) * | 2018-09-10 | 2021-03-12 | 广州大铁锐威科技有限公司 | Detection data synchronous acquisition system and method for measuring geometrical parameters of track |
| CN109450440A (en) * | 2018-10-29 | 2019-03-08 | 中惠医疗科技（上海）有限公司 | Multichannel phase generator |
| CN110855290B (en) * | 2019-11-12 | 2023-06-23 | 中电科思仪科技股份有限公司 | Circuit and method for automatically synchronizing output channels of arbitrary waveform generator |
| CN112436748B (en) * | 2020-11-17 | 2022-09-30 | 天津津航计算技术研究所 | Digital sine wave circuit based on CPLD |
| CN115657788B (en) * | 2022-12-27 | 2023-03-17 | 北京超摩科技有限公司 | High-speed multiphase clock generating circuit, serializer and electronic equipment |
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