CN104124964A - Delay phase-locked loop and method for improving accuracy of delay phase-locked loop - Google Patents
Delay phase-locked loop and method for improving accuracy of delay phase-locked loop Download PDFInfo
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- CN104124964A CN104124964A CN201410376028.5A CN201410376028A CN104124964A CN 104124964 A CN104124964 A CN 104124964A CN 201410376028 A CN201410376028 A CN 201410376028A CN 104124964 A CN104124964 A CN 104124964A
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Abstract
The invention provides a delay phase-locked loop and a method for improving the accuracy of the delay phase-locked loop, wherein the accuracy of the delay phase-locked loop is at least doubled on the premise of increasing a domain area and power consumption as little as possible. The delay phase-locked loop comprises a DLL delay chain, wherein the DLL delay chain comprises a DLL coarse tuning chain and a DLL fine tuning chain. The delay phase-locked loop is characterized in that a middle phase generator used for generating the middle phase of the odd clock and the even clock of an input clock signal is arranged between the DLL coarse tuning chain and the DLL fine tuning chain. The method for improving the accuracy of the delay phase-locked loop comprises is generating two clock signals which are an odd-even clock and a middle clock, through the even clocks and the odd clocks of two input clock signals, wherein the phase difference of the odd-even clock and the middle clock is one half of the phase difference of the even clock and the odd clock.
Description
Technical field
The invention provides a kind of method of delay locked loop and raising delay locked loop precision.
Background technology
Delay phase-locked loop (DLL) is widely used in interface between microprocessor, memory interface, chip and the clock distributing network of large scale integrated circuit, be used for the deflection problem that clock synchronous solves clock, make the clock delay between chip internal or chip have enough surpluses, thereby improve the sequential function of system.
Along with the increase of application system clock frequency, more and more higher to the requirement of DLL degree of regulation, because it has directly determined the maximum phase demodulation error of DLL.Traditional DLL is made up of DLL time delay chain (comprising coarse adjustment chain and fine setting chain), delay of feedback, phase discriminator, DLL controller and output driver.Its operation principle is as follows:
The input clock of DLL produces time delay clock after time delay chain, and time delay clock produces feedback clock after delay of feedback, and feedback clock and input clock all input to phase discriminator.Phase discriminator is sampled, is compared input clock and feedback clock, and comparative result is exported to DLL controller.DLL controller is adjusted the time delay of Variable delay chain according to comparative result, realize the phase alignment of feedback clock and input clock, thereby realizes the output clock with input clock with specific delay requirement.
In the specific implementation of DLL time delay chain, the system of considering requires to have longer time delay length and less time delay step-length to time delay chain simultaneously, and DLL time delay chain is divided into DLL coarse adjustment chain and DLL fine setting chain conventionally.Coarse delay chain circuit is subject to the control of DLL controller circuitry coarse adjustment control bit signal, the even clock and the strange clock signal that produce two outs of phase are exported to fine setting chain circuit, the i.e. step-length t of coarse adjustment circuit for this reason of the phase difference of these two clock signals, fine setting chain circuit is also subject to DLL control circuit vernier control position signal controlling simultaneously, two input clock signals are postponed with comprehensive, and generation precision is the Single-end output clock of t/n (n is the figure place of fine setting chain circuit).The phase accuracy of this signal is the degree of regulation of DLL circuit.
In existing DLL structure, in order to obtain more high-precision clock, often need the figure place that increases DLL fine setting chain to realize, need larger power consumption and chip area.
Summary of the invention
A kind of method that the invention provides delay locked loop and raising delay locked loop precision, under the prerequisite of the least possible increase chip area and power consumption, improves at least one times by delay locked loop precision.
Concrete technical solution of the present invention is as follows:
This delay locked loop comprises DLL time delay chain, described DLL time delay chain comprises DLL coarse adjustment chain and DLL fine setting chain, between described DLL coarse adjustment chain and DLL fine setting chain, is provided with the intermediate phase generator for generation of the intermediate phase clock of the strange clock of input clock signal and even clock.
Described intermediate phase generator comprises the first inverter for receiving strange clock signal and for receiving the second inverter of even clock signal, the output of the first inverter is connected with the input of strange time delay clock processing unit and middle delay process unit respectively, and the output of the second inverter is connected with the input of even time delay clock processing unit and middle delay process unit respectively; The output of described strange time delay clock processing unit, even time delay clock processing unit is connected with the 3rd inverter, and the output of middle delay process unit is connected with the 4th inverter; Described strange time delay clock processing unit, even time delay clock processing unit are by the inverter of three series connection triple gate composition of connecting again; In the middle of described, delay process unit comprises strange inverter group, even inverter group, inverter and triple gate, the input of strange inverter group is connected with the output of the first inverter, output is connected with the input of inverter, the input of even inverter group is connected with the output of the second inverter, output is connected with the input of inverter, and the output of inverter is connected with triple gate; Described strange inverter group and even inverter group are by the inverter composition of two series connection.
The inverter of described the first inverter, the second inverter and strange time delay clock processing unit, even time delay clock processing unit, middle delay process unit is identical, the triple gate of strange time delay clock processing unit, even time delay clock processing unit, middle delay process unit is identical, and the 3rd inverter is identical with the 4th inverter.
The method of this raising delay locked loop precision comprises the following steps: the even clock of two clock signals and strange clock by input produce two clock signals, respectively odd even clock and middle clock, the phase difference of odd even clock and middle clock is even clock and the poor half of odd clock phases,, the poor original input phase clock for t is become to the clock of phase difference output t/2, the precision of former time delay clock just can become t/2n from t/n accordingly, and precision doubles.
The even clocks of described two clock signals by input and strange clock produce odd even clock and middle clock signal specifically:
1] even input signal clock and the strange clock of input signal are inputted respectively in different inverters;
2] even the input signal through inverter processing clock is inputted respectively to even time delay clock processing unit and middle delay process unit, strange the input signal through inverter processing clock is inputted respectively to strange time delay clock processing unit and middle delay process unit;
3] clock signal of even time delay clock processing unit output and the clock signal of strange time delay clock processing unit output are inputed to simultaneously and in inverter, increase driving force and export odd even clock signal;
In the middle of entering in step 2 the strange clock of input signal of delay process unit and even clock enter generate after same inverter one be subject to simultaneously even clock and strange clock control and phase place in the middle of the two clock signal, time delay clock in the middle of called after, described time delay clock inputs to the triple gate of a conducting always, increases driving force more afterwards finally export middle clock signal by inverter.
The invention has the advantages that:
The method of delay locked loop provided by the invention and raising delay locked loop precision, under the prerequisite of the least possible increase chip area and power consumption, improves at least one times by delay locked loop precision.
Brief description of the drawings
Fig. 1 is existing delay locked loop principle schematic;
Fig. 2 is delay locked loop principle schematic of the present invention;
Fig. 3 is the structure chart of intermediate phase generator;
Fig. 4 is waveform schematic diagram;
Fig. 5 is signal corresponding relation figure;
Description of reference numerals:
The 0-the second inverter; 1,2,3,11,12,13,14,15,21,22,23-inverter; 4,16,24-triple gate; The 5-the three inverter; The 17-the four inverter; The 20-the first inverter.
Embodiment
Core of the present invention is that newly-increased intermediate phase produces circuit, the effect that intermediate phase produces circuit is according to strange clock and the even clock of input, produce the clock of the two intermediate phase, the poor original input phase clock for t is become to the clock of phase difference output t/2.The precision of former like this time delay clock just can become t/2n from t/n accordingly, and precision doubles.
The even clock of input signal inputs to inverter 0, and the strange clock of input signal inputs to inverter 20 simultaneously; Even clock is by rear inverter 1,2,3 and the inverter 11,12,13 of outputing to of inverter 0 simultaneously; Strange clock is by rear inverter 21,22,23 and the inverter 14,15,13 of outputing to of inverter 20 simultaneously; Inverter 12,15 exports inverter 13 to simultaneously, produce one be subject to simultaneously even clock and strange clock control and phase place in the middle of the two clock signal, time delay clock in the middle of called after.
The output of inverter 3 and 23 is the even time delay clock of called after and strange time delay clock respectively, and they input to respectively triple gate 4 and 24.Triple gate 4 and 24 suspension control signal odd evens are selected to control, and select the even time delay clock of output or strange time delay clock, increase driving force afterwards finally export odd even clock signal by inverter 5.Wherein odd even selects signal in former DLL controller circuitry, to obtain easily.Middle time delay clock inputs to the triple gate of a conducting always equally, increases driving force afterwards finally export middle clock signal by inverter 17.
In order to mate transmission delay and even clock, the equilibrium control of strange clock to middle clock, inverter 0～3,11～15 and 20～23 is all selected the device of same size, triple gate 4,16 and 24 is selected the device of same size, and output drives inverter 5 and 7 to select the device of same size.
Be described below in conjunction with waveform schematic diagram:
Signal corresponding relation: clkeven: even clock, clkodd: strange clock, clkeb: even time delay clock, clkmb: middle time delay clock, clkob: strange time delay clock, clkeo: odd even clock, clkmid: middle clock.
Clkeven and clkodd produce clkeb and clkob by identical time delay, and produce phase place between the clkmb between the two simultaneously.Clkeb and clkob are by selecting driver output clkeo, clkmb driver output clkmid.
Can find out, this is t for the phase difference of input clkeven and clkodd, and after intermediate phase generator circuit, the clkeo of output and clkmid phase difference only become original half t/2.
DLL fine setting chain can adopt traditional multiple circuit structure, after clock signal delay that its major function is is t two phase differences is comprehensive, is converted to the clock signal that a precision step-length is t/n, and wherein n is fine setting chain circuit figure place.
The DLL fine setting chain output signal eye pattern that can be adopted respectively thus traditional DLL structure and improvement DLL structure, the precision of this output signal represents the output clock precision of whole DLL.As shown in Figure 5: the corresponding DLL traditional structure of upper side waveform, clkeven: even clock, clkodd: strange clock, clkfine: time delay clock, the corresponding DLL that inserts intermediate phase generator of lower side waveform improves structure, clkeo: odd even clock, clkmid: middle clock, clkfine: time delay clock.
Can find out from eye pattern, while adopting DLL traditional structure, the phase difference of clkeven and clkodd is t, and the precision step-length of output time delay clock is t/n; And while adopting improved DLL structure, the phase difference of clkeo and clkmid is t/2, the precision step-length of output time delay clock is t/2n.
Claims (5)
1. a delay locked loop, comprise DLL time delay chain, described DLL time delay chain comprises DLL coarse adjustment chain and DLL fine setting chain, it is characterized in that: between described DLL coarse adjustment chain and DLL fine setting chain, be provided with the intermediate phase generator for generation of the intermediate phase clock of the strange clock of input clock signal and even clock.
2. delay locked loop according to claim 1, it is characterized in that: described intermediate phase generator comprises the first inverter for receiving strange clock signal and for receiving the second inverter of even clock signal, the output of the first inverter is connected with the input of strange time delay clock processing unit and middle delay process unit respectively, and the output of the second inverter is connected with the input of even time delay clock processing unit and middle delay process unit; The output of described strange time delay clock processing unit, even time delay clock processing unit is connected with the 3rd inverter, and the output of middle delay process unit is connected with the 4th inverter; Described strange time delay clock processing unit, even time delay clock processing unit are by the inverter of three series connection triple gate composition of connecting again; In the middle of described, delay process unit comprises strange inverter group, even inverter group, inverter and triple gate, the input of strange inverter group is connected with the output of the first inverter, output is connected with the input of inverter, the input of even inverter group is connected with the output of the second inverter, output is connected with the input of inverter, and the output of inverter is connected with triple gate; Described strange inverter group and even inverter group are by the inverter composition of two series connection.
3. delay locked loop according to claim 2, it is characterized in that: the inverter of described the first inverter, the second inverter and strange time delay clock processing unit, even time delay clock processing unit, middle delay process unit is identical, the triple gate of strange time delay clock processing unit, even time delay clock processing unit, middle delay process unit is identical, and the 3rd inverter is identical with the 4th inverter.
4. one kind is improved the method for delay locked loop precision, it is characterized in that, comprise the following steps: the even clock of two clock signals and strange clock by input produce two clock signals, respectively odd even clock and middle clock, the phase difference of odd even clock and middle clock is even clock and the poor half of odd clock phases, makes the precision of former time delay clock become t/2n from t/n accordingly.
5. the method for raising delay locked loop precision according to claim 4, is characterized in that: the even clocks of described two clock signals by input and strange clock produce odd even clock and middle clock signal specifically:
1] even input signal clock and the strange clock of input signal are inputted respectively in different inverters;
2] even the input signal through inverter processing clock is inputted respectively to even time delay clock processing unit and middle delay process unit, strange the input signal through inverter processing clock is inputted respectively to strange time delay clock processing unit and middle delay process unit;
3] clock signal of even time delay clock processing unit output and the clock signal of strange time delay clock processing unit output are inputed to simultaneously and in inverter, increase driving force and export odd even clock signal; In the middle of entering in step 2 the strange clock of input signal of delay process unit and even clock enter generate after same inverter one be subject to simultaneously even clock and strange clock control and phase place in the middle of the two clock signal, time delay clock in the middle of called after, described time delay clock inputs to the triple gate of a conducting always, increases driving force more afterwards finally export middle clock signal by inverter.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105281755A (en) * | 2015-11-17 | 2016-01-27 | 西安华芯半导体有限公司 | Delay phase-locked loop and filtering updating and control method of the same |
| WO2017157026A1 (en) * | 2016-03-16 | 2017-09-21 | 珠海全志科技股份有限公司 | Clock duty-cycle calibration and frequency-doubling circuit |
| CN109379077A (en) * | 2015-03-25 | 2019-02-22 | 华为技术有限公司 | A kind of time-to-digit converter in phaselocked loop |
| CN110212912A (en) * | 2019-06-06 | 2019-09-06 | 复旦大学 | A kind of multiple delay phase-locked loop with High-precision time-to-digital converter |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101951260B (en) * | 2010-10-11 | 2012-10-17 | 上海电力学院 | Digital delay phase locked loop circuit |
| CN103684438B (en) * | 2013-11-25 | 2016-06-08 | 龙芯中科技术有限公司 | Delay phase-locked loop |
| CN204119210U (en) * | 2014-08-01 | 2015-01-21 | 西安华芯半导体有限公司 | A kind of delay locked loop |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109379077A (en) * | 2015-03-25 | 2019-02-22 | 华为技术有限公司 | A kind of time-to-digit converter in phaselocked loop |
| CN105281755A (en) * | 2015-11-17 | 2016-01-27 | 西安华芯半导体有限公司 | Delay phase-locked loop and filtering updating and control method of the same |
| CN105281755B (en) * | 2015-11-17 | 2018-05-08 | 西安紫光国芯半导体有限公司 | A kind of delay phase-locked loop and its filtering more new control method |
| WO2017157026A1 (en) * | 2016-03-16 | 2017-09-21 | 珠海全志科技股份有限公司 | Clock duty-cycle calibration and frequency-doubling circuit |
| US10181844B1 (en) | 2016-03-16 | 2019-01-15 | All Winner Technology Company, Limited | Clock duty cycle calibration and frequency multiplier circuit |
| CN110212912A (en) * | 2019-06-06 | 2019-09-06 | 复旦大学 | A kind of multiple delay phase-locked loop with High-precision time-to-digital converter |
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Address after: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Applicant after: XI'AN UNIIC SEMICONDUCTORS Co.,Ltd. Address before: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Applicant before: Xi'an Sinochip Semiconductors Co., Ltd. |
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