CN102412806A - Farrow filter based on logic circuit and implementation method for Farrow filter - Google Patents

Farrow filter based on logic circuit and implementation method for Farrow filter Download PDF

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Publication number
CN102412806A
CN102412806A CN2011103257428A CN201110325742A CN102412806A CN 102412806 A CN102412806 A CN 102412806A CN 2011103257428 A CN2011103257428 A CN 2011103257428A CN 201110325742 A CN201110325742 A CN 201110325742A CN 102412806 A CN102412806 A CN 102412806A
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cut position
group
farrow filter
data
coefficient
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CN102412806B (en
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陈永红
岳亮
苟春茂
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Nanjing Zhongxing Software Co Ltd
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ZTE Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/0009—Time-delay networks
    • H03H17/0018—Realizing a fractional delay
    • H03H17/0027—Realizing a fractional delay by means of a non-recursive filter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters
    • H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
    • H03H17/0635—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
    • H03H17/0642—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being arbitrary or irrational

Abstract

The invention discloses a Farrow filter based on a logic circuit and an implementation method for the Farrow filter. The Farrow filter comprises a gating switch for controlling a working mode of the Farrow filter according to proportional relation between a configured input data sampling rate and a configured output data sampling rate, an interpolation filtering device for performing interpolation filtering on input data under the control of the gating switch, and performing bit-cutting operation on middle data during interpolation filtering according to a first set bit width to acquire a first type of fixed point data, and an extraction filtering device for performing extraction filtering on the input data under the control of the gating switch, and performing the bit-cutting operation on the middle data during extraction filtering according to a second set bit width to acquire a second type of fixed point data. By the Farrow filter, the problem that the conventional Farrow filter does not support online rate configuration because of inflexibility of hardware architecture is solved; and resource occupation rate of hardware is reduced by the bit-cutting operation on the middle data.

Description

Farrow filter and its implementation of logic-based circuit
Technical field
The present invention relates to the communications field, in particular to Farrow filter and its implementation of a kind of logic-based circuit.
Background technology
The maximum characteristics of Farrow filter are to utilize one group of fixed coefficient to realize the conversion of any sampling rate of signal.Its theoretical foundation is based on continuous time model, and is as shown in Figure 1.
The effect of Farrow filter is exactly that process with Fig. 1 realizes at numeric field fully: 1) use desirable DAC and analog filter h a(t) digital signal x (k) is recovered to be as the criterion primary signal y a(t); 2) to y a(t) resample and obtain the digital signal y (l) after the speed conversion.Filter h aThe time domain and the frequency domain quality of performance decision output signal (t).
The digitlization of this simulation process can be derived and proof by mathematical theory fully, can obtain interpolation and the Mathematical Modeling that extracts Farrow filter under two kinds of situation respectively.Can obtain the most abstract logic hardware implementation model according to Mathematical Modeling.
1, under the interpolation situation
Time coefficient μ lThe time interval between expression current output sample and the nearest before input sample, and to the input sample cycle T InNormalization, as shown in Figure 2.
The interpolation structure of Farrow filter is as shown in Figure 3.The corresponding one group of input sample of the calculating of each output sample y (l), this group input sample is through M+1 sub-filters C i(z) filtering, the v of output m(n l) respectively with (2 μ l-1) mMultiply each other and the output sample after obtaining resampling of adding up.Subfilter all is operated under the input sample speed, v m(n l) and (2 μ l-1) mMultiplying be operated in output sampling rate under.
2, under the extraction situation
Time coefficient μ kRepresent the time interval between current input sample and the nearest before output sample, and to output sampling period T OutNormalization.The drawing-out structure of Farrow filter is as shown in Figure 4.The corresponding one group of input sample of the calculating of each output sample y (l), each sample and each self-corresponding (2 μ k-1) mAfter multiplying each other, utilize the index bound that these group data are carried out segmentation and add up, promptly in each output sampling period, accumulator will calculate good one group of data (promptly importing sample) and send into subfilter C i(z), the output sample y (l) after subfilter output results added promptly obtains extracting.In this structure, input sample and (2 μ k-1) mMultiplying and accumulator computing be operated under the input sample speed, subfilter all be operated in output sampling rate under.
When the Farrow filter is used for doing the mark time-delay, do not change signal sampling speed, its Mathematical Modeling and logic realization block diagram can be regarded as a special case under the interpolation situation.
The background of front is described as the Mathematical Modeling and the corresponding software realization flow of Farrow filter, and this all has research and analysis on a lot of disclosed technical data.Research about the Farrow filter at present concentrates on how to seek more excellent bank of filters C mostly i(z) to satisfy under certain or some signal processing applications scenes performance requirement better to time domain and frequency domain.
The Farrow filter generally is divided into software and two kinds of implementations of logic hardware.Software is realized promptly at digital signal processor (Digital Signal Processor; Be called for short DSP) etc. the processor chips the inside use software program to carry out Floating-point Computation and realization, this is suitable for that non real-time calculates or the real-time calculating of data sampling speed very low the time.Software realizes that floating-point carries out entirely, uses the Mathematical Modeling of Farrow filter to calculate fully and gets final product.
The Farrow filter process of real-time intermediate-freuqncy signal is fit to use the logical circuit of fixed point to realize that this moment, data sampling speed was high, and dsp processor is difficult to the so big operand of burden.But also there is not fixed point logical circuit implementation at present about the Farrow filter.
To existing Farrow filter hardware framework underaction in the correlation technique, do not support the problem of online configured rate, effective solution is not proposed at present as yet.
Summary of the invention
To above-mentioned existing Farrow filter hardware framework underaction, do not support the problem of online configured rate, the invention provides Farrow filter and its implementation of a kind of logic-based circuit, to address the above problem at least.
According to an aspect of the present invention; A kind of Farrow filter of logic-based circuit is provided; Comprise: gating switch is used for according to the input data sampling speed of configuration and the proportionate relationship of dateout sampling rate the mode of operation of control Farrow filter; The filtering interpolation device is used under the control of gating switch, and the input data are carried out filtering interpolation, and in the process of filtering interpolation, sets bit wide according to first middle data are carried out the cut position operation, obtains first kind fixed-point data; Decimation filtering apparatus is used under the control of gating switch, and the input data are carried out filtering extraction, and in the process of filtering extraction, sets bit wide according to second middle data are carried out the cut position operation, obtains second type of fixed-point data.
Preferably, the shared one group of subfilter of filtering interpolation device and decimation filtering apparatus, this subfilter are supported coefficient Configuration Online function.
Preferably, the filtering interpolation device comprises one group of subfilter, one group of multiplier and one group of adder; Wherein, each multiplier of one group of multiplier is connected with a multiplication cut position device, and this multiplication cut position device is used for setting bit wide according to first the output result of above-mentioned multiplier is carried out the cut position operation, obtains first kind fixed-point data.
Preferably, the time coefficient that each multiplier receives is uiv=2*ui-I, wherein, and ui=μ i* I, μ i=mod (D*l, I)/I, the difference multiple of I for setting, the extracting multiple of D for setting; L is the data directory of output clock zone; Mod () is for getting surplus calculating.
Preferably, the coefficient c of each subfilter in above-mentioned one group of subfilter m' (n) adopt following formula to confirm: c m ′ ( n ) = Round ( c m ( n ) × 2 M × ( 2 NI I ) m ) , Wherein, M is the quantification bit wide of said one group of subfilter coefficient, c m(n) be the normalization floating-point coefficient of m sub-filters; N is a sequence numbering, n=0, and 1 ..., N-1; N is a sequence length; M is the integer more than or equal to 0; Round () is the calculating that rounds up; NI is the first setting bit wide,
Figure BDA0000101568350000022
Be provided with an addition cut position device between above-mentioned one group of adder and the data output end, this addition cut position device is used to clip the low M position by the result of one group of adder computing.
Preferably; Above-mentioned Farrow filter also comprises the first logic hardware system; This first logic hardware system comprises: first restorer, be used for the first logic hardware system is resetted, and uiv, rd_flag and temporary variable t are reset to initial value; Wherein, rd_flag is that address designation is read in the clock zone conversion; The first variable processor is used for when each output clock arrives, t=t+D being set, and whether judging t greater than I, if t=t-I is set, and rd_flag is added 1, if not, t and rd_flag are constant; Very first time coefficient maker is used to be provided with the corresponding said time coefficient uiv=2*t-I of each output clock.
Preferably, decimation filtering apparatus comprises one group of subfilter, one group of multiplier, one group of accumulator and one group of adder; Wherein, each multiplier of above-mentioned one group of multiplier is connected with a multiplication cut position device, and this multiplication cut position device is used for setting bit wide according to second the output result of multiplier is carried out the cut position operation, and with the corresponding accumulator of the input of the data behind the cut position; Be provided with the cut position device that adds up between each accumulator and the subfilter, the cut position device that adds up is used for the result of accumulator output is carried out the cut position operation, obtains second type of fixed-point data.
Preferably, the time coefficient that above-mentioned each multiplier receives is udv=2*ud-D, wherein, and ud=μ d* D, μ d=mod (I*k, D)/D, the difference multiple of I for setting, the extracting multiple of D for setting; K is the data directory of output clock zone; Mod () is for getting surplus calculating.
Preferably, the coefficient c of each subfilter in one group of subfilter m' (n) adopt following formula to confirm: c m ′ ( n ) = Round ( c m ( n ) × 2 M × ( 2 ND I ) m × ( 2 NP × I D ) ) , Wherein, M is the quantification bit wide of above-mentioned one group of subfilter coefficient, c m(n) be the normalization floating-point coefficient of m sub-filters; M is the integer more than or equal to 0; Round () is the calculating that rounds up; ND is the second setting bit wide,
Figure BDA0000101568350000032
NP is the cut position bit wide of cut position device of adding up,
Figure BDA0000101568350000033
Be provided with an addition cut position device between above-mentioned one group of adder and the data output end, addition cut position device is used to clip the low M position by the result of one group of adder computing.
Preferably; Above-mentioned Farrow filter also comprises the second logic hardware system; This second logic hardware system comprises: second restorer, be used for the second logic hardware system is resetted, and udv, clr_flag and temporary variable t are reset to initial value; Wherein, clr_flag is the zero clearing sign of accumulator feedback input end and effective sign of dateout; The second variable processor is used for when each output clock arrives, t=t+I being set, and whether judging t greater than D, if t=t-D is set, and clr_flag is put 1, if not, t and rd_flag are constant; The second time coefficient maker is used to be provided with each output clock time corresponding coefficient udv=2*t-D.
According to a further aspect in the invention, a kind of implementation method of Farrow filter of logic-based circuit is provided, has comprised:, confirmed the mode of operation of Farrow filter according to the input data sampling speed of configuration and the proportionate relationship of dateout sampling rate; When mode of operation is filtering interpolation, in the process of filtering interpolation, sets bit wide according to first middle data are carried out the cut position operation, obtain first kind fixed-point data; When mode of operation is filtering extraction, in the process of filtering extraction, sets bit wide according to second middle data are carried out the cut position operation, obtain second type of fixed-point data.
Through the present invention; Be employed in the filtering middle data are carried out the cut position operation, reduced hardware resource and taken, so this Farrow filter can be applied to the processing of (comprising live signal and non real-time signal) of various signals; Simultaneously; The signal processing controllable gain of this framework, thus the Farrow filter hardware framework underaction in the correlation technique solved, do not support the problem of online configured rate.Through gating switch is set, can realize the interpolation and the extract function of Farrow filter are merged, make the function of above-mentioned Farrow filter no longer single, strengthened the market competitiveness of Farrow filter.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 is the original theory model according to the Farrow filter of correlation technique;
Fig. 2 is according to the Farrow filter input and output sampled point of correlation technique and the time domain sketch map of time coefficient;
Fig. 3 is the mathematical theory implementation model according to Farrow filter under the interpolative mode of correlation technique;
Fig. 4 is the mathematical theory implementation model according to Farrow filter under the decimation pattern of correlation technique;
Fig. 5 is the Farrow Filter Structures block diagram according to the logic-based circuit of the embodiment of the invention;
Fig. 6 is the filtering interpolation schematic representation of apparatus according to the embodiment of the invention;
Fig. 7 is the concrete sketch map according to the filtering interpolation device of the embodiment of the invention;
Fig. 8 is the generation method sketch map according to the time coefficient of the filtering interpolation device input of the embodiment of the invention;
Fig. 9 is the structured flowchart according to the logic hardware system of the generation interpolation time coefficient of the embodiment of the invention;
Figure 10 is the sketch map according to the decimation filtering apparatus of the embodiment of the invention;
Figure 11 is the concrete sketch map according to the decimation filtering apparatus of the embodiment of the invention;
Figure 12 is the generation method sketch map according to the time coefficient of the decimation filtering apparatus input of the embodiment of the invention;
Figure 13 is the structured flowchart that extracts the logic hardware system of time coefficient according to the generation of the embodiment of the invention;
Figure 14 is the implementation method flow chart according to the Farrow filter of the logic-based circuit of the embodiment of the invention;
Figure 15 is the concrete structure sketch map according to the Farrow filter of the logic-based circuit of the embodiment of the invention.
Embodiment
Hereinafter will and combine embodiment to specify the present invention with reference to accompanying drawing.Need to prove that under the situation of not conflicting, embodiment and the characteristic among the embodiment among the application can make up each other.
The embodiment of the invention provides Farrow filter and its implementation of a kind of logic-based circuit, this technology with the Farrow filter applies in logical circuit, to improve the operational capability that the Farrow filter is handled in real time.
When adopting logical circuit to realize the Farrow filter, need consider following problems at least:
1, time coefficient μ lAnd μ kFixed point and in line computation, by finding out on the Mathematical Modeling that these two time coefficients are floating datas of the real-time change confirmed by the input and output sampling rate, need carry out that fixed point is handled and real-time online calculates to time coefficient;
2, the cut position of time coefficient and data multiplication is handled.Can find out from Mathematical Modeling; The different power powers of time coefficient and the input or the dateout of subfilter have the calculating of multiplying each other; This can bring in the fixed point process and calculate being multiplied of bit wide, and full accuracy computation is impossible basically, needs rational cut position operation.
Based on the problems referred to above; Present embodiment provides a kind of Farrow filter of logic-based circuit; The Farrow Filter Structures block diagram of logic-based circuit according to the embodiment of the invention as shown in Figure 5, this filter comprises: gating switch 52, interpolation filter 54 and decimation filter 56.Wherein,
Gating switch 52 is used for according to the input data sampling speed of configuration and the proportionate relationship of dateout sampling rate, the mode of operation of control Farrow filter;
Filtering interpolation device 54 is connected with gating switch 52, is used under the control of gating switch 52; The input data are carried out filtering interpolation; And in the process of filtering interpolation, set bit wide according to first middle data are carried out the cut position operation, obtain first kind fixed-point data;
Decimation filtering apparatus 56 is connected with gating switch 52, is used under the control of gating switch 52; The input data are carried out filtering extraction; And in the process of filtering extraction, set bit wide according to second middle data are carried out the cut position operation, obtain second type of fixed-point data.
Present embodiment is through carrying out the cut position operation to middle data in filtering; Having reduced hardware resource takies; Therefore this Farrow filter can be applied to the processing of (comprising live signal and non real-time signal) of various signals, simultaneously, and the signal processing controllable gain of this framework; Thereby solved the Farrow filter hardware framework underaction in the correlation technique, do not supported the problem of online configured rate.Through gating switch is set, can realize the interpolation and the extract function of Farrow filter are merged, make the function of above-mentioned Farrow filter no longer single, strengthened the market competitiveness of Farrow filter.
Wherein, the mode of operation of the Farrow filter in the embodiment of the invention can be the interpolation mode of operation, also can be to extract mode of operation, and this interpolation mode of operation comprises a special case, i.e. mark delay working pattern.Fig. 6 is the filtering interpolation schematic representation of apparatus according to the embodiment of the invention, and is as shown in Figure 6, and this device comprises one group of subfilter C i(z), one group of multiplier (is used among the figure The expression) and one group of adder (use among the figure
Figure BDA0000101568350000052
Expression), wherein,
Each multiplier in above-mentioned one group of multiplier is connected with a multiplication cut position device, and above-mentioned multiplication cut position device is used for setting bit wide according to first the output result of multiplier is carried out the cut position operation, obtains first kind fixed-point data.
At time coefficient 2 μ that specifically realize each multiplier reception among Fig. 6 with logical circuit i-1 o'clock, the time coefficient that each multiplier receives was uiv=2*ui-I, wherein, and ui=μ i* I,
Figure BDA0000101568350000053
The difference multiple of I for setting, the extracting multiple of D for setting; L is the data directory of output clock zone; Mod () is for getting surplus calculating.This l is exactly a continually varying integer, and 0 to N-1, suppose that Tout is the dateout sampling period, 0 corresponding 0 constantly, and in the 1 corresponding 1*Tout moment, 2 corresponding 2*Tout are constantly.
General fixed point realizes that filter process requires all to guarantee that the gain of signal in the passband is certain fixed gain that 0dB or user need, and generally there is not this problem in Floating-point Computation.Consider this problem, in the embodiment of the invention, adopt above-mentioned bank of filters C i(z) and time coefficient quantize, and time coefficient is carried out the multiplication cut position, and accumulator is carried out operation such as cut position, accomplish comprehensive trade-off and compensation to floating data.Based on this; The concrete sketch map of the filtering interpolation device according to the embodiment of the invention as shown in Figure 7, this device improves on the basis of Fig. 6, promptly between above-mentioned one group of adder and data output end, is provided with an addition cut position device; Based on Fig. 7, above-mentioned subfilter C i(z) coefficient c m' (n) adopt following formula to confirm: c m ′ ( n ) = Round ( c m ( n ) × 2 M × ( 2 NI I ) m ) , Wherein, M is the quantification bit wide of one group of subfilter coefficient, c m(n) be the normalization floating-point coefficient of m sub-filters; N is a sequence numbering, n=0, and 1 ..., N-1; N is a sequence length; M is the integer more than or equal to 0; Round () is the calculating that rounds up; NI is the first setting bit wide,
Figure BDA0000101568350000062
Above-mentioned addition cut position device is used to clip the low M position by the result of one group of adder computing.This mode has guaranteed that the gain of signal in the passband is certain fixed gain that 0dB or user need.
In order to obtain the time coefficient that each multiplier receives in the above-mentioned filtering interpolation device; Present embodiment is employed in and a logic hardware system is set in the Farrow filter realizes, referring to the generation method sketch map of the time coefficient of filtering interpolation device input shown in Figure 8, during initialization; Uiv, rd_flag and temporary variable t are reset to initial value; The initial value of each amount is 0 in the present embodiment, and wherein, rd_flag is that address designation is read in the clock zone conversion; When each output clock arrives, t=t+D is set, and whether judges t, if t=t-I is set, and rd_flag is added 1, if not, t and rd_flag are constant greater than I; Each output clock time corresponding coefficient uiv=2*t-I is set.
Based on the time coefficient generation method among above-mentioned Fig. 8; Present embodiment adopts the logic hardware system to realize this method, the structured flowchart of logic hardware system as shown in Figure 9, and this logic hardware system comprises: restorer 92; Be used for this logic hardware system is resetted; Uiv, rd_flag and temporary variable t are reset to initial value, and wherein, rd_flag is that address designation is read in the clock zone conversion; Variable processor 94 links to each other with restorer 92, is used for when each output clock arrives, t=t+D being set, and whether judging t greater than I, if t=t-I is set, and rd_flag is added 1, if not, t and rd_flag are constant; Time coefficient maker 96 links to each other with variable processor 94, is used to be provided with each output clock time corresponding coefficient uiv=2*t-I.
Figure 10 is the sketch map according to the decimation filtering apparatus of the embodiment of the invention, and is shown in figure 10, and this device comprises one group of subfilter, one group of adder of one group of multiplier; Wherein, one group of subfilter C i(z), one group of multiplier (is used among the figure
Figure BDA0000101568350000063
Expression), one group of accumulator (representing with ∑ among the figure) and one group of adder (are used among the figure
Figure BDA0000101568350000064
Expression), wherein, each multiplier of above-mentioned one group of multiplier is connected with a multiplication cut position device, and multiplication cut position device is used for setting bit wide according to second the output result of multiplier is carried out the cut position operation, and with the corresponding accumulator of the input of the data behind the cut position; Be provided with the cut position device that adds up between each accumulator and the subfilter, the cut position device that adds up is used for the result of accumulator output is carried out the cut position operation, obtains second type of fixed-point data.
The concrete sketch map of decimation filtering apparatus according to the embodiment of the invention shown in figure 11; This device improves on the basis of Figure 10; Be to be provided with an addition cut position device between above-mentioned one group of adder and the data output end, based on Figure 11, time coefficient 2 μ that each multiplier receives d-1 o'clock, the time coefficient that each multiplier receives was udv=2*ud-D, wherein, and ud=μ d* D, μ d=mod (I*k, D)/D, the difference multiple of I for setting, the extracting multiple of D for setting; K is the data directory of output clock zone; Mod () is for getting surplus calculating.
The coefficient c of each subfilter in above-mentioned one group of subfilter m' (n) adopt following formula to confirm: c m ′ ( n ) = Round ( c m ( n ) × 2 M × ( 2 ND I ) m × ( 2 NP × I D ) ) , Wherein, M is the quantification bit wide of one group of subfilter coefficient, c m(n) be the normalization floating-point coefficient of m sub-filters; M is the integer more than or equal to 0; Round () is the calculating that rounds up; ND is the second setting bit wide,
Figure BDA0000101568350000071
NP is the cut position bit wide of cut position device of adding up,
Figure BDA0000101568350000072
This addition cut position device is used to clip the low M position by the result of one group of adder computing.This mode has guaranteed that the gain of signal in the passband is certain fixed gain that 0dB or user need.
In order to obtain the time coefficient that each multiplier receives in the above-mentioned decimation filtering apparatus; Present embodiment is employed in and a logic hardware system is set in the Farrow filter realizes; Generation method sketch map referring to the time coefficient of decimation filtering apparatus shown in Figure 12 input; During initialization, udv, clr_flag and temporary variable t are reset to initial value, the initial value of each amount is 0 in the present embodiment; Wherein, clr_flag is the zero clearing sign of accumulator feedback input end and effective sign of dateout; When each output clock arrives, t=t+I is set, and whether judges t, if t=t-D is set, and clr_flag is put 1, if not, t and rd_flag are constant greater than D; Each output clock time corresponding coefficient udv=2*t-D is set.
Based on the time coefficient generation method among above-mentioned Figure 12; Present embodiment adopts the logic hardware system to realize this method, the structured flowchart of logic hardware system shown in figure 13, and this logic hardware system comprises: restorer 132; Be used for the logic hardware system is resetted; Udv, clr_flag and temporary variable t are reset to initial value, and wherein, clr_flag is the zero clearing sign of accumulator feedback input end and effective sign of dateout; Variable processor 134 links to each other with restorer 132, is used for when each output clock arrives, t=t+I being set, and whether judging t greater than D, if t=t-D is set, and clr_flag is put 1, if not, t and rd_flag are constant; Time coefficient maker 136 links to each other with variable processor 134, is used to be provided with each output clock time corresponding coefficient udv=2*t-D.
Above-mentioned extracting multiple D, interpolation multiple I and filter device group C i(z) but Configuration Online.
Above-mentioned filtering interpolation device 54 and decimation filtering apparatus 56 can shared one group of subfilters, and this subfilter is supported coefficient Configuration Online function.This mode can be saved hardware, reduces cost.
Corresponding to above-mentioned Farrow filter, present embodiment also provides a kind of implementation method of Farrow filter of logic-based circuit.With Farrow filter shown in Figure 5 is example, and referring to the implementation method flow chart of the Farrow filter of logic-based circuit shown in Figure 14, this method may further comprise the steps:
Step S142 according to the input data sampling speed of configuration and the proportionate relationship of dateout sampling rate, confirms the mode of operation of Farrow filter;
Step S144 when mode of operation is filtering interpolation, in the process of filtering interpolation, sets bit wide according to first middle data is carried out the cut position operation, obtains first kind fixed-point data;
Step S146 when mode of operation is filtering extraction, in the process of filtering extraction, sets bit wide according to second middle data is carried out the cut position operation, obtains second type of fixed-point data.
Present embodiment is through carrying out the cut position operation to middle data in filtering; Having reduced hardware resource takies; Therefore this Farrow filter can be applied to the processing of (comprising live signal and non real-time signal) of various signals, simultaneously, and the signal processing controllable gain of this framework; Thereby solved the Farrow filter hardware framework underaction in the correlation technique, do not supported the problem of online configured rate.According to the input data sampling speed of configuration and the proportionate relationship of dateout sampling rate; Confirm the mode of operation of Farrow filter; Can realize the interpolation and the extract function of Farrow filter are merged; Make the function of above-mentioned Farrow filter no longer single, strengthened the market competitiveness of Farrow filter.
Describe below in conjunction with a preferred embodiment, the preferred embodiment has combined the foregoing description and preferred implementation.Present embodiment provides a kind of Farrow filter of logic-based circuit; The concrete structure sketch map of the Farrow filter of logic-based circuit shown in figure 15, the extracting multiple D in the Farrow filter of this logic-based circuit, interpolation multiple I and filter device group C i(z) but online reconfiguration, simultaneously, present embodiment through increased by three gating switch controller K1, K2 and K3 compatible interpolation and extract two kinds of mode of operations; Wherein, when switch is set to shown in the dotted line, for being operated in decimation pattern; When switch is set to shown in the solid line, for being operated in interpolative mode.Present embodiment has increased configurable cut position after accumulator and multiplier, this one side can be used for adapting to the finite data bit wide needs of fixed-point computation, is used for satisfying the demand for control of processing gain on the other hand.
K2 bypass multiplication and ND cut position, the interpolation scene of corresponding D≤I when K3 bypass accumulator and NP cut position, K1 enable multiplication and NI cut position.K2 enables multiplication and ND cut position, and K3 enables accumulator and NP cut position, the extraction scene of corresponding D＞I in the time of K1 bypass multiplication and NI cut position.
It is identical with the structure of interpolation mode of operation that the Farrow filter is used for the time-delay of decimal sampling, and just the calculating of time coefficient and configuration and NI cut position bit wide computational methods are different.
Interpolation multiple I and extracting multiple D can be used for representing the proportionate relationship of inputoutput data sampling rate, so interpolation can be expressed as following formula (1) and (2) respectively with the time coefficient that extracts under two kinds of situation.
μ i＝mod(D*l，I)/I (1)
μ d＝mod(I*k，D)/D (2)
Mod representes to get surplus calculating.These two time coefficients all are the floating-point decimals, and logic hardware can't directly be calculated it.Here it is amplified I times and D times respectively and all become the surplus calculating of getting of fixed point, this can calculate in the logic hardware the inside.Following formula (3) and (4), calculative time coefficient becomes the ui and the ud of fixed point integer.Corresponding in Figure 15 with 2 μ of corresponding Mathematical Modeling i-1 and 2 μ d-1 amplify respectively I doubly and D doubly become 2*ui-I and 2*ud-D.
ui＝μ i*I＝mod(D*l，I) (3)
ud＝μ d*D＝mod(I*k，D) (4)
Because time coefficient has enlarged I times and D times respectively; It is doubly beneficial with the D multiplication that data processing must be reduced I; Here I and D are divided into integral number power and decimal two parts of 2, wherein the direct cut position of 2 integral number power part gets final product, and the bit wide of intercepting is shown in formula (5) and (6).
Figure BDA0000101568350000081
Figure BDA0000101568350000082
2^NI and 2^ND are the configurable cut position computing that rounds up among Figure 15, and low NI and the low ND position of clipping upper level result of calculation is to offset 2 integral number power gain.Remaining fractional part gain is handled in the quantification of filter coefficient.
M is the quantification bit wide of subfilter coefficient, and interpolation filter coefficient quantization formula is shown in (7).
c m ′ ( n ) = round ( c m ( n ) × 2 M × ( 2 NI I ) m ) - - - ( 7 )
Round in the formula (7) is the calculating that rounds up,
Figure BDA0000101568350000092
be used for offsetting time coefficient and amplify the doubly influence of the fractional part of back except that 2 integral number power of I.This formula the right is the normalization floating-point coefficient, and the formula left side is the fixed point coefficient, and coefficient is a data sequence vector, and n is a sequence numbering, generally is exactly 0 to N-1, and N is a sequence length.
The difference of drawing-out structure and interpolation structure is that there is an accumulator circuit in drawing-out structure; Accumulator circuit can bring D/I gain doubly; Identical with the processing thought of time coefficient gain; Also be split as integral number power and decimal two parts of 2, wherein the gain of 2 integral number power is by cut position control, and the cut position bit wide is shown in formula (8).
Figure BDA0000101568350000093
2^NP is the configurable cut position computing that rounds up among Figure 15, clips 2 the integral number power gain to offset that accumulator brings of low NP position that accumulation calculating increases.The fractional part gain of accumulator is also placed in the filter coefficient quantification to be handled, and like this, the quantification of decimation filter coefficient is shown in formula (9).
c m ′ ( n ) = round ( c m ( n ) × 2 M × ( 2 ND I ) m × ( 2 NP × I D ) ) - - - ( 9 )
Figure BDA0000101568350000095
in the formula (9) is used for offsetting and extracts the doubly decimal gain effects of back except that 2 integral number power of time coefficient amplification D, and
Figure BDA0000101568350000096
is used for offsetting the decimal gain effects of accumulator circuit except that 2 integral number power.
The influence that low M position neutralizing filter quantizes is clipped in the last output of filter, shown in the 2^M cut position of Figure 15.
So far, the gain of whole fixed-point processing is all handled by the quantification of cut position control and subfilter coefficient, and filter can theoretically guarantee to be 0dB or other fixed gain to the gain of inband signaling.
Formula (5), (6), (7), (8) and (9) are the fixed-point constant for being confirmed by interpolation multiple I and extracting multiple D and bank of filters floating-point coefficient all; The constant of just being confirmed by the different application scene, these values can be by the Farrow filter fixed point logic realization device that support and control software on the veneer or host computer computed in software obtain and Configuration Online defines to Fig. 5.
The interpolation of formula (3) and (4) definition and the time coefficient that extracts under two kinds of situation are the constants of the real-time change relevant with output or input sample clock sequence, need in logic hardware, calculate in real time and upgrade.
Under the interpolation situation, input data sampling speed is lower than the output sampling rate, and subfilter is operated in the input sample clock zone, need be transformed into the output clock zone and multiply each other and sue for peace with time coefficient through buffer memory to obtain dateout.The clock zone conversion writes according to the input clock order with being buffered in the input clock territory, but the sampling clock speed of reading side is high, the v in output sampling clock territory m(n l) at time sampling dimension and time coefficient μ lClose association is arranged, and all (D*l, result I) equally is cyclic variation with mod.
Under the interpolation situation of D≤I, use logical circuit to calculate the interpolation time coefficient in real time according to above-mentioned method shown in Figure 8, and the data of clock zone translation cache are read control.Uiv=2*ui-I among Fig. 8 is the calculating input that Figure 15 needs, and rd_flag is that address designation is read in the clock zone conversion.During logic hardware system reset, uiv, rd_flag and temporary variable t all are reset to initial value, and when each output clock arrived, assignment t=t+D also judged t and the size of I: if t is not less than I, the address of reading of the sign of t=t-I, and rd_flag so adds 1; If t is less than I, so t and rd_flag sign to read the address all constant.Each output clock all calculates the uiv value according to uiv=2*t-I and gives Figure 15 and calculate.
Under the extraction situation; Input data sampling speed is lower than the output sampling rate; Subfilter is operated in output sampling clock territory; Need add up and control the output result to the input data sementation of accumulator circuit, i.e. the input that adds up of accumulator needs control signal that a zero clearing resets and accumulator is imported data sementation and will export the result and be transformed into and export the sampling clock territory.
Under the extraction situation of D＞I, use logical circuit to calculate the extraction time coefficient in real time according to above-mentioned method shown in Figure 12, and add up input and the output that adds up of accumulator circuit are carried out zero clearing and kept operation.Udv=2*ud-D among Figure 12 is the calculating input that Figure 15 needs, and clr_flag is the accumulator circuit feedback input zero clearing sign that adds up, and clr_flag effectively identifies for the dateout that adds up simultaneously, this moment with the accumulation result sample conversion to exporting clock zone.During logic hardware system reset, udv, clr_flag and temporary variable t all are reset to initial value, and when each output clock arrived, assignment t=t+I also judged t and the size of D: if t is not less than D, the sign of t=t-D, and clr_flag so puts 1; If t is less than D, t and clr_flag sign is all constant so.Each output clock all calculates the udv value according to udv=2*t-D and gives Figure 15 and calculate.
Be that decimal delays time doubly that input and output speed does not change under the application scenarios in the time of I=D; This moment time constant time difference of sampled point and the previous input sample point of physical meaning after for time-delay to the normalization in sampling period; This moment, time coefficient was a constant, need not real-time online and calculated.The Farrow logic realization structure that decimal is doubly delayed time under the scene is consistent with interpolative mode; Just time coefficient is a constant that need not after the quantification of line computation; The integral number power that the quantizing process of this time constant is according to 2 amplifies calculating; The inferior temporal resolution with the decimal time-delay of the power that amplifies is relevant, and the cut position bit wide of NI equals the quantification bit wide of time coefficient simultaneously, guarantees that the gain of time coefficient multiplication is constant.
Data in the above-mentioned Farrow filter can be implemented in the conversion and the processing controls of two different sample clock zones.No matter be under extraction or the interpolation situation; Data all relate to conversion and the control from the input sample clock zone to output sampling clock territory; This processing is not simple clock zone conversion, therefore can adopt metadata cache mechanism, when promptly this Farrow filter is operated in interpolative mode; Can buffer storage be set at the data output end of each sub-filters of Figure 15, be used for the data of the corresponding subfilter output of buffer memory; When this Farrow filter is operated in decimation pattern, can a buffer storage be set at the output of each accumulator of Figure 15, be used for the data of the corresponding accumulator output of buffer memory.Wherein, the read-write control of metadata cache is relevant with the speed conversion multiple.
But above-mentioned Farrow filter online reconfiguration parameter can realize that floating number is carried out fixed point to be handled, and can directly apply in the exploitation and design of ASIC and FPGA.Above-mentioned Farrow filter need not confirmed interpolation multiple I and extracting multiple D and subfilter group coefficient value before realization, these parameters can be confirmed according to the practical application scene and the configuration relevant parameter makes apparatus of the present invention operate as normal as required by the user.
Design and realize that above-mentioned Farrow filter need confirm the deal with data bit wide; The dimension of subfilter group and exponent number; The expression bit wide of I, D, M, NI, ND, NP and subfilter fixed point coefficient is confirmed the processing bit wide of multiplier, accumulator and subfilter according to these bit wides.
Wherein, the data processing bit wide is generally 16 or 18 at present.The dimension of subfilter group and exponent number need be obtained by Algorithm Analysis and emulation assessment under the certain designed demand.Each subfilter is exactly a symmetry or antisymmetric common FIR filter in the logical design.The quantification bit wide of I, D and M is generally 16 or 18.NI, ND and NP are cut position bit wide parameter, generally are no more than 5, because 5 the intercepting scopes that just can represent 0～31.
Promptly can obtain Farrow wave filter application of logic circuit module shown in Figure 15 based on these parameters of confirming and basic calculating and control module.Being used to of K1, K2 and K3 selected interpolation or decimation pattern, can Fixed Design in practical application for only supporting a certain pattern.
The control of reading of the calculating of interpolation time coefficient and clock zone translation cache designs according to the flow process of Fig. 8, extracts the flow process that time coefficient and accumulator control according to Figure 12 and designs.
Farrow filter based on the aforesaid way design; System in this Farrow filter and veneer Control Software require configuration I, D and M according to application scenarios, and calculating and dispose NI, ND, NP and subfilter coefficient according to above-mentioned correlation formula is that suitable value promptly can normally be moved and worked.From above description, can find out; The foregoing description aims to provide Farrow filter fixed point computing technique; Extracting multiple D, interpolation multiple I and filter device group Ci (z) are disclosed in this technology but the implementation of online reconfiguration for example, is provided with the cut position device at assigned address; Simultaneously, in this design, also can compatible interpolation with extract two kinds of mode of operations; The fixed point method of the Farrow filter relevant parameter that comprises the some cut position parameters among Figure 15 that above-mentioned formula (5), (6), (7), (8) and (9) are described, these methods have guaranteed that in theory the processing gain of Farrow filter can be controlled by the user fully; The fixed point real-time computing technique of the interpolation time coefficient that above-mentioned formula (1) and Fig. 8 provide, and clock zone conversion and control metadata cache read control method; The fixed point real-time computing technique of the extraction time coefficient that above-mentioned formula (2) and Figure 12 provide, and accumulator circuit real-time control method under the decimation pattern based on the implementation of these formula, can be accomplished above-mentioned Farrow Design of Filter.This Farrow filter is that the decimal of using always is doubly delayed time and decimal sampling rate transformed filter, has a wide range of applications in the signal processing field, especially in the digital intermediate frequency signal of the communications field is handled, significant application value is arranged.
Above embodiment has realized a kind of general Farrow filter realization framework through a series of fixed points and may command cut position; Entire process controllable gain and reduction intermediate treatment bit wide; And then reduce hardware resource and take, simultaneously, this framework is applicable to that various many speed sampled signals handle.
Obviously; It is apparent to those skilled in the art that above-mentioned each module of the present invention or each step can realize that they can concentrate on the single calculation element with the general calculation device; Perhaps be distributed on the network that a plurality of calculation element forms; Alternatively, they can be realized with the executable program code of calculation element, carried out by calculation element thereby can they be stored in the storage device; And in some cases; Can carry out step shown or that describe with the order that is different from here, perhaps they are made into each integrated circuit modules respectively, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The above is merely the preferred embodiments of the present invention, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (11)

1. the Farrow filter of a logic-based circuit is characterized in that, comprising:
Gating switch is used for controlling the mode of operation of said Farrow filter according to the input data sampling speed of configuration and the proportionate relationship of dateout sampling rate;
The filtering interpolation device is used under the control of said gating switch, and the input data are carried out filtering interpolation, and in the process of said filtering interpolation, sets bit wide according to first middle data are carried out the cut position operation, obtains first kind fixed-point data;
Decimation filtering apparatus is used under the control of said gating switch, and said input data are carried out filtering extraction, and in the process of said filtering extraction, sets bit wide according to second middle data are carried out the cut position operation, obtains second type of fixed-point data.
2. Farrow filter according to claim 1 is characterized in that, the shared one group of subfilter of said filtering interpolation device and said decimation filtering apparatus, said subfilter are supported coefficient Configuration Online function.
3. Farrow filter according to claim 1 is characterized in that, said filtering interpolation device comprises one group of subfilter, one group of multiplier and one group of adder; Wherein,
Each multiplier of said one group of multiplier is connected with a multiplication cut position device, and said multiplication cut position device is used for setting bit wide according to first the output result of said multiplier is carried out the cut position operation, obtains first kind fixed-point data.
4. Farrow filter according to claim 3 is characterized in that,
The time coefficient that said each multiplier receives is uiv=2*ui-I, wherein, and ui=μ i* I, μ i=mod (D*l, I)/I, the difference multiple of I for setting, the extracting multiple of D for setting; L is the data directory of output clock zone; Mod () is for getting surplus calculating.
5. Farrow filter according to claim 4 is characterized in that,
The coefficient c of each subfilter in said one group of subfilter m' (n) adopt following formula to confirm: c m ′ ( n ) = Round ( c m ( n ) × 2 M × ( 2 NI I ) m ) , Wherein, M is the quantification bit wide of said one group of subfilter coefficient, c m(n) be the normalized floating-point coefficient of m sub-filters; N is a sequence numbering, n=0, and 1 ..., N-1; N is a sequence length; M is the integer more than or equal to 0; Round () is the calculating that rounds up; NI is the said first setting bit wide,
Figure FDA0000101568340000012
Be provided with an addition cut position device between said one group of adder and the data output end, said addition cut position device is used to clip the low M position by the result of said one group of adder computing.
6. Farrow filter according to claim 4 is characterized in that, said Farrow filter also comprises the first logic hardware system, and the said first logic hardware system comprises:
First restorer is used for the said first logic hardware system is resetted, and uiv, rd_flag and temporary variable t are reset to initial value, and wherein, rd_flag is that address designation is read in the clock zone conversion;
The first variable processor is used for when each output clock arrives, t=t+D being set, and whether judging t greater than I, if t=t-I is set, and rd_flag is added 1, if not, t and rd_flag are constant;
Very first time coefficient maker is used to be provided with the corresponding said time coefficient uiv=2*t-I of each output clock.
7. Farrow filter according to claim 1 is characterized in that, said decimation filtering apparatus comprises one group of subfilter, one group of multiplier, one group of accumulator and one group of adder; Wherein,
Each multiplier of said one group of multiplier is connected with a multiplication cut position device, and said multiplication cut position device is used for setting bit wide according to second the output result of said multiplier is carried out the cut position operation, and with the corresponding accumulator of the input of the data behind the cut position;
Be provided with the cut position device that adds up between each said accumulator and the said subfilter, the said cut position device that adds up is used for the result of said accumulator output is carried out the cut position operation, obtains second type of fixed-point data.
8. Farrow filter according to claim 7 is characterized in that,
The time coefficient that said each multiplier receives is udv=2*ud-D, wherein, and ud=μ d* D, μ d=mod (I*k, D)/D, the difference multiple of I for setting, the extracting multiple of D for setting; K is the data directory of output clock zone; Mod () is for getting surplus calculating.
9. Farrow filter according to claim 8 is characterized in that,
The coefficient c of each subfilter in said one group of subfilter m' (n) adopt following formula to confirm: c m ′ ( n ) = Round ( c m ( n ) × 2 M × ( 2 ND I ) m × ( 2 NP × I D ) ) , Wherein, M is the quantification bit wide of said one group of subfilter coefficient, c m(n) be the normalization floating-point coefficient of m sub-filters; M is the integer more than or equal to 0; Round () is the calculating that rounds up; ND is the said second setting bit wide,
Figure FDA0000101568340000022
NP is the cut position bit wide of the said cut position device that adds up,
Figure FDA0000101568340000023
Be provided with an addition cut position device between said one group of adder and the data output end, said addition cut position device is used to clip the low M position by the result of said one group of adder computing.
10. Farrow filter according to claim 8 is characterized in that, said Farrow filter also comprises the second logic hardware system, and the said second logic hardware system comprises:
Second restorer is used for the said second logic hardware system is resetted, and udv, clr_flag and temporary variable t are reset to initial value, and wherein, clr_flag is the zero clearing sign of accumulator feedback input end and effective sign of dateout;
The second variable processor is used for when each output clock arrives, t=t+I being set, and whether judging t greater than D, if t=t-D is set, and clr_flag is put 1, if not, t and rd_flag are constant;
The second time coefficient maker is used to be provided with the corresponding said time coefficient udv=2*t-D of each output clock.
11. the implementation method of the Farrow filter of a logic-based circuit is characterized in that, comprising:
According to the input data sampling speed of configuration and the proportionate relationship of dateout sampling rate, confirm the mode of operation of Farrow filter;
When said mode of operation is filtering interpolation, in the process of said filtering interpolation, sets bit wide according to first middle data are carried out the cut position operation, obtain first kind fixed-point data;
When said mode of operation is filtering extraction, in the process of said filtering extraction, sets bit wide according to second middle data are carried out the cut position operation, obtain second type of fixed-point data.
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