JP6686717B2 - ΔΣ AD converter - Google Patents

Description

  The present invention relates to a power converter using PWM modulation or the like, and relates to a function of accurately converting an analog value such as a current or voltage waveform on which a ripple component of a carrier frequency of PWM modulation is superimposed into a digital value.

  The power converter uses PWM modulation and outputs a square-wave voltage. Therefore, the ripple waveform of the harmonic component of the PWM carrier frequency is also superimposed on the current flowing through the load. Normally, an analog signal including harmonics such as voltage and current to which this PWM modulation is applied is converted into a digital value by AD conversion, and the digital value is used as a feedback signal for control and measurement.

  In order to improve the control response, it is necessary to increase the AD conversion speed to reduce the detection delay, and to improve the accuracy, a detection method that easily removes unnecessary PWM harmonic components is required. Patent Document 1 discloses the AD conversion of a current component to which such PWM modulation is applied.

  As described in FIGS. 15 and 16, the feature of Patent Document 1 is that the sampling period for current detection is set to an integral multiple of the carrier period for a triangular wave carrier signal used for generating PWM modulation. Moreover, it is to synchronize with the apex of the triangular wave carrier signal.

  Then, by averaging the AD-converted results for the period of the triangular wave carrier signal, the harmonic component caused by the triangular wave carrier signal is suppressed (removed). In FIG. 17, sampling and AD conversion are performed at a timing of circles m, m + 1, ... At a sampling period that is eight times the triangular wave carrier frequency, and the apex interval of the triangular wave carrier signal, for example, from Tc-2 sample data to Tc 8 points up to the immediately preceding sample data are averaged.

  However, even in the method of Patent Document 1, when sampling at a coarse discrete time, a thin ripple-shaped current waveform such as between 3 and 4 samples in the Tc-1 section of FIG. 17 deviates from the sampling timing, and thus the average value of the carrier period. Therefore, a detection error will occur.

  In order to suppress such an error due to the roughness of the sample, it is sufficient to shorten the sampling period as much as possible and increase the number of sampling points. To this end, a high-speed AD converter and averaging a large number of points of data are required. Large-scale digital circuits or high-speed arithmetic units are required.

As an AD converter that samples an analog signal at high speed, a ΔΣ type AD converter is already widely used for digital audio and the like. A PWM carrier synchronization type detection method using this ΔΣ type AD converter will be examined. Although there are many circuit systems and arithmetic systems as the ΔΣ type AD converter, this time, the description will be made using Non-Patent Document 1. Non-Patent Document 1 describes the following figures and tables.
(1) FIG. 18: Configuration diagram of a second-order ΔΣ modulation modulator circuit.
(2) FIG. 19: Example of analog input and digital output data of ΔΣ modulation (1 bit output).
(3) FIG. 20: Configuration diagram of a decimation filter for converting the ΔΣ modulation modulator output into a data width of a plurality of bits. This circuit is also called a “cascade integral comb (CIC) filter”, a “Sinc ³ (three-stage SINC function digital filter)” circuit, or the like.
(4) FIG. 21: Detailed circuit of the integrator in FIG. 20 (also called an integrating circuit or an accumulating circuit).
(5) FIG. 22: Detailed circuit of the differentiator in FIG. 20 (also called a Comb circuit or a difference circuit).

  The outline of these non-patent documents 1 will be described.

  FIG. 18 is a block diagram showing the basic principle of the modulator circuit of the ΔΣ type AD converter, in which the analog input signal X (t) changes its state in synchronization with the reference clock Fclk. Convert to data (DATA). FIG. 20 shows a configuration example of a circuit for converting continuous digital data (DATA) having a 1-bit width as shown in FIG. 19 into a discrete digital value having a multi-bit length. It is composed of units I1, I2 and I3, a decimator 30 which operates at a timing obtained by dividing the reference clock by M, and differentiators D1, D2 and D3 which are cascaded in three stages.

  Here, the input signal (x (n) and the reference clock fs of the input signal) in FIG. 20 corresponds to (DATA and fclk) in FIG. Since the decimator 30 operates at the frequency F = fs / M obtained by dividing the reference clock fs by the decimation ratio M, the output signal y (m) in FIG. 20 is also updated at the operation timing of this decimator 30.

  FIG. 21 shows a detailed circuit of one stage of the integrators I1 to I3 in FIG. 20. The adder 1 and the D-FF (D-phillip flop) circuit D-FF for latching the result are shown in FIG. It is configured. Here, the reference clock MCLK of the D-FF circuit D-FF is the aforementioned reference clock fs.

  FIG. 22 shows a detailed circuit of one stage of the differentiators D1 to D3 of FIG. 20, which is composed of a D-FF circuit D-FF that latches the previous input value and a subtractor 2. In the D-FF circuit D-FF of the differentiators D1 to D3, the reference clock MCLK divided by M is input as the reference clock (MCLK / M).

  FIG. 23 shows the circuit of FIG. 20 using the circuits of FIGS. 21 and 22. In this non-patent document 1, since the signal names are different for each figure, the input signals X (t) of FIG. 18 are the same as the input signals X (n) of FIG. 20 and the input MOUT of FIG. Equivalent to. The output signal y (m) in FIG. 20 corresponds to the signal CN5 in FIG.

The bit width of each signal is as follows.
The ΔΣ modulation modulator output signal DATA (X (n), MOUT) of FIG. 18 has a 1-bit width. The signals of the integrators I1 to I3 and the differentiators D1 to D3 (DELTA1, CN1, CN2, CN3, CN4, DN0, DN1). , DN3, DN5), the required bit length (lower limit of the number of digits) is determined according to the decimation ratio M, as shown in Table 1.

  Further, in FIG. 20, the block in the first stage is not an integrator but a function of a special “+/−” input. This is the same function of the integrator as in FIG. 21, but the input signal shown in FIG. 19 has a binary 1-bit value “1/0”, while it has a positive / negative value “1 / −1”. It means that the special operation of converting to "and then integrating is added. That is, the range of the output digital value is to have positive and negative polarities such as a maximum negative value and a maximum positive value.

  However, in the embodiment to be described later, this special operation is not applied to simplify the description, the input signal of the decimation filter is treated as "1/0", and the output digital amount has a minimum value of 0 and a positive maximum value. It will be treated as one-sided amplitude data with only a positive sign having a value.

  Further, the decimator 30 of FIG. 20 is represented as a D-FF circuit D-FF having a terminal of (input CN2, output DN0, clock CNR) in FIG. 23, and the reference clock MCLK is divided by M in this clock CNR. Signal (MCLK / M) is input.

Regarding the bit width of the internal signal in FIG. 23 described above, Table 1 describes that the necessary width is determined by the decimation ratio (Decimation Ratio): M, which is a frequency division ratio. In the case of output data (integral input of the first stage is "1 / -1"), a bit width of Bus Width [bits] in Table 1 or more is required, and the obtained resolution may be Gain _DC [bits]. It is shown.

There are already many documents about the detailed principle of the decimation filter circuit of the ΔΣ type AD converter, and since it is not directly related to the technical contents to be proposed, only the above functional description will be described here. , It has the following features.
(1) As shown in Table 1, the combination of the update cycle of the output data and the bit length (resolution) of the output data can be selected by the decimation ratio: M.
(2) A high resolution of 16 bits or more can be realized relatively easily.
(3) An analog signal is sampled by the reference clock fclk in the modulator section, and if an element operating at a high clock frequency of fclk = 10 MHz or more is used, almost continuous sampling is performed for a PWM waveform of about several kHz. Can be approximated to.

  Therefore, even if there is a thin ripple pointed out in FIG. 17, this is sampled at a large number of points, and a more accurate AD conversion result can be obtained. A high-speed sample using ΔΣ type AD conversion like this method can be expressed as “an analog signal is oversampled at a frequency M times the AD conversion output update frequency”.

In the following description, the following terms will be used.
A "modulator" is a circuit for converting the analog input of Non-Patent Document 1 shown in FIG. 18 into 1-bit data.
The clock fclk is the "modulator reference clock" or the "reference clock".
"Decimation filter" for the entire circuit of FIG. 21 of Non-Patent Document 1.
The decimation ratio M in FIG. 21 of Non-Patent Document 1 is “decimation ratio: M”.
-The components of FIG. 20 are respectively an "integrator", a "decimator", and a "differentiator".
-A circuit that generates a decimator operating signal from a reference clock is a decimator frequency divider or frequency divider.
The timing of the frequency divider output at which the decimator operates is “decimator operation timing”. This is also the timing at which the output data of the AD converter is updated, so it is also called “AD output timing”.

  When such a ΔΣ modulator and a decimation filter having a decimation ratio of M are used, the output data is updated at the M division cycle of the reference clock while oversampling at the reference clock cycle.

  Explaining with the example of FIG. 24, the portion of the waveform surrounded by the ellipse is the period shown that one decimation output is measured, and if a high-speed clock as shown in the modulator output timing at the bottom is used, thin ripple It is possible to realize a large number of samples in which even components are not missed.

  Also, the AD conversion is updated at the end of the period indicated by the ellipse, and this corresponds to the “sample period of AD conversion in Patent Document 1”. Therefore, if the "combination of the reference clock and the decimation ratio M" or the "carrier frequency" is selected so as to be synchronized with the PWM carrier signal and become an integral multiple of the carrier frequency, "PWM of Patent Document 1" It is possible to combine the advantages of both “ripple component removal capability” and “high oversampling function of the ΔΣ AD converter of Non-Patent Document 1”. As a result, even with an analog signal waveform including PWM ripple as shown in FIG. 24, it is possible to obtain an accurate AD conversion value in which ripple harmonic components are easily removed. The above is the description of the related art.

  However, in the conventional method, in order to precisely synchronize the triangular wave carrier signal and the AD conversion output timing, the reference clocks of both the PWM carrier generation circuit and the decimation filter circuit are made to coincide with each other, and further the carrier signal on the PWM carrier generator side is matched. And the decimator operation (AD output) timing on the ΔΣ type AD converter side must be synchronized at the same time.

  Therefore, in general, the circuit for oscillating the PWM carrier and the modulator or decimation filter circuit are arranged close to each other or mounted on the same integrated circuit to operate as a common reference clock and timing signal. .

JP, 10-42569, A JP-A-2-146939

  TEXAS INSRUMENTS Application Report SBAA094-June2003 `` Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Application ''

  However, in a large-capacity power converter or the like, the size of the device becomes large, and the signal wiring also becomes long. In particular, we want to shorten the gate signal wiring and analog signal wiring so that they are not affected by noise. Therefore, the circuit of the control unit that generates the PWM signal is arranged on the main circuit side such as the IGBT, while the analog circuit and the AD conversion circuit that mount the ΔΣ converter are arranged on the output terminal side where the analog sensor is mounted. . Then, it is preferable that a communication is performed between them by digital transmission such as a differential system that is less susceptible to noise.

  However, if the PWM generating section and the AD converting section are arranged apart from each other in this manner, noise is likely to be mixed, and it becomes difficult to share the reference clock. Strictly speaking, there is a minute frequency difference even if a crystal oscillator having a high frequency accuracy is used. Therefore, the frequency difference is time-integrated with time and the synchronization between the PWM carrier signal and the AD sample is deviated. .

  In such a case, as shown in FIG. 25, a method of synchronizing clocks of different circuits using a PLL oscillator PLL is used.

  A synchronization timing signal Ts (m) for AD conversion is transmitted from the PWM carrier generator 3, and a phase-locked loop (PLL: Phase Locked Loop) is used on the AD conversion side with the received signal of the synchronization timing signal Ts (m) as a reference. ) Is used to generate a clock Fclk_PLL synchronized with the reference clock on the transmission side by multiplying the frequency.

  Then, the digital control circuit 4 on the PWM generation side performs a control calculation for realizing a function required as a power converter from the AD conversion result of the analog signal to generate a PWM command, and PWM is generated from the PWM command and the PWM carrier signal. A PWM signal is output from the comparator section 5, and thereby a load is driven through an amplifier circuit INV such as an inverter to control as desired.

  Supplementally, in FIG. 20 of Non-Patent Document 1, an example in which the decimator 30 is arranged between the three-stage integrators I1 to I3 and the three-stage differentiators D1 to D3 is shown. Since it operates in one, two, three or more stages, it is not particularly limited to a three-stage Sinc filter circuit. However, if the number of stages is small, the resolution will be reduced as shown in Table 1, and therefore appropriate selection is required according to the required performance.

  Patent Document 2 is disclosed as a prior art of a power converter using a PLL oscillator PLL.

  As described above, in a power converter or relay that requires AD conversion of voltage, current, etc., it is an object to realize highly accurate AD conversion at low cost without using an expensive high frequency PLL circuit. Become.

  The present invention has been devised in view of the conventional problems described above, and one aspect thereof is a digital control arithmetic unit that outputs a PWM signal to an amplifier circuit, and an amplifier circuit that supplies the load to the load based on the PWM signal. A delta-sigma AD converter including: an analog detection unit that detects a current or a voltage as an analog signal, converts the analog signal into a digital signal, and outputs the digital signal to the digital control calculation unit. Has a first reference clock oscillator that outputs a first reference clock and a PWM carrier generator that outputs a synchronization timing signal to the analog detection unit, and the analog detection unit is different from the first reference clock. A second reference clock oscillator that outputs a second reference clock and a decimator operation timing signal that is one clock or more earlier than the synchronization timing signal. Frequency division ratio selection signal is set to 1, and when the time difference between the decimator operation timing signal and the synchronization timing signal is less than ± 1 clock, the division ratio selection signal is set to 0 and the decimator operation timing signal is set. Occurs more than one clock later than the synchronization timing signal, a frequency division ratio correction unit that sets the frequency division ratio selection signal to 2, and a decimation ratio is corrected based on the frequency division ratio selection signal to obtain the synchronization timing. A variable frequency divider circuit that outputs the decimator operation timing signal based on the signal and the corrected decimation ratio, a ΔΣ modulator that converts the analog signal into a digital signal at the timing of the second reference clock, and two or more are connected in series. It has an integrator, a decimator, and two or more series-connected differentiators, and the ΔΣ modulator outputs Based on the frequency division ratio selection signal and the decimator operation timing signal, the digital signal is input to the integrator when the frequency division ratio selection signal is 1, and when it is 0, the first stage integrator inputs the digital signal. In the second and subsequent integrators, the output of the integrator in the previous stage is input, and in the case of 2, the integrator in the first stage receives twice the digital signal and the integrator in the second stage is the integrator in the previous stage. When the value obtained by doubling the output of the above and the digital signal are input and the integrators are connected in series of 3 series or more, the integrators in the 3rd and subsequent stages are set to the value obtained by doubling the output of the integrator in the previous stage. A decimation filter for converting the sum of the outputs of the integrators of each stage into AD conversion data, and the decimation filter outputs the AD conversion data to the digital control arithmetic unit. .

  Further, as another aspect, a digital control arithmetic unit that outputs a PWM signal to an amplifier circuit, and a current or a voltage supplied to the load from the amplifier circuit based on the PWM signal is detected as an analog signal, and the analog signal is a digital signal. An analog detection unit for converting into the digital control calculation unit and outputting to the digital control calculation unit, wherein the digital control calculation unit includes a first reference clock oscillator that outputs a first reference clock; A PWM carrier generator for outputting carrier apex timing to an analog detection unit, wherein the analog detection unit outputs a second reference clock different from the first reference clock, and a decimator operation timing. The carrier cycle average output timing signal obtained by dividing the signal by N is 1 clock more than the carrier vertex timing. If it occurs earlier than the clock, the division ratio selection signal is set to 1, and if the time difference between the carrier cycle average output timing signal and the carrier vertex timing is less than ± 1 clock, the division ratio selection signal is set to 0, When the carrier cycle average output timing signal occurs 1 clock or more later than the carrier apex timing, a frequency division ratio correction unit that sets the frequency division ratio selection signal to 2, and a decimation ratio based on the frequency division ratio selection signal. And a ΔΣ modulator that corrects the analog signal to the digital signal at the timing of the second reference clock, and a variable frequency divider circuit that outputs the decimator operation timing signal based on the carrier vertex timing and the corrected decimation ratio. And an integrator connected in series with two or more, a decimator, and two or more connected in series with A divider, the digital signal output from the ΔΣ modulator is based on the frequency division ratio selection signal and the decimator operation timing signal, and when the frequency division ratio selection signal is 1, the input of the integrator is 0, When 0, the first-stage integrator inputs the digital signal, and the second-stage and subsequent integrators input the output of the previous-stage integrator, and when 2, the first-stage integrator doubles the digital signal. Is input, and the second-stage integrator receives as input the value obtained by adding the digital signal obtained by doubling the output of the previous-stage integrator. And a decimation filter for converting the AD output data into a value obtained by adding the output of the pre-stage integrator to the value obtained by doubling the output of the pre-stage integrator, and the decimation filter outputs the decimation filter. AD conversion day The data is integrated N times and divided by N (N is a natural number of 2 or more), and a value is output to the digital control arithmetic unit as AD average value data.

  Further, as one aspect thereof, the frequency division ratio correction unit does not correct the decimation ratio during a period other than after the carrier vertex timing is generated and before the first decimator operation timing signal is output thereafter. Is characterized by.

  According to the present invention, it is possible to realize highly accurate AD conversion at low cost without using an expensive high frequency PLL circuit in a power converter or relay that requires AD conversion of voltage, current, and the like. Become.

3 is a block diagram showing a power converter according to the first embodiment. FIG. 3 is a schematic diagram showing a variable frequency dividing circuit and a decimation filter according to the first embodiment. FIG. 3 is a time chart showing the operation of each unit of the power converter according to the first embodiment. FIG. 3 is a schematic diagram showing a variable frequency dividing circuit and a decimation filter. FIG. 3 is a schematic diagram showing a variable frequency dividing circuit and a decimation filter. FIG. 6 is a block diagram showing a variable frequency divider and a decimation filter according to the second embodiment. The block diagram which shows the power converter in Embodiment 3. FIG. 9 is a block diagram showing a frequency division ratio correction unit according to the fourth embodiment. 9 is a time chart showing an operation example of the fourth embodiment. 10 is an operation time chart of input / output of AD conversion and each signal to which the fourth embodiment is applied. 9 is an operation time chart of input / output of AD conversion and each signal to which the fourth embodiment is not applied. The enlarged view of FIG. The enlarged view of FIG. The enlarged view of FIG. Schematic which shows the control apparatus of the power converter in patent document 1. The time chart which shows each signal in patent documents 1. A time chart showing discrete time sampling. FIG. 3 is a configuration diagram of a secondary ΔΣ modulation module circuit. The figure which shows the example of the analog input of delta-sigma modulation, and digital output data. The block diagram of a decimation filter. The detailed circuit diagram of the integrator in the decimation filter. The detailed circuit diagram of the differentiator inside a decimation filter. The figure which showed the decimation filter of FIG. 20 by the integrator and differentiator of FIG. 21, FIG. Time chart showing oversampling. The block diagram of the synchronous system between different printed boards using a PLL oscillator.

  The conventional method shown in FIG. 25 requires a PLL oscillator PLL that restores the reference clock from the synchronization timing signal Ts (m) and a high-frequency PLL circuit that operates at a high frequency.

  Therefore, in the present invention, reference clock oscillators having slightly different frequencies are used, and the synchronization between the PWM carrier and the modulator operation timing of the AD converter is realized without mounting the PLL circuit.

  Instead of modifying the reference clock with the PLL circuit, instead of adjusting the decimation ratio: M inside the decimation filter, the frequency division ratio of the modulator is changed minutely (for example, M ± 1 with respect to M). To realize the synchronization correction function.

  As the synchronization reference signal, there are two types of signals, the carrier vertex timing Tc in FIG. 17 and the synchronization timing signal Ts (m) in FIG. Therefore, regarding the PLL function in the embodiments, the implementation method for synchronizing with the synchronization timing signal Ts is shown first, and then the extension is performed so as to synchronize with the carrier vertex timing Tc.

  Here, if the decimation ratio: M is simply corrected, the number of integrations of the integrators I1 to I3 connected in cascade does not match, and only some of the integrators are different from the pre-correction decimation ratio: M. Is added. In this case, the AD conversion output that has passed through the differentiation circuit after the decimator becomes an abnormal value. Therefore, we devised a method to prevent this abnormal output.

  Hereinafter, Embodiments 1 to 4 of the power converter of the present invention will be described in detail.

[Embodiment 1]
The overall configuration of the first embodiment is shown in FIG. 1, and its schematic configuration is as follows. A PWM circuit 11 is built in the digital control calculation unit 6, and a PWM carrier generator 3 outputs a carrier signal and a synchronization timing signal Ts (m) obtained by multiplying the triangular wave carrier period by N.

  The PWM comparator unit 5 compares the carrier signal with the PWM command to generate a PWM signal, and drives the load L via the amplifier circuit (inverter) INV. Information such as the input current of the load L is detected by the analog sensor 7, AD-converted by the analog detection unit 8, and output as a digital value to the digital control calculation unit 6.

  In the first embodiment, the above-mentioned ΔΣ type is adopted as the AD converter, and this decimator operation timing signal Td (m) is synchronized with the timing of the synchronization timing signal Ts (m) received from the PWM carrier generator 3. .

  Next, individual components of FIG. 1 will be described.

(1) Digital control arithmetic unit 6
A circuit on the PWM generation side, which is constructed by a synchronous digital circuit that operates by the first reference clock Fclk1 output from the first reference clock oscillator 9, and includes a digital control circuit 4 for generating a PWM command and a PWM carrier generator 3 A PWM circuit 11 having a PWM comparator (pulse output generator) 5 and a first reference clock oscillator 9 that outputs a first reference clock Fclk1 are provided.

  The digital control circuit 4 uses, as an input signal, data obtained by AD-converting an analog signal detected by an analog sensor 7, which will be described later, and based on this data, outputs a PWM command corresponding to a voltage command necessary for controlling the load L. It is outputting.

(2) Amplifier circuit INV and analog sensor 7
The amplifier circuit INV is a converter such as an inverter in which power semiconductor switching elements are combined, and amplifies the power into a PWM waveform required to actually drive the load L, that is, a pulsed voltage or current waveform. The analog sensor 7 detects the output information of this amplifier circuit via a voltage sensor, a current sensor, etc., and the AD conversion circuit 21 converts this analog signal into a digital quantity, and the digital control circuit 4 described above. To transmit.

(3) Load L
The digital control calculation unit 6 is an object to be controlled, and a motor, an electric power system and the like correspond to this.

(4) Second reference clock oscillator 10
The second reference clock oscillator 10 outputs a second reference clock Fclk2 different from the first reference clock Fclk1.

(5) Analog detector 8
The analog detection unit 8 AD-converts the output signal of the analog sensor 7 into a digital amount handled by the digital control calculation unit 6. The circuit of the analog detection unit 8 uses the second reference clock Fclk2 different from the first reference clock Fclk1 on the PWM side, but since a crystal oscillator or the like is used, the frequency difference between these is assumed to be minute. The analog detection unit 8 is further composed of the following elements.

(5-1) ΔΣ modulator 12
The ΔΣ modulator 12 converts the analog value into a digital signal Si (k) having a length of 1 bit at the timing of the second reference clock Fclk2 according to the principle of ΔΣ conversion. Strictly speaking, there is a circuit that outputs not only 1-bit length but also multi-bit length. Even in that case, the first embodiment is effective, but the first embodiment will be described by using an example of 1-bit.

(5-2) Frequency division ratio correction unit 13a
The frequency division ratio correction unit 13a performs a function corresponding to the phase correction of the PLL control. In the phase comparator 14, the generation time t (Ts (m)) of the synchronization timing signal Ts (m) input from the outside and the generation time t (Td (m)) of the internal decimator operation timing signal Td (m) are compared. The time difference (phase difference) ΔT = t (Td (m)) − t (Ts (m)) is detected.

  The frequency division ratio correction selection unit 15 operates as follows.

(1) When Td (m) occurs 1 clock or more earlier than Ts (m) (-1 [clk] ≧ ΔT)
Msel = (M + 1): Frequency division ratio selection signal (2) When the difference between Td (m) and Ts (m) is less than ± 1 clock (-1 <ΔT <1 [clk])
Mesl = (M): Frequency division ratio selection signal (3) When Td (m) occurs 1 clock or more later than Ts (m) (1 [clk] ≦ ΔT)
Msel = (M-1): Frequency division ratio selection signal The clock described in (1) to (3) is the second reference clock Fclk2.

  M here is an ideal decimation ratio (frequency division ratio for the second reference clock Fclk2) assuming that Fclk1 = Fclk2.

In an actual circuit, the frequency division ratio selection signal Msel has a code value such as "0, 1, 2", but in the above description, it is displayed as a functional description in order to make it easier to understand the relation with the later description. An example in which the frequency division ratio selection signal Msel is represented by a code value is shown below.
Under the above condition (1): Frequency division ratio selection signal Msel = 1
Under the condition of (2) above: Frequency division ratio selection signal Msel = 0
Under the condition of (3) above: Frequency division ratio selection signal Msel = 2
Further, this time, it is assumed that the frequency error of the second reference clock Fclk2 is small and the minimum correction amount, that is, the correction value of the decimation ratio is limited to (M ± 1).

  Practically, it is necessary to add a filter function and a correction coefficient to the information on the time difference, and to set the correction amount to ± 1 clock or more, but these have already been studied as PLL control. Therefore, I will only give a brief explanation of the principle here.

  Further, in FIG. 1, the frequency division ratio is not directly output from the frequency division ratio correction selection unit 15, but a code called the frequency division ratio selection signal Msel is output, and the decimation filter 16 or the variable frequency division is performed according to this code. The circuit 17 has a configuration in which the frequency division ratio is corrected.

  This is also made easy to understand by expressing it with a selector circuit of the same configuration in FIG. 2 which will be described later, and it has a special meaning that the frequency division ratio selection signal Msel corresponding to the functional description is coded. There is no.

(5-3) Variable frequency dividing circuit 17 and decimation filter 16
The variable frequency dividing circuit 17 and the decimation filter 16 have the configuration shown in FIG. The variable frequency dividing circuit 17 includes a selector Sel_M1, a down counter Count1, and a comparator Comp1 that outputs a decimator operation timing signal Td (m) as "active (= 1)" when the counter value is 0. Has been done.

  Then, when the decimator operation timing signal Td (m) input to the load enable terminal LD becomes active (= 1), the down counter Count1 loads the value of the D input and outputs the value of Q when the next clock is generated. To do. Then, when the load enable terminal LD is not active, the normal countdown operation is performed until it becomes zero.

  Therefore, in the case of the decimation ratio: M, if the value of (M-1) is set to the D terminal, the decimator operation timing signal Td (m) is adjusted at the timing of dividing the second reference clock Fclk2 by M. It becomes active (= 1).

  In the first embodiment, the variable frequency dividing function is added by expanding the D input to ± 1 with respect to the reference decimation ratio: M. Specifically, in order to realize the decimation ratio (frequency division ratio): {(M + 1), M, (M-1)} corresponding to the frequency division ratio selection signal Msel which is the output of the frequency division ratio correction selection unit 15. Then, the value of {M, (M-1), (M-2)} is selected by the selector Sel_M1.

  The input signals of the selectors Sel_c11, Sel_c12, and Sel_c13 inserted before the integrators I1 to I3 are in the following combinations according to the Msel signal.

(1) When Msel = M division (basic decimation period, decimator operation timing signal Td (m) is synchronized with synchronization timing signal Ts (m))
Sel_c11: Selects the digital signal Si (k) (k indicates the timing of the second reference clock Fclk2)
Sel_c12: Select the output of the preceding D-FF circuit D-FF1 Sel_c13: Select the output of the preceding D-FF circuit D-FF2 (2) In the case of Msel = (M + 1) frequency division (decimator operation timing signal Td (m ) If you want to delay)
Sel_c11: Selects the input signal to zero Sel_c12: Selects the input signal to zero Sel_c13: Selects the input signal to zero (3) In the case of Msel = (M-1) division (decimator operation timing signal Td (m) should be accelerated If)
Sel_c11: Selects twice the digital signal Si (k) Sel_c12: Selects twice the output of the previous stage D-FF circuit D-FF1 and the added value of the digital signal Si (k) Sel_c13: Previous stage D-FF circuit Double the output of the D-FF2 and the added value of the output of the D-FF circuit D-FF1 are selected. The reason for applying this input value will be described later, but the important point of the first embodiment is that the variable frequency division is performed. The selector Sel_M1 that selects the ratio corrects the decimation timing in a PLL control manner, but the selectors Sel_c11, Sel_c12, and Sel_c13 added to the integrators I1 to I3 make the integration times between the decimation timings always approximate to M times. It is to let. Therefore, the input signal is ignored only once or doubled to make an adjustment to correct the integrated amount.

  Of the decimation filter part, the part of the decimation filter that is changed in the first embodiment is the part of these three-stage integrators I1 to I3, and the subsequent parts are the decimator operation timing signal Td ( m) and a decimator 30 operating in m) and a three-stage differentiator D1, a differentiator D2, and a differentiator D3, and the output of the final differentiator D3 is the output of the AD converter. , Is updated at the operation timing of the decimator. The above is the description of the configuration of the first embodiment.

(Explanation of action / operation)
First, using the time chart of FIG. 3 to explain the variable frequency division operation, the relationship between the frequency division ratio selection signal Msel of the frequency division ratio correction unit 13a of FIG. 1 and the counter value QM of the down counter Count1 of FIG. Will be explained.

  Generation time t (Ts (m)) of the synchronization timing signal Ts (m) transmitted from the PWM circuit 11 in the first stage of FIG. 3 and decimator operation timing signal Td (in the second stage of FIG. 3 The time difference ΔT from the generation time t (Td (m)) of m) is detected as the phase difference of the PLL.

  Due to this time difference ΔT, the frequency division ratio selection signal Msel changes as in the fifth stage of FIG. If the time difference ΔT is within the range of (−1) to (+1) clocks, the Msel signal is “select frequency division ratio (decimation ratio) = M”. When the time difference ΔT becomes (+1) or more, it is considered that the phase difference is delayed by one clock or more, and the frequency division ratio selection signal Msel is set to “select frequency division ratio = (M−1)”, and the decimator operation timing signal Td ( Correct so that the cycle of m) becomes shorter. Conversely, when the time difference ΔT becomes (−1) or less, it is considered that the phase difference has advanced by one clock or more, and the frequency division ratio selection signal Msel is set to “select frequency division ratio = (M + 1)” and the decimator operation timing signal Td (m ) Is corrected so that the cycle becomes longer. The three types of states of the frequency division ratio selection signal Msel are represented as zero and positive and negative level signals in FIG.

  When the counter value QM at the third stage in FIG. 3 becomes zero due to the frequency division ratio selection signal Msel, the decimator operation timing signal Td (m) at the fourth stage in FIG. 2 changes to the load enable terminal LD of the frequency divider counter. , And the counter value QM of the down counter Count1 at the next clock becomes the value selected by the selector Sel_M.

  Since "M division" is selected in the synchronization timing signal Ts (ma-1) and the synchronization timing signal Ts (ma) in FIG. 3, (M-1) is loaded into the down counter Count1. In the case of the synchronization timing signal Ts (ma + 1), "M-1 division" is selected, so (M-2) is selected, and in the case of Ts (mb), "M + 1 division" is selected. Therefore, (M) is loaded into the down counter Count1.

  As a result, the generation timing of the next decimator operation timing signal Td (m) to which the correction of the variable frequency division is applied is corrected within a clock with a time difference from the synchronization timing signal Ts (m). (PLL) function can be realized.

  FIG. 4 shows only the variable frequency division which is a part of the first embodiment is applied, and the decimator is the same as the conventional example. In this state, when the operations of the three-stage integrators I1 to I3 are viewed in time series, the frequency division ratio (decimation ratio) changes every moment, so that the number of integrations at each decimation timing is M or other than M. Since they are mixed, a normal AD conversion result cannot be obtained even after passing through the three differentiators D1 to D3 after decimation. Therefore, in the first embodiment, the integrators I1 to I3 are also improved, and FIG. 4 is changed as shown in FIG.

  Since FIG. 2 includes two types of frequency division correction functions having a frequency division ratio (decimation ratio) of (M-1) and (M + 1), first, frequency division is performed only for the frequency division ratio (M + 1). The case of correction will be described.

  FIG. 5 is a diagram in which the portion corresponding to the division ratio (M−1) is deleted from FIG. 2. According to FIG. 5, when the frequency division ratio (M + 1) is selected by the frequency division ratio selection signal Msel, the adder inputs of the integrators I1 to I3 are selected for one clock only when the initial value of the down counter Count1 is loaded. It is forcibly switched to zero by Sel_c1, Sel_c2, and Sel_c3.

  As a result, the number of operations of the integrating circuit is M + 1, but it is possible to artificially stop the integration of one time of which the down counter Count1 is loaded with the initial value. In other words, by discarding the input signal at this time, it is possible to approximate the number of integrations to the basic M number of times.

  Discarding the input signal for one time causes an error. However, since a component having a 1-bit width and an extremely short time for one clock input to the modulator is ignored, it can be ignored as a minute in practical use. it can. For example, in the case of M = 16, 2 ^ 16 = 65534 times of integration are performed, but the error is only one of them.

  The frequency of this frequency division correction is also due to the frequency difference between different reference clocks, and if an oscillator with high frequency accuracy such as a crystal oscillator is used, the frequency of occurrence will be very low, so it will be long enough. Considering the error with respect to the average value in the time interval, the influence becomes smaller. In this way, we decided to correct the number of integrations, paying attention to the fact that the ΔΣ modulator output has a 1-bit width and a small amount of instantaneous information.

  Next, the correction operation of the integrators I1 to I3 in the case of the frequency division ratio (M-1) will be described. When the frequency division ratio is smaller than the basic number such as (M-1), it is necessary to perform the approximate correction so that the number of integration is increased by one.

  Therefore, at the same timing as the correction of the frequency division ratio (M + 1), that is, when the frequency division ratio (M-1) is selected by the frequency division ratio selection signal Msel, and the down counter Count1 is loaded with the initial value. By doubling the adder input of each of the integrators I1 to I3 only for one clock timing, the correction is performed as if the integration for two clocks were performed.

  This is realized by switching the selectors Sel_c11, Sel_c12, and Sel_c13 in FIG. 2 to the "M-1" side. However, the integrator I1 at the first stage only needs to double the input signal, but if the integrators I2 and I3 at the second stage and thereafter try to simulate the integrator for two clocks, the increase amount of the integrator at the previous stage is increased. Must also be considered. Therefore, the two integral operations of (k) and (k + 1) will be described using discrete equations.

  First, in the first (k) clock, the three-stage integrators I1 to I3 are calculated based on the input and the previous integration result as shown in equation (1). Here, the symbols are defined as follows.

k, (k + 1), ...: Number indicating operation timing of reference clock S _i (k): Digital signal C ₁ (k), C ₂ (k) input to decimation filter at time of operation timing k of reference clock , C ₃ (k): Latch outputs of the integrators I1 to I3 of the first, second, and third stages (k), the operation of the following equation (1) is executed.

Then, assuming that the same input signal continues, and approximating S _i (k) ≈S _i (k + 1), the calculation of the following equation (2) is executed at the timing of (k + 1).

  By substituting the equation (1) into the equation (2), it is possible to collectively calculate the operation results for two clocks that reach the time (n + 1) after the time (n) by using the time (n-1) data as the previous value. The integrators I1 to I3 at the respective stages are expressed by equations (3) to (5).

  From this result, the integrator I1 at the first stage only needs to double the input value and add it as in the equation (3). However, as in the equations (4) and (5), the second and third integrators I2 and I3 not only double the output of the previous integrator, which is the original input signal, Further, it is understood that the value of the output from the integrator at the previous stage (in the case of the integrator I2 at the second stage, the digital signal Si (k)) must be added.

  FIG. 2 shows the expressions (3) to (5) in the form of a block diagram. As a result, only one of the (M-1) integration operations is approximated to the M integration operations by changing the input value for two clocks.

The error in this case is that the virtual input of S _i (k) ≈S _i (k + 1) is set in the first stage, and it has a 1-bit width and the modulator has the same value as the correction operation of the (M + 1) frequency division. It is a component for one clock that is input. Therefore, the effect of this error can be practically ignored.

  As described above, in order to realize the PLL function for operating the ΔΣ AD converter in synchronization with the AD conversion timing given from the outside, the decimation timing is generated according to the time difference (phase comparator). By applying a correction that makes the cycle of the frequency divider variable and by approximating the integrators I1 to I3 in the decimation filter 16 to a frequency equivalent to the frequency of frequency division without correction even when the frequency division ratio is corrected, The AD conversion can be accurately executed at the timing.

  In the first embodiment, highly accurate AD conversion can be realized without using an expensive high frequency PLL circuit in a power converter or relay that requires AD conversion of voltage, current, and the like. As a result, a power converter with high output accuracy can be realized at low cost.

  When the basic control circuit and the AD conversion circuit use different reference clocks, the AD conversion can be executed in synchronization with the timing required by the control circuit.

  In the conventional method, the PLL oscillator generates a reference clock that is synchronized with one of the reference clocks. However, even if the frequencies of these reference clocks are slightly deviated, the frequency divider inside the decimation filter in the ΔΣ AD conversion is used. By adding the function of correcting the frequency division ratio of, the conventional PLL oscillator can be made unnecessary.

  Further, with respect to the problem that a normal output cannot be obtained by changing the frequency division ratio of the frequency divider for the multistage integrators I1 to I3 in the decimation filter 16, the integrator is stopped or integrated twice. Since functions such as the above are added to simulate the operation as if the standard decimation ratio: M, the AD conversion output does not become an abnormal value.

  Regarding the error when the frequency division ratio changes due to the PLL correction, the output of the ΔΣ modulator 12 has only a 1-bit width, and only this one-clock integration error occurs.

  With respect to the frequency of the correction operation, if a crystal oscillator or the like is used, the error of a plurality of clocks is very small, so that it is considerably reduced. For example, if a crystal oscillator of 10 MHz with a frequency difference of 1 × 10 ^ (− 9) is used, the error frequency will be about 0.001 Hz. In this case, once every 100 seconds, a deviation of one clock will occur. Can be maintained to maintain synchronization.

  That is, since the error is of a level that can be ignored and the frequency of occurrence is further low, practically, the error can be ignored. Therefore, it is possible to achieve both required operation timing synchronization and accuracy maintenance without using a PLL oscillator.

[Embodiment 2]
As the decimation filter 16 of the first embodiment, those in which three-stage Sinc functions (CIC circuits) as shown in FIG. 2 are connected in cascade are used. The number of stages need not be three. Therefore, a simplified configuration of the two-stage Sinc function (CIC circuit) is referred to as the second embodiment. The overall configuration is the same as that of the first embodiment shown in FIG. 1, and only the decimation filter 16 is changed from FIG. 2 to FIG. In FIG. 6, the integrator I3, the selector Sel_13, and the operation unit of the input signal of this selector are deleted from FIG. 2, and the differentiator D3 is also deleted.

  This reduces the accuracy (resolution) of the AD converter, but simplifies the circuit.

[Third Embodiment]
In the first and second embodiments, the AD conversion-decimator operation timing signal Td (m) that is the PWM carrier frequency multiplication signal is used as the reference timing as the AD conversion operation timing transmitted from the PWM circuit side.

  On the other hand, when further averaging a plurality of AD conversion results during the carrier cycle period as in Patent Document 1, as shown in FIG. I would like to incorporate the averaging circuit (average of N times) 18 of. Then, the synchronization timing signal Ts (m) is also changed to the carrier apex timing Tc (n) of the carrier signal for which the averaging period can be designated, and in synchronization with this, the AD average value data SO_ave (n) is digitally controlled and calculated by the digital control computing unit 6 Want to send to.

  Therefore, the following functions are added to the first embodiment. First, Ts (m) corresponding to the AD conversion operation timing in FIG. 25 is changed to the carrier vertex timing Tc (n) at the carrier vertex time such as (Tc-2) or (Tc-1) in FIG.

  Since the carrier apex timing Tc (n) corresponds to the synchronization timing signal Ts (m) divided by N, the decimator is used to operate the phase comparator 14 of the division ratio correction unit 13a in FIG. 7 normally. The carrier cycle average output timing signal Tc_ad (n) obtained by dividing the operation timing signal Td (m) by N by the N divider 19 changes the carrier cycle average output timing signal Tc_ad (n) into a phase comparison signal.

  The frequency division ratio correction unit 13a in FIG. 7 operates as follows, similar to the first embodiment.

(1) When the carrier cycle average output timing signal Tc_ad (n) occurs at least one clock earlier than the carrier vertex timing Tc (n) (-1 [clk] ≧ ΔT).
Signal for selecting Msel = (M + 1) frequency division (2) When the difference between the carrier cycle average output timing signal Tc_ad (n) and the carrier vertex timing Tc (n) is less than ± 1 clock (-1 <∠ΔT <1 [Clk])
Msel = (M) signal for selecting frequency division (3) When carrier cycle average output timing signal Tc_ad (n) occurs 1 clock or more later than carrier vertex timing Tc (n) (1 [clk] ≦ ΔT)
Signals for selecting Msel = (M-1) frequency division The clocks described in (1) to (3) are the second reference clock Fclk2.

  The carrier cycle average output timing signal Tc_ad (n) is also used as the average calculation and the transmission timing of the result.

  In the first and second embodiments, the timing signal transmitted from the PWM circuit side uses the synchronous timing signal Ts (m). In Patent Document 1, this corresponds to a multiplied signal of the PWM carrier frequency, and this makes it possible to synchronize the AD conversion timing required by the PWM circuit side and the decimator operation timing for actually updating the AD conversion output.

  Further, in Patent Document 1, the AD conversion results of a plurality of times within the carrier peak timing Tc period are averaged. Therefore, I would like to incorporate an averaging circuit (N-time average) 18 for the PWM carrier period as shown in FIG. 7 on the AD converter side. For that purpose, the execution timing of the averaging operation, that is, the carrier vertex timing Tc of the triangular wave carrier signal also needs to be transmitted to the AD conversion side. Therefore, in FIG. 7, the synchronization timing signal Ts (m) is changed to the carrier vertex timing Tc (n) of the triangular wave carrier signal. Then, the decimator operation timing signal Td (m) corresponding to this N multiplication is generated by the variable frequency dividing circuit and used as the AD conversion timing.

  Regarding the time difference detection of the PLL operation, the carrier cycle average output timing signal Tc_ad (n) obtained by dividing the decimator operation timing signal Td (m) by N is generated as shown in FIG. The time difference of occurrence is compared and the function like PLL is executed as in the first and second embodiments.

  The method relating to the average calculation unit (average of N times) 18 in FIG. 7 is not described in detail because it is general, but the average calculation unit 18 stores N times AD conversion results and accumulates the results. And divide by N. In the case of serial transmission, the averaged result is once latched, converted into a serial transmission signal, and output to the digital control arithmetic unit 6.

  This allows the analog detection unit 8 to synchronize the AD conversion timing and the average value calculation timing with respect to the signal transmitted from the digital control arithmetic unit 6 according to the first or second embodiment.

  By applying the third embodiment, the timing signal from the digital control calculation unit 6 can be changed to the carrier apex timing Tc of the carrier frequency. As a result, it becomes possible to average the output of the AD conversion in the period synchronized with the carrier vertex timing Tc, and the PWM ripple removal can be realized.

[Embodiment 4]
In the third embodiment, the output of the decimator operation timing signal Td (m) and the AD conversion occur N times during the interval of the carrier vertex timing Tc (n) synchronized with the PWM carrier. As shown in FIG. 7, only by changing the phase synchronization timing to the N-fold cycle with respect to the first embodiment, the frequency division ratio correction is executed a plurality of times out of N times of AD conversion results for performing one averaging operation. There is a possibility.

  Even if the error caused by the frequency division ratio correction per time is small, many correction operations of (M-1) and (M + 1) by the frequency division ratio selection signal Msel are performed during the interval of the carrier vertex timing Tc (n). If the operation is repeated, the errors will be concentrated and the error of the average output will increase. Therefore, in the fourth embodiment, the frequency division ratio correction unit 13b is changed to the frequency division ratio correction unit 13b as shown in FIG.

  The frequency division ratio correction unit 13b has a configuration in which RS-ff for performing a set / reset operation and a selector Sel_Msel for enabling / disabling the frequency division ratio selection signal for the frequency division ratio correction of the third embodiment are added to perform the frequency division. When the output of the ratio correction unit 13a is Msel ', the output of the selector Sel_Msel is input to the variable frequency dividing circuit 17 and the decimation filter 16 as a new frequency dividing ratio selection signal Msel.

  In this RS-ff, the set operation is performed at the carrier vertex timing Tc (n), and the reset operation is performed by the AD conversion decimator operation timing signal Td (m).

  Then, this RS-ff output is input to the selector Sel_Msel, and only when the RS-ff output is active (when 1), the frequency division ratio selection signal 1Msel ′ of the frequency division ratio correction unit 13a is directly corrected. When the output of RS-ff is 0, the frequency division ratio selection signal is forcibly output so that the decimation ratio = M when the output of RS-ff is 0. That is, when the RS-ff output is 0, the decimation ratio is not corrected.

  As a result, the number of operations of the correction operation is limited with respect to the PWM carrier cycle, so that the error of the average value is also limited, and even if noise at the carrier apex timing Tc (n) is mixed, it does not rapidly follow.

  FIG. 9 shows an operation example of the fourth embodiment.

  Although the third and fourth embodiments show examples of the integrator and the differentiator having three stages, of course, three stages as in the first embodiment, two stages as in the second embodiment, or three stages. Any number of stages other than stages can be applied. Since Embodiments 1 and 2 and Embodiments 3 and 4 have different functions and principles, it is obvious that they can be freely combined.

  If a measurement synchronization signal is generated instead of the PWM carrier signal, a plurality of signals such as current and voltage can be detected simultaneously and accurately. Therefore, high accuracy can be obtained for the instantaneous electric power, which is the product of current and voltage.

  In Embodiments 1 to 4, the power converter has been described as an example. These inventions can also be applied to the relay by using the measurement synchronization signal instead of the PWM carrier signal.

  Furthermore, it can be easily inferred that this principle can be applied to many applications, such as expansion to a grid interconnection device by synchronizing with a commercial power source.

  In contrast to the third embodiment, by limiting the timing of permitting correction for the frequency division ratio correction inside the decimation filter 16, even if the correction operation is likely to occur frequently, the correction operation is limited to only once in the average calculation period. Output accuracy can be prevented from decreasing.

  Further, by limiting the number of corrections, the timing signal Tc (n) transmitted from the digital control arithmetic unit 6 is gently adjusted so as not to be rapidly synchronized with an erroneous timing even if an erroneous signal is mixed due to noise. Can be followed synchronously.

  In order to show the effect of the method of the fourth embodiment, the results of numerical simulation are shown in FIGS. 10 and 11.

This set the following conditions.
(1) Reference clock frequency on analog detection side = 1 MHz (corresponding to the input clock of ΔΣ modulator 12)
(2) Decimation ratio of the decimation filter 16: M = 32 (2 ^ 5)
(3) Number of AD conversion outputs used for averaging = 4 times Modulator frequency that is the basis of AD conversion: Fc [Hz] = (1 MHz / 32) /4=7812.5 Hz
(4) The analog signal is a sine wave signal with an amplitude of ± 0.8. Then, the frequency of the carrier apex timing Tc (n) transmitted from the digital control calculation unit 6 is changed so that the operation on the AD conversion side follows it. I am letting you.

(1) Initial time difference ΔT = 22 [clk] at the start of operation (AD side is in a time delay state, which is set to zero by PLL operation)
(2) Frequency setting of carrier apex timing Tc (n) Period of 0 to 0.007 s: 7828.125 Hz (= 1.002 × Fc [Hz])
Period of 0.007 to 0.01 s: 7796.875 Hz (= 0.998 × Fc [Hz])
At the start of the operation, a time delay corresponding to 22 clk is set, and the frequency of the synchronization reference signal is set to 1.002 × Fc [Hz] with respect to the original AD conversion frequency of the analog detection unit 8 and the AD conversion is relatively delayed. It was set so that the time difference would be even wider. On the contrary, after 0.007 s, 0.998 × Fc [Hz] is set to the original AD conversion frequency, and switching is performed so that the operation timing on the AD conversion side advances.

  Under this condition, an example of an operation time chart when only the correction of the frequency dividing circuit is applied and the correction of the integrator is not applied in the first embodiment as shown in FIG. 4 is shown in FIG. On the other hand, the result of adding the integrator correction of FIG. 2 is shown in FIG.

The following signals are drawn on each chart.
(1) Uppermost stage: input analog signal, AD conversion data So (m), AD average value data So_ave (n)
(Here, the AD output is in the range of 0 to 1, but in order to match the scale with the analog signal, the AD conversion data is subjected to double gain correction and offset correction.)
(2) Second stage: time difference ΔT [clk]
(3) Third stage: Input to the LD terminal of the frequency division down counter (4) Fourth stage: Carrier apex timing Tc indicating the apex of the carrier signal and modulator operation timing signal Td (m)
In FIG. 11, the frequency division ratio is corrected by correcting the LD terminal of the frequency division counter from “31” to “31 ± 1” as in the third stage, and the second stage is corrected. Like the time difference, the initial time difference gradually decreases and converges to zero, and thereafter, the division ratio correction corresponding to the frequency difference occurs sporadically. As a result, it can be confirmed that the PLL function using the frequency dividing circuit operates normally.

  However, since the integrator correction is not applied, the AD conversion data So (m) at the uppermost stage does not have the same sine waveform as the analog input, and has an abnormal value. In FIG. 12, the scale at the top of FIG. 11 is changed, and an excessive abnormal signal of 300 times or more is generated with respect to the original amplitude of the AD input signal ± 0.8.

  On the other hand, when the decimation filter 16 of FIG. 2 which is the fourth embodiment is applied, the sine wave signal equivalent to the analog input is output as the AD conversion data So (m) as shown in FIG. It can be seen that the abnormal phenomenon can be dealt with.

  Further, FIG. 13 is an enlarged view of the time axis at the time when the initial time difference converges to zero (around 0.003 s), and the limiting function of the correction operation added in the fourth embodiment can be confirmed. The LD value of the Count1 at the third stage is corrected only at the timing of the first AD conversion after the rising of the square wave (the carrier reference pulse Tc (n) at the fourth stage) corresponding to the carrier signal. As a result, continuous frequency division ratio correction is prevented, and slow synchronization correction like the time difference of the second stage is realized.

  Further, FIG. 14 is an enlarged view of the time axis of the portion (around 0.009 s) at which the phase is sporadically advanced in the steady state after the synchronization is realized. This time, the value of the LD terminal of the Count1 of the third stage is sporadically corrected from 31 of the reference to 32, and the time difference accumulated by the frequency difference of (0.02 × Fs) is the carrier vertex timing Tc (n. When the time difference of −1 clock, that is, the AD timing, is detected as in the second stage, the frequency division ratio is corrected to M + 1 only once, whereby the timing of the next Tc (n + 1) (9. At about 44 [ms]), the time difference can be corrected to near zero.

  In the above, the present invention has been described in detail only for the specific examples described, but it is obvious to those skilled in the art that various variations and modifications are possible within the scope of the technical idea of the present invention, Of course, such variations and modifications are within the scope of the claims.

  Examples of application of the power converter include an inverter that drives a motor and a system interconnection device (PCS).

  It detects an analog signal that contains a steep ripple waveform and performs digital control. It has a function to speed up the sample of the AD converter to prevent sample leakage even with a pulse-like narrow waveform, and an integer PWM carrier signal. By performing AD conversion sampling at a doubled cycle and at a synchronized timing, a detection function that realizes accurate and high removal performance of harmonic components generated by PWM modulation is realized.

  Since the invention of the present application is not the product itself but the elemental technology of “ΔΣ type AD conversion synchronized with PWM modulation”, in Embodiments 1 to 4, an example of current detection of an inverter is taken up, but it can also be used for detection of other analog signals. Also, it can be applied to the following products other than inverters.

(1) Variable speed device Current detection and voltage detection, especially the voltage waveform is a square wave containing many harmonics, so high frequency samples are required.

(2) System interconnection device (PCS) connected to the electric power system, etc. The system voltage can be detected to generate a synchronization signal, and it can be applied to suppress resonance of an LC filter.

(3) Relay If a measurement synchronization signal is generated instead of the PWM carrier signal, a plurality of signals such as current and voltage can be detected simultaneously and accurately. Therefore, high accuracy can be obtained for the instantaneous electric power, which is the product of current and voltage.

3 ... PWM carrier generator 4 ... Digital control circuit 5 ... PWM comparator 6 ... Digital control calculation unit 7 ... Analog sensor 8 ... Analog detection unit 9 ... First reference clock oscillator 10 ... Second reference clock oscillator 11 ... PWM circuit 12 ... .DELTA..SIGMA. Modulators 13a, 13b ... Dividing ratio correction unit 14 ... Phase comparator 15 ... Dividing ratio correction selecting unit 16 ... Decimation filter 17 ... Variable dividing circuit 18 ... Averaging circuit 19 ... N divider

Claims (3)

A digital control arithmetic unit for outputting the PWM signal to the amplifier circuit;
An analog detection unit that detects a current or a voltage supplied to the load from the amplification circuit as an analog signal based on the PWM signal, converts the analog signal into a digital signal, and outputs the digital signal to the digital control calculation unit;
A delta-sigma AD converter having:
The digital control arithmetic unit,
A first reference clock oscillator for outputting a first reference clock;
A PWM carrier generator that outputs a synchronization timing signal to the analog detector,
The analog detector is
A second reference clock oscillator that outputs a second reference clock different from the first reference clock;
When the decimator operation timing signal occurs 1 clock or more earlier than the synchronization timing signal, the division ratio selection signal is set to 1, and when the time difference between the decimator operation timing signal and the synchronization timing signal is less than ± 1 clock, the When the frequency ratio selection signal is 0 and the decimator operation timing signal occurs later than the synchronization timing signal by one clock or more, the frequency ratio selection unit sets the frequency ratio selection signal to 2.
A variable frequency divider circuit that corrects the decimation ratio based on the frequency division ratio selection signal, and outputs the decimator operation timing signal based on the synchronization timing signal and the corrected decimation ratio,
A ΔΣ modulator that converts the analog signal into a digital signal at the timing of a second reference clock;
The digital signal output from the ΔΣ modulator includes an integrator connected in series of two or more, a decimator, and a differentiator connected in series of two or more, based on the frequency division ratio selection signal and the decimator operation timing signal. When the division ratio selection signal is 1, the input of the integrator is 0, when it is 0, the digital signal is input to the integrator of the first stage, and the output of the integrator of the previous stage is input to the integrators of the second and subsequent stages. When 2, the first-stage integrator inputs twice the digital signal, and the second-stage integrator inputs the value obtained by doubling the output of the preceding-stage integrator and the digital signal. When three or more series integrators are connected in series, the third and subsequent integrators use the value obtained by adding the output of the preceding integrator to the value obtained by doubling the output of the preceding integrator as the input, and the AD conversion data With decimation filter, which converts to ,
The delta-sigma AD converter, wherein the decimation filter outputs AD conversion data to the digital control arithmetic unit. A digital control arithmetic unit for outputting the PWM signal to the amplifier circuit;
An analog detection unit that detects a current or a voltage supplied to the load from the amplification circuit as an analog signal based on the PWM signal, converts the analog signal into a digital signal, and outputs the digital signal to the digital control calculation unit;
A delta-sigma AD converter having:
The digital control arithmetic unit,
A first reference clock oscillator for outputting a first reference clock;
A PWM carrier generator that outputs the carrier peak timing to the analog detection unit,
The analog detector is
A second reference clock oscillator that outputs a second reference clock different from the first reference clock;
When the carrier cycle average output timing signal obtained by dividing the decimator operation timing signal by N occurs earlier than the carrier apex timing by one clock or more, the division ratio selection signal is set to 1 and the carrier cycle average output timing signal and the carrier apex When the time difference from the timing is less than ± 1 clock, the division ratio selection signal is set to 0, and when the carrier cycle average output timing signal occurs 1 clock or more later than the carrier vertex timing, the division ratio selection signal And a frequency division ratio correction unit that is 2,
A variable frequency divider circuit that corrects the decimation ratio based on the frequency division ratio selection signal, and outputs the decimator operation timing signal based on the carrier vertex timing and the corrected decimation ratio,
A ΔΣ modulator that corrects the analog signal into the digital signal at the timing of a second reference clock;
The digital signal output from the ΔΣ modulator is provided as the frequency division ratio selection signal and the decimator operation timing signal, including an integrator connected in series of two or more, a decimator, and a differentiator connected in series of two or more. Based on this, when the frequency division ratio selection signal is 1, the input of the integrator is 0, when it is 0, the integrator of the first stage inputs the digital signal, and the integrators of the second and subsequent stages are the integrators of the previous stage. When the output is input and the value is 2, the integrator in the first stage inputs twice the digital signal, and the integrator in the second stage adds the value obtained by doubling the output of the integrator in the previous stage and the digital signal. When a value is input and the integrators are connected in series of 3 or more, the third and subsequent integrators input the value obtained by adding the output of the previous integrator to the doubled output of the previous integrator. Decimation to convert to AD conversion data With a filter,
A ΔΣ type AD characterized in that the AD conversion data output from the decimation filter is integrated N times and divided by N (N is a natural number of 2 or more) and the value is output to the digital control arithmetic unit as AD average value data. converter. The division ratio correction unit,
3. The ΔΣ type AD converter according to claim 2, wherein the decimation ratio is not corrected during a period other than after the occurrence of the carrier apex timing and before the output of the first decimator operation timing signal thereafter.

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