JP2017225210A - Δς type ad converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inexpensively implement accurate AD conversion without using an expensive high-frequency PLL circuit in a power converter or relay requiring AD conversion of voltage, current, etc.SOLUTION: Synchronization of a PWM carrier with decimeter operation timing is implemented by using reference clock oscillators having frequencies slightly differing from each other. A synchronization correction function is implemented by minutely changing a frequency division ratio selection signal Msel by adjusting a decimation ratio M inside a modulation filter. As a synchronization reference signal, there are two types of signals of a synchronization timing signal Ts(m) and a carrier peak timing Tc(m).SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power converter using PWM modulation or the like, and relates to a function for accurately converting an analog value such as a current or voltage waveform on which a ripple component of a carrier frequency of PWM modulation is superimposed into a digital value.

  A power converter or the like uses PWM modulation, and outputs a square wave voltage. Therefore, the ripple waveform of the harmonic component of the PWM carrier frequency is also superimposed on the current flowing through the load. Normally, analog signals including harmonics such as voltages and currents to which this PWM modulation is applied are converted into digital values by AD conversion, and control and measurement are performed using these as feedback signals.

  In order to improve the control response, it is necessary to speed up AD conversion to reduce detection delay, and in order to improve accuracy, a detection method that can easily remove unnecessary PWM harmonic components is required. Japanese Patent Application Laid-Open No. H10-228707 discloses an AD conversion of a current component to which such PWM modulation is applied.

  As described in FIG. 15 and FIG. 16, the feature of this Patent Document 1 is that the sampling period of current detection is set to an integral multiple of the carrier period with respect to the triangular wave carrier signal used for generating the PWM modulation, And it is synchronizing with the vertex of a triangular wave carrier signal.

  And the harmonic component resulting from a triangular wave carrier signal is suppressed (removed) by averaging the result of AD conversion for the period of a triangular wave carrier signal. In FIG. 17, sampling and AD conversion are performed at a sampling period of 8 times the triangular wave carrier frequency at the timing of circles m, m + 1,..., And the interval between the apexes of the triangular wave carrier signal, for example, Tc−2 sample data Eight points up to the previous sample data are averaged.

  However, even in the method of Patent Document 1, when sampling at a coarse discrete time, a thin ripple-like current waveform such as between 3 and 4 samples in the Tc-1 section of FIG. Even if it is taken, a detection error occurs.

  In order to suppress such errors due to the roughness of the sample, it is sufficient to shorten the sample period as much as possible and increase the number of sample points. To that end, in order to average high-speed AD converters and a large amount of point data A large-scale digital circuit or a high-speed computing unit is required.

A ΔΣ type AD converter is already widely used for digital audio and the like as an AD converter for sampling analog signals at high speed. A PWM carrier synchronization detection method using this ΔΣ AD converter will be examined. There are many circuit methods and arithmetic methods as the ΔΣ type AD converter, but this time, it will be described using Non-Patent Document 1. Non-Patent Document 1 describes the following figures and tables.
(1) FIG. 18: Configuration diagram of a second-order ΔΣ modulation modulator circuit.
(2) FIG. 19: Example of analog input and digital output data of ΔΣ modulation (1 bit output).
(3) FIG. 20: Configuration diagram of a decimation filter that converts a ΔΣ modulation modulator output into a data width of a plurality of bits. This circuit is also referred to as a “cascade integral comb (CIC) filter”, a “Sinc ³ (three-stage SINC function digital filter)” circuit, or the like.
(4) FIG. 21: Detailed circuit of the integrator in FIG. 20 (also called an integration circuit or an accumulation circuit).
(5) FIG. 22: Detailed circuit of the differentiator in FIG. 20 (also called a Comb circuit or a differential circuit).

  The outline | summary of these nonpatent literature 1 is demonstrated.

  FIG. 18 is a block diagram showing the basic principle of the modulator circuit of the ΔΣ type AD converter. The state of the analog input signal X (t) changes in synchronization with the reference clock Fclk as shown in FIG. Convert to data (DATA). FIG. 20 shows a configuration example of a circuit for converting continuous digital data (DATA) having a 1-bit width as shown in FIG. 19 into a discrete digital value having a multi-bit length, which is an integration cascaded in three stages. It comprises an I1, I2, I3, a decimator 30 that operates at a timing obtained by dividing the reference clock by M, and differentiators D1, D2, D3 cascaded in three stages.

  Here, the input signal (x (n) and the reference clock fs of the input signal) in FIG. 20 corresponds to (DATA and fclk) in FIG. Since the decimator 30 operates at a frequency F = fs / M obtained by dividing the reference clock fs by the decimation ratio M, the output signal y (m) in FIG. 20 is also updated at the operation timing of the decimator 30.

  FIG. 21 shows a detailed circuit for one stage of the integrators I1 to I3 in FIG. 20, and the adder 1 and a D-FF (D-Philip flop) circuit D-FF that latches the result are shown in FIG. It is configured. Here, the reference clock MCLK of the D-FF circuit D-FF is the above-described reference clock fs.

  FIG. 22 shows a detailed circuit for one stage of the differentiators D1 to D3 in FIG. 20, which includes a D-FF circuit D-FF that latches the previous input value and a subtractor 2. In the D-FF circuit D-FF of the differentiators D1 to D3, the reference clock MCLK divided by M is input as the reference clock (MCLK / M).

  FIG. 23 shows the circuit of FIG. 20 using the circuits of FIG. 21 and FIG. In this non-patent document 1, since the signal names are different for each figure, the input signal X (t) in FIG. 18 is changed to the input signal X (n) in FIG. 20 or the input MOUT in FIG. Equivalent to. The output signal y (m) in FIG. 20 corresponds to the signal CN5 in FIG.

The bit width of each signal is as follows.
.DELTA..SIGMA. Modulation modulator output signal DATA (X (n), MOUT) of FIG. 18 has a 1-bit width. , DN3, DN5), as described in Table 1, the required bit length (lower limit of the number of digits) is determined according to the decimation ratio M.

  In FIG. 20, the first block is not an integrator but a function of a special “+/−” input. This is the function of the same integrator as in FIG. 21, but the input signal shown in FIG. 19 is a binary 1-bit value “1/0”, whereas this is a positive / negative value “1 / −1”. This means that a special operation of integrating after converting to "" is added. In other words, the range of the output digital value has a positive and negative polarity amplitude from a negative maximum value to a positive maximum value.

  However, in the embodiments described later, this special operation is not applied in order to simplify the description, the input signal of the decimation filter is handled as “1/0”, and the output digital quantity has a minimum value of 0 and a positive maximum. It will be handled as single amplitude data having only a positive sign having a value.

  20 is represented as a D-FF circuit D-FF having terminals (input CN2, output DN0, clock CNR) in FIG. 23, and the reference clock MCLK is divided by M in this clock CNR. Signal (MCLK / M) is input.

As for the bit width of the internal signal in FIG. 23 described above, it is described in Table 1 that the necessary width is determined by a decimation ratio (decimation ratio): M. In the case of output data (the integration input of the first stage is “1 / −1”), the bit width of Bus Width [bits] or more in Table 1 is required, and the obtained resolution may be Gain _DC [bits]. It is shown.

Since there are many documents about the detailed principle of the decimation filter circuit of the ΔΣ type AD converter, and it is not directly related to the proposed technical contents, only the function description as described above is limited here. There are the following features.
(1) As shown in Table 1, the decimation ratio: M allows selection of a combination of the output data update cycle and the output data bit length (resolution).
(2) A high resolution of 16 bits or more can be realized relatively easily.
(3) The modulator section samples the analog signal with the reference clock fclk, and if an element that operates at a high clock frequency of fclk = 10 MHz or more is used, it is a substantially continuous sample for a PWM waveform of about several kHz. Can be approximated.

  Therefore, even if a thin ripple as pointed out in FIG. 17 exists, it is sampled at many points, and a more accurate AD conversion result can be obtained. A high-speed sample using ΔΣ type AD conversion like this method can also be expressed as “an analog signal is oversampled at a frequency M times the AD conversion output update frequency”.

The following terms will be used in the following description.
A circuit that converts the analog input of Non-Patent Document 1 shown in FIG. 18 into 1-bit data is “modulator”.
The clock fclk is a “modulator reference clock” or “reference clock”.
The whole circuit of FIG. 21 of Non-Patent Document 1 is a “decimation filter”.
The decimation ratio M in FIG. 21 of Non-Patent Document 1 is “decimation ratio: M”.
20 are “integrator”, “decimator”, and “differentiator”, respectively.
A circuit that generates a decimator operation signal from a reference clock is a “decimator divider or divider”.
The timing of the frequency divider output at which the decimator operates is “decimator operation timing”. This is also referred to as “AD output timing” because the output data of the AD converter is also updated.

  When such a ΔΣ modulator and a decimation filter with a decimation ratio: M are used, output data is updated in the M frequency division cycle of the reference clock while oversampling in the reference clock cycle.

  In the example of FIG. 24, the portion of the waveform surrounded by an ellipse is a period in which a single decimation output is measured, and if a high-speed clock as shown in the bottom modulator output timing is used, a thin ripple is used. Even if it is a component, a large number of samples that cannot be missed can be realized.

  Further, AD conversion is updated at the end of the period indicated by the ellipse, and this corresponds to “sample period of AD conversion in Patent Document 1”. Therefore, if “combination of reference clock and decimation ratio M” or “carrier frequency” is selected so that it is synchronized with the PWM carrier signal and becomes an integral multiple of the carrier frequency, “PWM of Patent Document 1” is selected. The advantages of both “ripple component removal capability” and “high oversampling function of ΔΣ AD converter of Non-Patent Document 1” can be combined. Thereby, even if it is an analog signal waveform containing a PWM ripple like FIG. 24, the AD conversion value which is easy to remove a ripple harmonic component correctly can be obtained. The above is the description of the prior art.

  However, in the prior art method, in order to synchronize the triangular wave carrier signal and the AD conversion output timing precisely, the reference clocks of both the PWM carrier generation circuit and the decimation filter circuit are matched, and the carrier signal on the PWM carrier generator side is further matched. And the decimator operation (AD output) timing on the ΔΣ AD converter side must be synchronized at the same time.

  For this reason, a PWM carrier oscillation circuit and a modulator or decimation filter circuit are usually arranged close to each other or mounted on the same integrated circuit, so that the circuit is operated with a common reference clock and timing signal. .

Japanese Patent Laid-Open No. 10-42569 JP-A-2-146939

  TEXAS INSRUMENTS Application Report SBAA094-June2003 `` Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Application ''

  However, in a large-capacity power converter or the like, the apparatus becomes large, so that the signal wiring becomes long. In particular, the gate signal wiring and analog signal wiring should be shortened so as not to be affected by noise. Therefore, the circuit of the control unit that generates the PWM signal is arranged on the main circuit side such as an IGBT, while the analog circuit and the AD conversion circuit on which the ΔΣ converter is mounted are arranged on the output terminal side on which the analog sensor is mounted. . And the structure which communicates by digital transmissions, such as a differential system which does not receive the influence of noise among them, is preferable.

  However, if the PWM generation unit and the AD conversion unit are arranged apart from each other as described above, it is difficult to share a reference clock because noise is easily mixed. Strictly speaking, even if a crystal unit having high frequency accuracy is used, there is a minute frequency difference. Therefore, the frequency difference is integrated over time, and the synchronization between the PWM carrier signal and the AD sample is shifted. .

  In such a case, as shown in FIG. 25, a method of synchronizing clocks of different circuits using a PLL oscillator PLL is used.

  The PWM carrier generator 3 transmits a synchronization timing signal Ts (m) at which AD conversion operates, and the AD conversion side uses a PLL phase synchronization circuit (PLL: Phase Locked Loop) with reference to the reception signal of the synchronization timing signal Ts (m). ) Is used to generate a clock Fclk_PLL synchronized with the reference clock on the transmission side.

  Then, the digital control circuit 4 on the PWM generation side generates a PWM command by performing a control calculation for realizing a function necessary as a power converter from the AD conversion result of the analog signal, and generates a PWM command from the PWM command and the PWM carrier signal. The comparator unit 5 outputs a PWM signal, thereby driving a load via an amplifier circuit INV such as an inverter and controlling it as intended.

  In addition, FIG. 20 of Non-Patent Document 1 shows an example in which the decimator 30 is arranged between the three-stage integrators I1 to I3 and the three-stage differentiators D1 to D3. Since it operates in one or two stages or more than three stages, it is not particularly limited to a three-stage Sinc filter circuit. However, if the number of stages is small, the resolution will decrease as shown in Table 1, so an appropriate selection is required according to the required performance.

  Patent Document 2 is disclosed as a prior art of a power converter using a PLL oscillator PLL.

  As described above, in power converters and relays that require AD conversion such as voltage and current, it is an issue to realize high-precision AD conversion at low cost without using an expensive high-frequency PLL circuit. Become.

  The present invention has been devised in view of the above-described conventional problems. One aspect of the present invention is a digital control arithmetic unit that outputs a PWM signal to an amplifier circuit, and a load supplied from the amplifier circuit based on the PWM signal. An analog detection unit that detects an electric current or a voltage as an analog signal, converts the analog signal into a digital signal, and outputs the digital signal to the digital control calculation unit, and includes the digital control calculation unit Includes a first reference clock oscillator that outputs a first reference clock and a PWM carrier generator that outputs a synchronization timing signal to the analog detection unit, and the analog detection unit is different from the first reference clock. A second reference clock oscillator for outputting a second reference clock, and a decimator operation timing signal one clock or more earlier than the synchronous timing signal The frequency division ratio selection signal is set to 1, and when the time difference between the decimator operation timing signal and the synchronization timing signal is less than ± 1 clock, the frequency division ratio selection signal is set to 0 and the decimator operation timing signal Occurs at least one clock later than the synchronization timing signal, a frequency division ratio correction unit that sets the frequency division ratio selection signal to 2, a decimation ratio is corrected based on the frequency division ratio selection signal, and the synchronization timing Two or more variable frequency dividing circuits that output the decimator operation timing signal based on the signal and the corrected decimation ratio, and a ΔΣ modulator that converts the analog signal into a digital signal at the timing of the second reference clock are connected in series. An integrator, a decimator, and two or more differentiators connected in series, and the ΔΣ modulator outputs Based on the division ratio selection signal and the decimator operation timing signal, the integrator input is set to 0 when the division ratio selection signal is 1, and the digital signal is input to the first-stage integrator when the division ratio is 0. The second and subsequent stages of integrators input the output of the previous stage integrator. When the number is 2, the first stage integrator inputs twice the digital signal, and the second stage integrator is the previous stage integrator. When the value obtained by doubling the output of the digital signal and the sum of the digital signals are input, and the integrators are connected in series in three or more series, the integrators in the third and subsequent stages are the same as the values obtained by doubling the output of the previous stage integrator. And a decimation filter that converts the value obtained by adding the outputs of the two stages of integrators into AD conversion data. The decimation filter outputs the AD conversion data to the digital control arithmetic unit. .

  As another aspect, a digital control arithmetic unit that outputs a PWM signal to an amplifier circuit, and a current or voltage supplied from the amplifier circuit to a load based on the PWM signal is detected as an analog signal, and the analog signal is converted into a digital signal. A ΔΣ AD converter comprising: an analog detection unit that converts the signal into a digital control operation unit; and the digital control operation unit outputs a first reference clock, A PWM carrier generator that outputs a carrier vertex timing to an analog detection unit, the analog detection unit outputting a second reference clock different from the first reference clock, and a decimator operation timing The carrier cycle average output timing signal obtained by dividing the signal by N is one clock lower than the carrier apex timing. If the time difference between the carrier cycle average output timing signal and the carrier vertex timing is less than ± 1 clock, the division ratio selection signal is set to 0. When the carrier cycle average output timing signal is generated one clock or more later than the carrier vertex timing, a division ratio correction unit that sets the division ratio selection signal to 2 and a decimation ratio based on the division ratio selection signal And a variable frequency dividing circuit for outputting the decimator operation timing signal based on the carrier vertex timing and the corrected decimation ratio, and a ΔΣ modulator for correcting the analog signal to the digital signal at the timing of a second reference clock Two or more integrators connected in series, a decimator, and two or more connected in series The digital signal output from the ΔΣ modulator is based on the division ratio selection signal and the decimator operation timing signal, and when the division ratio selection signal is 1, the input of the integrator is set to 0. When 0, the first-stage integrator inputs a digital signal, and the second and subsequent integrators input the output of the previous-stage integrator, and when it is 2, the first-stage integrator doubles the digital signal. Is input, and the second-stage integrator inputs the value obtained by doubling the output of the previous-stage integrator and the digital signal. When three or more integrators are connected in series, the third and subsequent stages are integrated. And a decimation filter for converting the output of the previous-stage integrator to a value obtained by adding the output of the previous-stage integrator to a value obtained by doubling the output of the previous-stage integrator, and converting the converted data into AD conversion data. The decimation filter outputs AD conversion data A value obtained by accumulating the data N times and dividing by N (N is a natural number of 2 or more) is output to the digital control arithmetic unit as AD average value data.

  Further, as one aspect thereof, the frequency division ratio correction unit does not correct the decimation ratio during a period other than after the occurrence of the carrier vertex timing until the first subsequent decimator operation timing signal is output. It is characterized by.

  According to the present invention, it is possible to realize highly accurate AD conversion at low cost without using an expensive high-frequency PLL circuit in a power converter or relay that requires AD conversion such as voltage and current. Become.

FIG. 3 is a block diagram illustrating a power converter according to the first embodiment. FIG. 2 is a schematic diagram illustrating a variable frequency divider and a decimation filter in the first embodiment. 3 is a time chart illustrating the operation of each unit of the power converter according to the first embodiment. Schematic which shows a variable frequency dividing circuit and a decimation filter. Schematic which shows a variable frequency dividing circuit and a decimation filter. FIG. 6 is a block diagram illustrating a variable frequency divider and a decimation filter in the second embodiment. FIG. 6 is a block diagram illustrating a power converter according to a third embodiment. FIG. 9 is a block diagram illustrating a frequency division ratio correction unit according to a fourth embodiment. 9 is a time chart showing an operation example of the fourth embodiment. FIG. 6 is an AD conversion input / output and an operation time chart of each signal to which the fourth embodiment is applied. 10 is an input / output of AD conversion to which the fourth embodiment is not applied and an operation time chart of each signal. The enlarged view of FIG. The enlarged view of FIG. The enlarged view of FIG. Schematic which shows the control apparatus of the power converter in patent document 1. FIG. 3 is a time chart showing each signal in Patent Document 1. The time chart which shows discrete time sampling. The block diagram of a secondary ΔΣ modulation module circuit. The figure which shows the example of the analog input of a delta-sigma modulation, and digital output data. The block diagram of a decimation filter. The detailed circuit diagram of the integrator inside a decimation filter. The detailed circuit diagram of the differentiator inside a decimation filter. The figure which showed the decimation filter of FIG. 20 with the integrator and the differentiator of FIG. 21, FIG. A time chart showing oversampling. The block diagram of the synchronous system between different printed boards using a PLL oscillator.

  The conventional system shown in FIG. 25 requires a PLL oscillator PLL that restores the reference clock from the synchronization timing signal Ts (m), and a high-frequency PLL circuit that operates at a high frequency.

  Therefore, in the present invention, the synchronization between the PWM carrier and the modulator operation timing of the AD converter is realized by using a reference clock oscillator having a slightly different frequency and without mounting a PLL circuit.

  Instead of correcting the reference clock in the PLL circuit, instead, the decimation ratio: M inside the decimation filter is adjusted to change the frequency division ratio of the modulator to a very small value (for example, M ± 1 with respect to M). Thus, the synchronization correction function is realized.

  As the synchronization reference signal, there are two types of signals: the carrier vertex timing Tc in FIG. 17 and the synchronization timing signal Ts (m) in FIG. Therefore, regarding the PLL function in the embodiment, an implementation method of synchronizing with the synchronization timing signal Ts is shown first, and then extended in order to synchronize with the carrier vertex timing Tc.

  Here, simply correcting the decimation ratio: M does not match all the integration times of the cascaded integrators I1 to I3, and only a part of the integrators is different from the pre-correction decimation ratio: M. Will be integrated. In this case, the AD conversion output after the differential circuit after the decimator becomes an abnormal value. Therefore, a method for preventing this abnormal output was devised.

  Hereinafter, Embodiments 1-4 of the power converter of the present invention will be described in detail.

[Embodiment 1]
The overall configuration of the first embodiment is shown in FIG. 1, and the schematic configuration is as follows. The digital control arithmetic unit 6 includes a PWM circuit 11 and outputs a carrier signal and a synchronization timing signal Ts (m) obtained by multiplying the triangular wave carrier period by N from the PWM carrier generator 3.

  The PWM comparator unit 5 compares the carrier signal with the PWM command to generate a PWM signal, and drives the load L via the amplifier circuit (inverter) INV. Information such as the input current of the load L is detected by the analog sensor 7, AD converted by the analog detection unit 8, and output to the digital control calculation unit 6 as a digital value.

  In the first embodiment, the above-described ΔΣ type is adopted as the AD converter, and the decimator operation timing signal Td (m) is synchronized with the timing of the synchronization timing signal Ts (m) received from the PWM carrier generator 3. .

  Next, the individual components in FIG. 1 will be described.

(1) Digital control arithmetic unit 6
A circuit on the PWM generation side, which is constructed by a synchronous digital circuit that operates by the first reference clock Fclk1 output from the first reference clock oscillator 9, and a digital control circuit 4 that generates a PWM command, and a PWM carrier generator 3 And a PWM circuit 11 having a PWM comparator (pulse output generator) 5 and a first reference clock oscillator 9 for outputting a first reference clock Fclk1.

  This digital control circuit 4 uses, as an input signal, data obtained by AD-converting an analog signal detected by an analog sensor 7 as described later, and outputs a PWM command corresponding to a voltage command necessary for controlling the load L based on this data. Output.

(2) Amplifier circuit INV and analog sensor 7
The amplifier circuit INV is a converter such as an inverter combined with a power semiconductor switching element, and amplifies the power to a PWM waveform necessary for actually driving the load L, that is, a pulsed voltage or current waveform. The analog sensor 7 detects output information of the amplifier circuit via a voltage sensor, a current sensor, or the like, and the AD conversion circuit 21 converts the analog signal into a digital quantity and supplies it to the digital control circuit 4 described above. To transmit.

(3) Load L
The digital control arithmetic unit 6 is an object to be controlled, and a motor, a power system, and the like correspond to this.

(4) Second reference clock oscillator 10
The second reference clock oscillator 10 outputs a second reference clock Fclk2 that is different from the first reference clock Fclk1.

(5) Analog detector 8
The analog detection unit 8 AD converts the output signal of the analog sensor 7 into a digital quantity handled by the digital control calculation unit 6. The circuit of the analog detection unit 8 uses a second reference clock Fclk2 that is different from the first reference clock Fclk1 on the PWM side. However, since a crystal resonator or the like is used, the frequency difference between them is very small. The analog detection unit 8 further includes the following elements.

(5-1) ΔΣ Modulator 12
The ΔΣ modulator 12 converts an analog value into a 1-bit length digital signal Si (k) at the timing of the second reference clock Fclk2 based on the principle of ΔΣ conversion. Strictly speaking, there is a circuit that outputs not only a 1-bit length but also a multi-bit length. Even in this case, the first embodiment is effective, but the first embodiment will be described using a 1-bit example.

(5-2) Frequency division correction unit 13a
This frequency division ratio correction unit 13a performs a function corresponding to phase correction of PLL control. In the phase comparator 14, the generation time t (Ts (m)) of the synchronization timing signal Ts (m) input from the outside, the generation time t (Td (m)) of the internal decimator operation timing signal Td (m), and The time difference (phase difference) ΔT = t (Td (m)) − t (Ts (m)) is detected.

  The frequency division ratio correction selection unit 15 operates as follows.

(1) When Td (m) is generated one clock or more earlier than Ts (m) (−1 [clk] ≧ ΔT)
Msel = (M + 1): Frequency division ratio selection signal (2) When the difference between Td (m) and Ts (m) is less than ± 1 clock (−1 <ΔT <1 [clk])
Mesl = (M): Frequency division ratio selection signal (3) When Td (m) is generated one clock or more later than Ts (m) (1 [clk] ≦ ΔT)
Msel = (M−1): Frequency division ratio selection signal The clock described in (1) to (3) is the second reference clock Fclk2.

  Here, M is an ideal decimation ratio (frequency division ratio with respect to the second reference clock Fclk2) assuming that Fclk1 = Fclk2.

In an actual circuit, the frequency division ratio selection signal Msel is a code value such as “0, 1, 2”, etc., but in the above description, the function description is displayed in order to make it easy to understand the relation with the description to be described later. An example in which the division ratio selection signal Msel is represented by a code value is shown below.
Condition (1) above: Frequency division ratio selection signal Msel = 1
Condition (2) above: Frequency division ratio selection signal Msel = 0
Condition (3) above: Frequency division ratio selection signal Msel = 2
Further, this time, it is assumed that the frequency error of the second reference clock Fclk2 is small, and the minimum correction amount, that is, the decimation ratio correction value is limited to (M ± 1).

  Practically, it is necessary to consider adding a filter function or correction coefficient to the time difference information, or making the correction amount ± 1 clock or more, but these have already been studied as PLL control. Therefore, here is a brief explanation of the principle.

  Further, in FIG. 1, instead of outputting the division ratio directly from the division ratio correction selection unit 15, a code called the division ratio selection signal Msel is output, and the decimation filter 16 and the variable division ratio are selected according to this code. The frequency division ratio is corrected inside the circuit 17.

  This is also made easy to understand by expressing it in the selector circuit having the same configuration in FIG. 2 described later, and it has a special meaning in that it is coded in the division ratio selection signal Msel corresponding to the function description. There is no.

(5-3) Variable frequency divider 17 and decimation filter 16
The variable frequency dividing circuit 17 and the decimation filter 16 are configured as shown in FIG. The variable frequency dividing circuit 17 includes a selector Sel_M1, a down counter Count1, and a comparator Comp1 that outputs a decimator operation timing signal Td (m) as “active (= 1)” when the counter value is zero. Has been.

  When the decimator operation timing signal Td (m) input to the load enable terminal LD becomes active (= 1), the down counter Count1 loads the value of the D input and outputs the Q output when the next clock is generated. To do. When the load enable terminal LD is not active, a normal countdown operation is performed until it becomes zero.

  Therefore, when the decimation ratio is M, if the value of (M−1) is set to the D terminal, the decimator operation timing signal Td (m) is applied at the timing divided by M with respect to the second reference clock Fclk2. Active (= 1).

  In the first embodiment, a variable frequency dividing function is added by expanding the D input to ± 1 with respect to a decimation ratio M that is a reference. Specifically, in order to realize the decimation ratio (frequency division ratio): {(M + 1), M, (M−1)} corresponding to the frequency division ratio selection signal Msel that is the output of the frequency division ratio correction selection unit 15. The values of {M, (M−1), (M−2)} are selected by the selector Sel_M1.

  The input signals of the selectors Sel_c11, Sel_c12, and Sel_c13 inserted in the previous stage of the integrators I1 to I3 have the following combinations according to the Msel signal.

(1) When Msel = M frequency division (basic decimation period, decimator operation timing signal Td (m) is synchronized with synchronization timing signal Ts (m))
Sel_c11: Digital signal Si (k) is selected (k indicates the timing of the second reference clock Fclk2)
Sel_c12: Selects the output of the D-FF circuit D-FF1 at the previous stage. Sel_c13: Selects the output of the D-FF circuit D-FF2 at the previous stage. ) If you want to delay
Sel_c11: Selects the input signal as zero. Sel_c12: Selects the input signal as zero. Sel_c13: Selects the input signal as zero. (3) When Msel = (M-1) frequency division If)
Sel_c11: Select twice the digital signal Si (k) Sel_c12: Select twice the output of the D-FF circuit D-FF1 in the previous stage and the added value of the digital signal Si (k) Sel_c13: D-FF circuit in the previous stage The double value of the output of the D-FF2 and the added value of the output of the D-FF circuit D-FF1 are selected. The reason why this input value is applied will be described later, but the important point of the first embodiment is the variable frequency division. The selector Sel_M1 for selecting the ratio corrects the PLL-controlled decimation timing. However, the selectors Sel_c11, Sel_c12, and Sel_c13 added to the integrators I1 to I3 always approximate the number of integrations between the decimation timings to M times. It is to make it. Therefore, adjustment is performed to correct the integrated amount by ignoring the input signal only once or doubling the input signal.

  Of the decimation filter portion, the first embodiment is changed to the three-stage integrators I1 to I3, and the subsequent portions are the decimator operation timing signal Td (output from the down counter Count1 as in the conventional case. m) and a three-stage differentiator, that is, a differentiator D1, a differentiator D2, and a differentiator D3, and the output of the last-stage differentiator D3 is the output of the AD converter. It is updated at the operation timing of the decimator. The above is the description of the configuration of the first embodiment.

(Description of action / operation)
First, in order to explain the variable frequency division operation, the relationship between the frequency division ratio selection signal Msel of the frequency division ratio correction unit 13a of FIG. 1 and the counter value QM of the down counter Count1 of FIG. Will be explained.

  The generation time t (Ts (m)) of the synchronization timing signal Ts (m) transmitted from the PWM circuit 11 as in the first stage in FIG. 3 and the decimator operation timing signal Td (as in the second stage in FIG. A time difference ΔT from the occurrence time t (Td (m)) of m) is detected as a phase difference of the PLL.

  Due to this time difference ΔT, the frequency division ratio selection signal Msel changes as in the fifth stage of FIG. If the time difference ΔT is within the range of (−1) to (+1) clocks, the Msel signal is set to “select frequency division ratio (decimation ratio) = M”. When the time difference ΔT is equal to or greater than (+1), the phase difference is regarded as being delayed by one clock or more, the division ratio selection signal Msel is set to “select division ratio = (M−1)”, and the decimator operation timing signal Td ( Correction is made so that the period of m) becomes shorter. Conversely, when the time difference ΔT becomes (−1) or less, the phase difference is considered to have advanced by one clock or more, and the division ratio selection signal Msel is set to “select division ratio = (M + 1)”, and the decimator operation timing signal Td (m ) So that the period becomes longer. Three types of states of the frequency division ratio selection signal Msel are represented as signals of zero and positive / negative levels in FIG.

  When the counter value QM at the third stage in FIG. 3 becomes zero by the frequency division ratio selection signal Msel, the decimator operation timing signal Td (m) as at the fourth stage in FIG. 2 is output to the load enable terminal LD of the frequency divider counter. The counter value QM of the down counter Count1 at the next clock becomes the value selected by the selector Sel_M.

  In the synchronization timing signal Ts (ma-1) and the synchronization timing signal Ts (ma) of FIG. 3, since "M division" is selected, (M-1) is loaded into the down counter Count1. In the case of the synchronization timing signal Ts (ma + 1), “M−1 division” is selected, so that (M−2) is selected, and in the case of Ts (mb), “M + 1 division” is selected. Therefore, (M) is loaded into the down counter Count1.

  As a result, the generation timing of the next decimator operation timing signal Td (m) to which the variable frequency division correction is applied is corrected so that the time difference from the synchronization timing signal Ts (m) is corrected within one clock. (PLL) function can be realized.

  FIG. 4 shows only the variable frequency division which is a part of the first embodiment, and the decimator is a conventional example. If the operation of the three-stage integrators I1 to I3 is viewed in chronological order as it is, the frequency division ratio (decimation ratio) changes every moment, so that the number of integrations at each decimation timing is M times or other than M times. Since they are mixed, a normal AD conversion result cannot be obtained even after passing through the three-stage differentiators D1 to D3 after decimation. Therefore, in the first embodiment, the integrators I1 to I3 are also improved, and FIG. 4 is changed as shown in FIG.

  FIG. 2 includes two types of frequency division correction functions with a frequency division ratio (decimation ratio) of (M−1) and (M + 1). Therefore, first, only the frequency division ratio is (M + 1). A case where correction is performed will be described.

  FIG. 5 is a diagram obtained by deleting the portion corresponding to the frequency division ratio (M-1) from FIG. According to FIG. 5, when the frequency division ratio (M + 1) is selected by the frequency division ratio selection signal Msel, the adder inputs of the integrators I1 to I3 are selected by one clock only when the initial value of the down counter Count1 is loaded. Sel_c1, Sel_c2, and Sel_c3 are forcibly switched to zero.

  As a result, the number of operations of the integration circuit is M + 1, but the integration can be stopped in a simulated manner for one time the down counter Count1 loads the initial value. In other words, by discarding the input signal at this time, it is possible to approximate the number of integrations to that performed M times.

  Discarding the input signal for one time causes an error. However, since the component of 1 bit width and an extremely short time for one clock input to the modulator is neglected, it may be ignored as being practically minute. it can. For example, in the case of M = 16, 2 ^ 16 = 65534 integrations are performed, but only one error is included.

  In addition, the frequency of occurrence of the frequency division correction is also due to the frequency difference between different reference clocks. If an oscillator with high frequency accuracy such as a crystal oscillator is used, the frequency of occurrence is very low. Considering the error with respect to the average value in the time interval, the influence is further reduced. Thus, paying attention to the fact that the ΔΣ modulator output has a 1-bit width and the amount of instantaneous information is small, it was decided to correct the number of integrations.

  Next, the correction operation of the integrators I1 to I3 in the case of the frequency division ratio (M-1) will be described. If the frequency division ratio is smaller than the basic number, such as (M−1), the approximation correction must be performed so that the number of integrations is increased by one.

  Therefore, the same timing as the correction of the division ratio (M + 1), that is, when the division ratio (M−1) is selected by the division ratio selection signal Msel, and the down counter Count1 is loaded with the initial value. Only when the timing is equivalent to one clock, the adder inputs of the integrators I1 to I3 are doubled, so that the correction is made as if the integration was performed for two clocks.

  This is realized by switching the selectors Sel_c11, Sel_c12, and Sel_c13 in FIG. 2 to the “M−1” side. However, in the first-stage integrator I1, it is only necessary to double the input signal. However, if an integrator for two clocks is simulated in the second-stage integrators I2 and I3, the amount of increase in the previous-stage integrator is increased. Must also be considered. Therefore, two integration operations (k) and (k + 1) will be described using a discrete expression.

  First, in the first (k) clock, the three-stage integrators I1 to I3 calculate based on the input and the previous integration result as shown in equation (1). Here, symbols are defined as follows.

k, (k + 1),...: number indicating the operation timing of the reference clock S _i (k): digital signal C ₁ (k), C ₂ (k) input to the decimation filter at the operation timing k of the reference clock , C ₃ (k): At the timing of the latch outputs (k) of the integrators I1 to I3 in the first, second, and third stages, the following equation (1) is executed.

Then, assuming that the same input signal continues, and approximating S _i (k) ≈S _i (k + 1), the calculation of the following equation (2) is executed at the timing of (k + 1).

  By substituting equation (1) into equation (2), time (n-1) data can be used as the previous value, and the operation results for two clocks reaching (n + 1) after time (n) can be calculated together. In each stage of the integrators I1 to I3, equations (3) to (5) are obtained.

  From this result, the integrator I1 in the first stage only needs to double the input value and add as shown in the equation (3). However, as shown in equations (4) and (5), the second and third integrators I2 and I3 not only double the output of the previous integrator, which is the original input signal. It can also be seen that the value of the output of the previous stage integrator (digital signal Si (k) in the case of the second stage integrator I2) must also be added.

  FIG. 2 shows the expressions (3) to (5) in the form of a block diagram. Thus, only one out of (M−1) integration operations is approximated to M integration operations by changing the input value to 2 clocks.

The error in this case is that in the first stage, a virtual input of S _i (k) ≈S _i (k + 1) is set. Similar to the (M + 1) frequency division correction operation, the error is 1 bit width and is applied to the modulator. This is a component for one input clock. Therefore, the influence of this error can also be ignored practically.

  As described above, in order to realize the PLL function for operating the ΔΣ type AD converter in synchronization with the AD conversion timing given from the outside, the decimation timing is generated according to the time difference (phase comparator). By applying a correction for making the period of the frequency variable, and further correcting the frequency division ratio, the integrators I1 to I3 in the decimation filter 16 are approximated to the number of frequency divisions without correction. A / D conversion can be executed accurately at the timing to be performed.

  In the first embodiment, high-precision AD conversion can be realized without using an expensive high-frequency PLL circuit in a power converter or relay that requires AD conversion such as voltage and current. Thereby, a power converter with high output accuracy can be realized at low cost.

  When the basic control circuit and the AD conversion circuit use different reference clocks, AD conversion can be executed in synchronization with the timing required by the control circuit.

  In the conventional method, a reference clock that is synchronized with one of the reference clocks is generated by a PLL oscillator. Even if the frequency of these reference clocks is slightly shifted, a frequency divider inside the decimation filter in the ΔΣ type AD conversion By adding a function for correcting the frequency division ratio of the conventional PLL oscillator, the conventional PLL oscillator can be made unnecessary.

  Further, with respect to the problem that a normal output cannot be obtained by changing the frequency dividing ratio of the frequency dividers for the multistage integrators I1 to I3 in the decimation filter 16, the integrator is stopped or integration is performed twice. Such a function is added and simulated as if it operates at a decimation ratio: M as a reference, so that the AD conversion output does not become an abnormal value.

  As for the error when the frequency division ratio is changed by the PLL correction, the output of the ΔΣ modulator 12 is only 1 bit width, and only an integration error for this 1 clock occurs.

  As for the frequency of the correction operation, if a crystal resonator or the like is used, the error of a plurality of clocks is very small, so it is considerably reduced. For example, if a 10 MHz crystal resonator with a frequency difference of 1 × 10 ^ (− 9) is used, the error frequency will be about 0.001 Hz. In this case, a deviation of one clock at a frequency of once every 100 seconds. If this is corrected, synchronization can be maintained.

  In other words, the error can be neglected and the frequency of occurrence is lower, so that the error can be neglected practically. Therefore, even if a PLL oscillator is not used, it is possible to achieve both required operation timing synchronization and accuracy maintenance.

[Embodiment 2]
The decimation filter 16 according to the first embodiment uses a cascade connection of three-stage Sinc functions (CIC circuits) as shown in FIG. The number of stages need not be three. Therefore, a configuration simplified to a two-stage Sinc function (CIC circuit) is referred to as the second embodiment. 1 is the same as that of the first embodiment, and only the decimation filter 16 is changed from FIG. 2 to FIG. In FIG. 6, the integrator I3, the selector Sel_13, and the operation unit for the input signal of this selector are deleted from FIG. 2, and the differentiator D3 is also deleted.

  Thereby, the accuracy (resolution) of the AD converter is lowered, but the circuit can be simplified.

[Embodiment 3]
In the first and second embodiments, the AD conversion-decimator operation timing signal Td (m), which is a PWM carrier frequency multiplied signal, is used as the reference timing as the AD conversion operation timing transmitted from the PWM circuit side.

  On the other hand, when averaging a plurality of AD conversion results in the carrier cycle period as in Patent Document 1, as shown in FIG. 7, the PWM carrier cycle is output to the output side of the AD conversion circuit 21 of the analog detection unit 8. I would like to build an averaging circuit (N times average) 18. The synchronization timing signal Ts (m) is also changed to the carrier vertex timing Tc (n) of the carrier signal that can specify the average period, and the AD average value data SO_ave (n) is synchronized with this to the digital control calculation unit 6. Want to send to.

  Therefore, the following functions are added to the first embodiment. First, Ts (m) corresponding to the AD conversion operation timing in FIG. 25 is changed to the carrier vertex timing Tc (n) at the carrier vertex time as shown in (Tc-2) or (Tc-1) in FIG.

  Since the carrier vertex timing Tc (n) corresponds to the frequency obtained by dividing the synchronization timing signal Ts (m) by N, in order to operate the phase comparator 14 of the frequency division ratio correction unit 13a in FIG. The carrier cycle average output timing signal Tc_ad (n) obtained by dividing the decimator operation timing signal Td (m) by N by the N divider 19 from the operation timing signal Td (m) is changed to a phase comparison signal.

  The frequency division correction unit 13a in FIG. 7 operates as follows in the same manner as in the first embodiment.

(1) When the carrier cycle average output timing signal Tc_ad (n) is generated one clock or more earlier than the carrier vertex timing Tc (n) (−1 [clk] ≧ ΔT)
Msel = (M + 1) signal for selecting frequency division (2) When the difference between the carrier cycle average output timing signal Tc_ad (n) and the carrier vertex timing Tc (n) is less than ± 1 clock (-1 <∠ΔT <1 [Clk])
Msel = (M) signal for selecting frequency division (3) When the carrier cycle average output timing signal Tc_ad (n) is generated one clock or more later than the carrier vertex timing Tc (n) (1 [clk] ≦ ΔT)
Msel = (M−1) Signal for Selecting Frequency Division The clock described in (1) to (3) is the second reference clock Fclk2.

  The carrier cycle average output timing signal Tc_ad (n) is also used as an average calculation and a transmission timing of the result.

  In the first and second embodiments, the synchronization timing signal Ts (m) is used as the timing signal transmitted from the PWM circuit side. This corresponds to a multiplied signal of the PWM carrier frequency in Patent Document 1, so that the AD conversion timing required by the PWM circuit side and the decimator operation timing for actually updating the AD conversion output can be synchronized.

  Furthermore, in patent document 1, the AD conversion result of several times within the carrier vertex timing Tc period is averaged. Therefore, let's assemble an averaging circuit (N times average) 18 for the PWM carrier period as shown in FIG. 7 on the AD converter side. For this purpose, it is necessary to transmit the execution timing of the averaging operation, that is, the carrier vertex timing Tc of the triangular wave carrier signal to the AD conversion side. Therefore, in FIG. 7, the synchronization timing signal Ts (m) is changed to the carrier vertex timing Tc (n) of the triangular wave carrier signal. Then, the decimator operation timing signal Td (m) corresponding to the N multiplication is generated by the variable frequency dividing circuit and used as the AD conversion timing.

  For detection of the time difference of the PLL operation, a carrier cycle average output timing signal Tc_ad (n) obtained by dividing the decimator operation timing signal Td (m) by N as shown in FIG. 7 is generated, and this and the carrier vertex timing Tc (n) Are compared, and a function such as a PLL is executed as in the first and second embodiments.

  The method related to the average calculation unit (N-time average) 18 in FIG. 7 is general and is not described in detail. However, the average calculation unit 18 stores N AD conversion results and integrates the results. And then divide by N. In the case of serial transmission, the averaged result is once latched, converted into a serial transmission signal, and output to the digital control arithmetic unit 6.

  Thereby, the analog detection unit 8 can synchronize the AD conversion timing and the average value calculation timing with respect to the signal transmitted from the digital control calculation unit 6 of the first embodiment or the second embodiment.

  If the third embodiment is applied, the timing signal from the digital control calculation unit 6 can be changed to the carrier vertex timing Tc of the carrier frequency. As a result, it is possible to perform an average operation on the output of AD conversion in a period synchronized with the carrier vertex timing Tc, and PWM ripple removal can be realized.

[Embodiment 4]
In the third embodiment, N outputs of the decimator operation timing signal Td (m) and AD conversion occur during the interval of the carrier vertex timing Tc (n) synchronized with the PWM carrier. As shown in FIG. 7, only by changing the phase synchronization timing to the N-fold cycle with respect to the first embodiment, a plurality of frequency division ratio corrections are executed out of N AD conversion results for one average calculation. There is a possibility.

  Even if the error caused by the division ratio correction per time is small, many correction operations of (M−1) and (M + 1) by the division ratio selection signal Msel are performed during the interval of the carrier vertex timing Tc (n). If the operation is repeated, the error is concentrated and the error of the average output also becomes large. Therefore, in the fourth embodiment, the frequency division ratio correction unit 13b as shown in FIG. 8 is changed to restrict the frequency division ratio correction operation from being concentrated.

  The configuration of the frequency division ratio correction unit 13b includes RS-ff that performs a set / reset operation for the frequency division ratio correction of the third embodiment and a selector Sel_Msel that enables / disables the frequency division ratio selection signal Msel. When the output of the ratio correction unit 13a is Msel ′, the output of the selector Sel_Msel is input to the variable frequency dividing circuit 17 and the decimation filter 16 as a new frequency division ratio selection signal Msel.

  In this RS-ff, the set operation is performed at the carrier vertex timing Tc (n), and the reset operation is performed at the decimator operation timing signal Td (m) for AD conversion.

  Then, the RS-ff output is input to the selector Sel_Msel, and the frequency division ratio selection signal 1Msel ′ of the frequency division ratio correction unit 13a is corrected as it is only when the RS-ff output is active (when 1). When the output Msel of the unit 13b is 0 and the output of RS-ff is 0, the division ratio selection signal is forcibly output so that the decimation ratio = M. That is, when the RS-ff output is 0, the decimation ratio is not corrected.

  As a result, since the number of operations in the correction operation is limited with respect to the PWM carrier cycle, the error of the average value is also limited, and even if noise at the carrier vertex timing Tc (n) is mixed, it does not follow rapidly.

  FIG. 9 shows an operation example of the fourth embodiment.

  Embodiments 3 and 4 show an example in which the integrator and the differentiator have three stages. Of course, three stages as in the first embodiment, two stages as in the second embodiment, and 3 stages. Any number of stages other than stages can be applied. Since Embodiments 1 and 2 and Embodiments 3 and 4 have different functions and principles, it is obvious that they can be freely combined.

  If a measurement synchronization signal is generated instead of a PWM carrier signal, a plurality of signals such as current and voltage can be detected simultaneously and accurately. Therefore, high accuracy can be obtained even for instantaneous power, which is the product of current and voltage.

  In the first to fourth embodiments, the power converter has been described as an example. By using the measurement synchronization signal instead of the PWM carrier signal, these inventions can be applied to the relay.

  Furthermore, it can be easily inferred that this principle can be applied to many applications, for example, if it is synchronized with a commercial power supply, it can be extended to a grid interconnection device.

  In contrast to the third embodiment, by limiting the timing for permitting correction for the division ratio correction in the decimation filter 16, even when correction operations are likely to occur frequently, the correction is limited to once in the average calculation period. Therefore, it is possible to prevent a decrease in output accuracy.

  In addition, by limiting the number of corrections, the timing signal Tc (n) transmitted from the digital control arithmetic unit 6 is moderate so that even if an erroneous signal is mixed due to noise, it is not rapidly synchronized with the erroneous timing. Can be synchronized.

  In order to show the effect of the system of the fourth embodiment, the results of the numerical calculation simulation are shown in FIGS.

The following conditions were set for this.
(1) Reference clock frequency on the analog detection side = 1 MHz (corresponding to the input clock of the ΔΣ modulator 12)
(2) Decimation ratio of the decimation filter 16: M = 32 (2 ^ 5)
(3) Number of AD conversion outputs used for averaging calculation = 4 times Modulator frequency that is the basis of AD conversion: Fc [Hz] = (1 MHz / 32) /4=7812.5 Hz
(4) The analog signal is a sine wave signal having an amplitude of ± 0.8. Then, the frequency of the carrier vertex timing Tc (n) transmitted from the digital control calculation unit 6 is changed to follow the operation on the AD conversion side. I am letting.

(1) Initial time difference ΔT = 22 [clk] at the start of operation (AD side is in a time delay state, which is made zero by PLL operation)
(2) Frequency setting of carrier vertex timing Tc (n) Period of 0 to 0.007 s: 7828.125 Hz (= 1.002 × Fc [Hz])
Period of 0.007 to 0.01 s: 779.875 Hz (= 0.998 × Fc [Hz])
At the start of operation, a time delay equivalent to 22 clk is set, and the frequency of the synchronization reference signal is also set to 1.002 × Fc [Hz] with respect to the original AD conversion frequency of the analog detection unit 8, and the AD conversion is relatively delayed. The time difference is set to open further. On the other hand, after 0.007 s, the operation is switched to 0.998 × Fc [Hz] with respect to the original AD conversion frequency so that the operation timing on the AD conversion side advances.

  FIG. 11 shows an example of an operation time chart in the case where only the frequency division circuit correction is applied in the first embodiment and the integrator correction is not applied as shown in FIG. 4 under this condition. On the other hand, FIG. 10 shows the result of adding the integrator correction of FIG.

The following signals are drawn on each chart.
(1) Uppermost stage: input analog signal, AD conversion data So (m), AD average value data So_ave (n)
(Here, the AD output is in the range of 0 to 1, but in order to match the scale with the analog signal, the AD conversion data is subjected to double gain correction and offset correction.)
(2) Second stage: time difference ΔT [clk]
(3) Third stage: input to LD terminal of frequency division down counter (4) Fourth stage: carrier vertex timing Tc indicating the vertex of the carrier signal and modulator operation timing signal Td (m)
In FIG. 11, the division ratio is corrected by correcting the LD terminal of the frequency dividing counter from “31” to “31 ± 1” as in the third stage, and the second stage. Like the time difference, the initial time difference gradually decreases and converges to zero, and thereafter, the frequency division ratio correction corresponding to the frequency difference occurs sporadically. Thereby, it can be confirmed that the PLL function using the frequency dividing circuit operates normally.

  However, since the integrator correction is not applied, the uppermost AD conversion data So (m) does not have the same sine waveform as the analog input, but has an abnormal value. FIG. 12 is a diagram in which the scale of the uppermost stage in FIG. 11 is changed, and an excessive abnormal signal of 300 times or more is generated with respect to the amplitude ± 0.8 of the original AD input signal.

  On the other hand, when the decimation filter 16 of FIG. 2 which is the fourth embodiment is applied, the AD conversion data So (m) is output as a sine wave signal equivalent to an analog input as shown in FIG. It can be seen that it is possible to take measures against the abnormal phenomenon.

  FIG. 13 is an enlarged view of the time axis of the time (near 0.003 s) when the initial time difference converges to zero, and the correction function restriction function added in the fourth embodiment can be confirmed. The LD value of the third-stage Count 1 is corrected only at the timing of the first AD conversion after the rising of the square wave (fourth-stage carrier reference pulse Tc (n)) corresponding to the carrier signal. As a result, prevention of continuous frequency division ratio correction and slow synchronization correction such as the second stage time difference are realized.

  FIG. 14 is an enlarged view of the time axis of a portion (near 0.009 s) where the phase is sporadically advanced in the steady state after synchronization is realized. This time, the value of the LD terminal of the third stage Count1 is corrected sporadically from 31 to 32 as a reference, and the time difference accumulated by the frequency difference of (0.02 × Fs) is the carrier vertex timing Tc (n ), And when the time difference of −1 clock, that is, AD timing advances as in the second stage, the frequency division ratio is corrected only once to M + 1, whereby the timing of the next Tc (n + 1) (9. In the vicinity of 44 [ms], the time difference can be corrected to near zero.

  Although the present invention has been described in detail only for the specific examples described above, it is obvious to those skilled in the art that various changes and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are naturally within the scope of the claims.

  Application examples of the power converter include an inverter that drives a motor, a grid interconnection device (PCS), and the like.

  This function detects and digitally controls analog signals that contain steep ripple waveforms, and functions to prevent sample leakage even with pulse-shaped thin waveforms by making the AD converter samples high-speed, and an integer of the PWM carrier signal By performing AD conversion sampling at a double cycle and synchronized timing, a detection function with high accuracy and high removal performance of harmonic components generated by PWM modulation is realized.

  Since the present invention is not a product itself but an elemental technique called “ΔΣ-type AD conversion synchronized with PWM modulation”, Embodiments 1 to 4 take up examples of inverter current detection, but can also be used to detect other analog signals. Moreover, it can be applied to the following products other than the inverter.

(1) Variable speed device Current detection and voltage detection, especially the voltage waveform is a square wave containing many harmonics, so a high frequency sample is required.

(2) System interconnection device (PCS) connected to the power system, etc. It can be applied to the detection of system voltage to generate a synchronization signal, suppression of LC filter resonance, and the like.

(3) Relay If a measurement synchronization signal is generated instead of a PWM carrier signal, a plurality of signals such as current and voltage can be detected simultaneously and accurately. Therefore, high accuracy can be obtained even for instantaneous power, which is the product of current and voltage.

DESCRIPTION OF SYMBOLS 3 ... PWM carrier generator 4 ... Digital control circuit 5 ... PWM comparator 6 ... Digital control calculating part 7 ... Analog sensor 8 ... Analog detection part 9 ... 1st reference clock oscillator 10 ... 2nd reference clock oscillator 11 ... PWM circuit 12 ... .DELTA..SIGMA. Modulators 13a, 13b... Division ratio correction unit 14 ... phase comparator 15 ... division ratio correction selection unit 16 ... decimation filter 17 ... variable frequency dividing circuit 18 ... averaging circuit 19 ... N frequency divider

Claims (3)

A digital control arithmetic unit for outputting a PWM signal to an amplifier circuit;
An analog detection unit that detects a current or voltage supplied from the amplifier circuit to the load based on the PWM signal as an analog signal, converts the analog signal into a digital signal, and outputs the digital signal to the digital control calculation unit;
A ΔΣ type AD converter comprising:
The digital control arithmetic unit is
A first reference clock oscillator for outputting a first reference clock;
A PWM carrier generator for outputting a synchronization timing signal to the analog detection unit,
The analog detection unit is
A second reference clock oscillator that outputs a second reference clock different from the first reference clock;
When the decimator operation timing signal is generated one clock or more earlier than the synchronization timing signal, the division ratio selection signal is set to 1, and when the time difference between the decimator operation timing signal and the synchronization timing signal is less than ± 1 clock, A division ratio correction unit that sets the division ratio selection signal to 2 when the division ratio selection signal is set to 0 and the decimator operation timing signal is generated at least one clock later than the synchronization timing signal;
A variable frequency divider that corrects a decimation ratio based on the frequency division ratio selection signal and outputs the decimator operation timing signal based on the synchronization timing signal and the corrected decimation ratio;
A ΔΣ modulator that converts the analog signal into a digital signal at the timing of a second reference clock;
Two or more integrators connected in series, a decimator, and two or more differentiators connected in series are provided, and the digital signal output from the ΔΣ modulator is based on the division ratio selection signal and the decimator operation timing signal. When the division ratio selection signal is 1, the integrator input is set to 0. When it is 0, the first-stage integrator inputs the digital signal, and the second and subsequent integrators input the output of the previous-stage integrator. In the case of 2, the first stage integrator inputs twice the digital signal, and the second stage integrator inputs the value obtained by doubling the output of the previous stage integrator and the digital signal, When three or more integrators are connected in series, the integrators in the third and subsequent stages receive AD converted data using the value obtained by adding the output of the preceding integrator to the value obtained by doubling the output of the preceding integrator. A decimation filter that converts to ,
The delta-sigma AD converter, wherein the decimation filter outputs AD conversion data to the digital control arithmetic unit. A digital control arithmetic unit for outputting a PWM signal to an amplifier circuit;
An analog detection unit that detects a current or voltage supplied from the amplifier circuit to the load based on the PWM signal as an analog signal, converts the analog signal into a digital signal, and outputs the digital signal to the digital control calculation unit;
A ΔΣ type AD converter comprising:
The digital control arithmetic unit is
A first reference clock oscillator for outputting a first reference clock;
A PWM carrier generator that outputs the carrier vertex timing to the analog detector,
The analog detection unit is
A second reference clock oscillator that outputs a second reference clock different from the first reference clock;
When the carrier cycle average output timing signal obtained by dividing the decimator operation timing signal by N is generated one clock or more earlier than the carrier vertex timing, the division ratio selection signal is set to 1, and the carrier cycle average output timing signal and the carrier vertex When the time difference from the timing is less than ± 1 clock, the division ratio selection signal is set to 0, and when the carrier cycle average output timing signal is generated one clock or more later than the carrier vertex timing, the division ratio selection signal A frequency division ratio correction unit for
A variable frequency divider that corrects a decimation ratio based on the division ratio selection signal and outputs the decimator operation timing signal based on the carrier vertex timing and the corrected decimation ratio;
A ΔΣ modulator that corrects the analog signal to the digital signal at a timing of a second reference clock;
Two or more integrators connected in series, a decimator, and two or more differentiators connected in series, and the digital signal output from the ΔΣ modulator is used as the division ratio selection signal and the decimator operation timing signal. Based on this, when the division ratio selection signal is 1, the input of the integrator is 0, and when it is 0, the first-stage integrator inputs the digital signal, and the second-stage and subsequent integrators are those of the previous-stage integrator. When the output is input, when the value is 2, the first-stage integrator inputs twice the digital signal, and the second-stage integrator adds the value obtained by doubling the output of the previous-stage integrator and the digital signal. When the value is input and three or more integrators are connected in series, the integrator after the third stage inputs the value obtained by adding the output of the previous stage integrator to the value obtained by doubling the output of the previous stage integrator. Decimation to convert to AD conversion data A filter, and
A ΔΣ-type AD characterized in that AD conversion data output from the decimation filter is integrated N times and a value obtained by dividing by N (N is a natural number of 2 or more) is output to the digital control arithmetic unit as AD average value data. converter. The division ratio correction unit
3. The ΔΣ AD converter according to claim 2, wherein the decimation ratio is not corrected during a period other than after the generation of the carrier apex timing until the first subsequent decimator operation timing signal is output.

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