JP2023166169A - Circuit arrangement and oscillator - Google Patents

Abstract

To provide a circuit arrangement and the like that can avoid inconvenience associated with installation of a high-order delta-sigma modulator.SOLUTION: A circuit arrangement 20 includes a frequency control circuit 52, a voltage control oscillation circuit 74, a multi-phase clock signal generation circuit 82, a phase interpolation circuit 88, and a control circuit 160. The phase interpolation circuit 88 selects a clock signal for comparison FBCK from a plurality of interpolation clock signals based on an interpolation control code CF. The control circuit 160 includes a delta-sigma modulator 162 that performs second- or more order delta-sigma modulation based on a division ratio setting code CDV, and an integrator 164 that integrates outputs from the delta-sigma modulator 162. The control circuit 160 outputs an integer dividing control code CN, and an interpolation control code CF based on an integrated value of the integrator 164. When the integrated value falls below the lower limit of a range, the control circuit 160 performs first processing P1 of raising an integer division ratio to -1 power for the integer dividing control code CN.SELECTED DRAWING: Figure 1

Description

The present invention relates to a circuit device, an oscillator, and the like.

For example, in a PLL circuit such as a fractional-N type PLL, the frequency division number of a frequency divider can be dynamically switched. Non-Patent Document 1 states that a multi-phase signal is generated from a clock signal from a voltage controlled oscillation circuit using a phase interpolation circuit, the signal is compared with a reference signal, and frequency division can be set by switching the phase. Disclosed.

J. Tao et al, "A 2.2-GHz 3.2-mW DTC-Free Sampling ΔΣFractional-N PLL With -110-dBc/Hz In-Band Phase Noise and -246-dB FoM and -83-dBc Reference Spur", IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 66, No. 9, pp. 3317-3328, Sep. 2019

In the configuration disclosed in Non-Patent Document 1, when a high-order delta-sigma modulator is used, the output range of the delta-sigma modulator is expanded to a negative value compared to a first-order delta-sigma modulator. Therefore, it becomes necessary to expand the input range of the phase interpolation circuit in response to the expansion of the output range of the delta-sigma modulator. This causes a problem that the linearity of the phase interpolation circuit deteriorates and the jitter performance also deteriorates.

One aspect of the present disclosure includes a frequency control circuit that generates a frequency control voltage based on a comparison result between a reference clock signal and a comparison clock signal, and a voltage controlled oscillation circuit that generates a clock signal with a frequency corresponding to the frequency control voltage. , a plurality of divided clock signals obtained by dividing a clock signal by an integer frequency division ratio based on an integer frequency division control code indicating an integer frequency division ratio, and outputting a plurality of divided clock signals with different phases. A phase clock signal generation circuit and a plurality of interpolated clock signals generated by phase interpolation based on the i-th divided clock signal and the i+1th divided clock signal of the plurality of divided clock signals based on the interpolation control code. It includes a phase interpolation circuit that selects a comparison clock signal, a delta-sigma modulator that performs second-order or higher-order delta-sigma modulation based on the division ratio setting code, and an integrator that integrates the output from the delta-sigma modulator. a control circuit that outputs a frequency division control code and an interpolation control code based on the integrated value of the integrator; when the integrated value is below the lower limit of the range, the control circuit outputs a frequency division control code; This relates to a circuit device that performs a first process of reducing an integer frequency division ratio by 1.

Another aspect of the present disclosure relates to an oscillator including the circuit device described above and a vibrator for generating a reference clock signal.

A configuration example of a circuit device according to the present embodiment. A configuration example of a frequency dividing circuit according to the present embodiment. FIG. 3 is a signal waveform diagram illustrating the operation of a phase interpolation type frequency dividing circuit. FIG. 3 is a diagram illustrating processing in a control circuit. FIG. 2 is a circuit diagram showing the configuration of a first-order delta-sigma modulator. FIG. 3 is a diagram illustrating details of processing in a control circuit. FIG. 3 is a diagram illustrating changes in signal waveforms when phase adjustment is performed. FIG. 6 is a diagram illustrating phase adjustment after carry-down processing. FIG. 4 is a diagram illustrating phase adjustment after carry-down processing. FIG. 3 is a circuit diagram showing the configuration of a second-order delta-sigma modulator. FIG. 2 is a circuit diagram showing the configuration of a third-order delta-sigma modulator. The figure which shows an example of the numerical value change of each node in a 3rd order delta-sigma modulator. 1 is a detailed first configuration example of a circuit device according to an embodiment of the present invention; A detailed second configuration example of the circuit device according to the present embodiment. FIG. 3 is a signal waveform diagram illustrating the operation of the circuit device of this embodiment. A detailed third configuration example of the circuit device according to the present embodiment. A first configuration example of an oscillator according to the present embodiment. A second configuration example of the oscillator of this embodiment.

This embodiment will be described below. Note that this embodiment described below does not unduly limit the contents described in the claims. Furthermore, not all of the configurations described in this embodiment are essential configuration requirements.

1. Circuit Device FIG. 1 shows a configuration example of a circuit device 20 of this embodiment. The circuit device 20 is, for example, an integrated circuit device called an IC (Integrated Circuit). For example, the circuit device 20 is an IC manufactured by a semiconductor process, and is a semiconductor chip in which circuit elements are formed on a semiconductor substrate. The circuit device 20 includes a PLL (Phase Locked Loop) circuit 150 and a control circuit 160. For example, in FIG. 1, the PLL circuit 150 detects the phase difference between the reference clock signal RFCK input to the PLL circuit 150 and the comparison clock signal FBCK, and sets the phase of the comparison clock signal FBCK to the phase of the reference clock signal RFCK. Perform synchronization processing. PLL circuit 150 includes a frequency control circuit 52, a voltage controlled oscillation circuit 74, and a frequency dividing circuit 80.

The frequency control circuit 52 compares the phases of the reference clock signal RFCK and the comparison clock signal FBCK. For example, if the comparison clock signal FBCK is behind the reference clock signal RFCK, the frequency control circuit 52 generates an up signal, and if the comparison clock signal FBCK is ahead of the reference clock signal RFCK in phase, the frequency control circuit 52 generates an up signal. If so, generate a down signal. The frequency control circuit 52 generates a phase difference signal that includes information about such phase. The frequency control circuit 52 then performs a charge pump operation based on the phase difference signal to generate a charge pump current. The frequency control circuit 52 then generates a control voltage that controls the oscillation frequency of the voltage controlled oscillation circuit 74 based on the charge pump current. Specifically, a loop filter circuit 72, which will be described later with reference to FIGS. 13 to 15, generates a control voltage based on the charge pump current.

The voltage controlled oscillation circuit 74 generates an oscillation signal whose oscillation frequency is controlled by the control voltage from the frequency control circuit 52. The oscillation signal then becomes the output signal of the PLL circuit 150 as the clock signal CK. Here, the clock signal CK is also input to the frequency dividing circuit 80, and the frequency divided clock signal DVCK after frequency division processing in the frequency dividing circuit 80 is inputted to the frequency control circuit 52 as the comparison clock signal FBCK. Ru. The comparison clock signal FBCK is, for example, a feedback clock signal. The voltage controlled oscillator circuit 74 is, for example, a VCO (Voltage controlled oscillator). The voltage controlled oscillation circuit 74 may be realized by an LC type oscillation circuit using an inductor and a capacitor, or may be realized by a loop type oscillation circuit in which a plurality of inverter circuits are connected in a loop.

FIG. 2 shows a configuration example of the frequency dividing circuit 80, and FIG. 3 shows a signal waveform diagram explaining the operation of the frequency dividing circuit 80. The frequency dividing circuit 80 shown in FIG. 2 is a configuration example of a phase interpolation type frequency dividing circuit 80. Frequency dividing circuit 80 includes a multiphase clock signal generation circuit 82 and a phase interpolation circuit 88. Further, the phase interpolation circuit 88 includes a multiplexer 86 and an interpolation circuit 87. Note that the configuration of the frequency dividing circuit 80 is not limited to the configuration shown in FIG. 2, and some of these components may be omitted, other components may be added, or some components may be replaced with other components. Various modifications such as replacement are possible.

The frequency dividing circuit 80 divides the frequency of the clock signal CK and outputs the divided clock signal DVCK. For example, the voltage controlled oscillation circuit 74 generates a clock signal CK having a frequency that is multiplied by the frequency of the reference clock signal RFCK. The multiplication number in this case is set by the frequency division ratio of the frequency dividing circuit 80. The frequency dividing circuit 80 is, for example, a decimal point frequency dividing circuit capable of performing decimal point frequency division with a frequency division ratio including a decimal number. For example, a phase interpolation type frequency dividing circuit or the like can be used as the frequency dividing circuit 80. This makes it possible to realize a fractional-N type PLL circuit. In this manner, the frequency dividing circuit 80 divides the frequency of the clock signal CK in the PLL circuit 150, and feeds back the divided clock signal DVCK to the frequency control circuit 52 as the comparison clock signal FBCK.

The multiphase clock signal generation circuit 82 includes frequency dividers 83 and 84 and five flip-flop circuits FF. The frequency divider 83 is a frequency dividing circuit that divides the frequency by two. Specifically, the frequency divider 83 receives a clock signal CK and a clock signal XCK obtained by inverting the clock signal CK, and outputs signals I, Q, IB, and QB obtained by dividing these signals by two. When the period of the clock signal CK is TVCO, as shown in FIG. 3, the periods of the signals I, Q, IB, and QB divided by two are 2×TVCO. That is, the frequencies of the signals I, Q, IB, and QB are 1/2 of the frequency of the clock signal CK. Further, with respect to the signal I, the signals Q, IB, and QB are signals whose phases are delayed by 90 degrees, 180 degrees, and 270 degrees, respectively. In this way, the signals I, Q, IB, and QB are signals whose phases are shifted by 90 degrees.

The frequency divider 84 is a frequency dividing circuit called a feedback divider (FDIV). Specifically, the frequency divider 84 divides the signal QB by a set integer frequency division ratio N and outputs the signal FDIVCLK. Then, by inputting and sampling the signal FDIVCLK to the CK terminal of the flip-flop circuit FF, in which the signals I, Q, IB, and QB are input to the D terminal, the signals I, Q, IB, and QB are input to the D terminal of the flip-flop circuit FF. Frequency-divided clock signals P0, P90, P180, and P270 are output. In addition, by inputting and sampling the signal FDIVCLK to the CK terminal of the flip-flop circuit FF to which the frequency-divided clock signal P0 is input to the D terminal, the frequency-divided clock signal P360 is output from the Q terminal of the flip-flop circuit FF. Ru.

As shown in the signal waveform diagram of FIG. 3, frequency-divided clock signals P0, P90, P180, P270, and P360 are generated by dividing signals I, Q, IB, QB, and I by an integer frequency division ratio N by a frequency divider 84. It is a divided signal. For example, when the periods of the signals I, Q, IB, QB, and I are 2×TVCO, the periods of the divided clock signals P0, P90, P180, P270, and P360 are N×2×TVCO. Furthermore, the frequency-divided clock signals P0, P90, P180, P270, and P360 are signals whose signal levels change at edges corresponding to the edges of the signals I, Q, IB, QB, and I. The phase difference between P0 and P90 corresponds to the phase difference between I and Q, and the phase difference between P90 and P180 corresponds to the phase difference between Q and IB. The phase difference between P180 and P270 corresponds to the phase difference between IB and QB, and the phase difference between P270 and P360 corresponds to the phase difference between QB and I.

In this way, the multiphase clock signal generation circuit 82 generates a plurality of divided clock signals P0, P90, which are clock signals obtained by dividing the clock signals CK and , P180, P270, and P360.

The control circuit 160 in FIG. 1 controls the PLL circuit 150 in the circuit device 20. Control circuit 160 includes a delta-sigma modulator 162 and an integrator 164. Control circuit 160 includes a delta-sigma modulator 162 that performs delta-sigma modulation based on a frequency division ratio setting code CDV, and an integrator 164 that integrates the output of the delta-sigma modulator. The delta-sigma modulator 162 performs delta-sigma modulation based on the fractional part of the frequency division ratio of the frequency division ratio setting code CDV, and the integrator 164 performs integration processing of the output of the delta-sigma modulator 162. Then, the control circuit 160 outputs an integer frequency division control code CN for setting an integer frequency division ratio N to the multiphase clock signal generation circuit 82 of the frequency division circuit 80. Further, the control circuit 160 outputs an interpolation control code CF based on the integrated value of the integrator 164 to the multiplexer 86 of the frequency dividing circuit 80 and the interpolation circuit 87.

Phase interpolation circuit 88 includes a multiplexer 86 and an interpolation circuit 87. The multiplexer 86 outputs divided clock signals P0, P90, P180, P270, P360 based on, for example, M[4:3], which is the upper bits of M[4:0], which is the interpolation control code CF from the control circuit. The i-th frequency-divided clock signal PCK1 and the i+1-th frequency-divided clock signal PCK2 are selected from among them. For example, if it is determined that the first quadrant is from 0 to 90 degrees based on M[4:3], which is the upper bit of the interpolation control code CF, the divided clock signals P0 and P90 are used as PCK1 and PCK2. If selected and determined to be in the second quadrant of 90 to 180 degrees, P90 and P180 are selected as PCK1 and PCK2. Furthermore, if it is determined that the third quadrant is between 180 and 270 degrees based on M[4:3], which is the upper bit of the interpolation control code CF, P180 and P270 are selected as PCK1 and PCK2, and 270 degrees are selected as PCK1 and PCK2. If it is determined that it is in the fourth quadrant of ~360 degrees, P270 and P360 are selected as PCK1 and PCK2.

Then, the interpolation circuit 87 generates an interpolation control code CF M[4:0] from a plurality of interpolated clock signals generated by phase interpolation based on the i-th frequency-divided clock signal PCK1 and the i+1-th frequency-divided clock signal PCK2. For example, the interpolated clock signal selected based on the lower bits of M[2:0] is output as the frequency-divided clock signal DVCK. Here, i is an integer of 1 or more. Furthermore, PCK1 and PCK2 are also included in the interpolation clock signals to be selected. For example, assume that the first quadrant is determined based on M[4:3], which is the upper bit of the correction control code, and the frequency-divided clock signals P0 and P90 are selected as PCK1 and PCK2. In this case, the interpolation circuit 87 performs interpolation control from a plurality of interpolated clock signals generated by 8-division phase interpolation based on the i-th frequency-divided clock signal PCK1=P0 and the i+1-th frequency-divided clock signal PCK2=P90. The interpolated clock signal selected based on M[2:0], which is the lower bit of the code, is output as the divided clock signal DVCK. For example, the k-th interpolated clock signal between the m-th interpolated clock signal and the n-th interpolated clock signal buffers the output terminal of the buffer that buffers the m-th interpolated clock signal and the n-th interpolated clock signal. It can be generated by shorting the output terminals of the buffer and causing the signals to collide. Here, m, k, and n are integers of 1 or more that satisfy the relationship m<k<n. For example, by connecting the output terminal of a buffer that buffers PCK1 and the output terminal of a buffer that buffers PCK2 and causing the signals to collide, the fourth phase-divided interpolated clock signal can be generated. By connecting the output terminal of the buffer that buffers PCK1 and the output terminal of the buffer that buffers the fourth interpolated clock signal of phase division and causing the signals to collide, generate the second interpolated clock signal of phase division. can. The interpolated clock signal generated in this way is often a narrow pulse signal.

In this way, the interpolation circuit 87 converts the plurality of frequency-divided clock signals P0, P90, P180, P270, and P360 into the i-th frequency-divided clock signal PCK1 and the i+1-th frequency-divided clock signal PCK2 based on the interpolation control code CF. A frequency-divided clock signal DVCK, which is a clock signal for phase comparison with a reference clock signal RFCK, is selected from a plurality of interpolated clock signals generated by phase interpolation based on the reference clock signal RFCK. By doing so, a phase interpolation type frequency dividing circuit 80 can be realized. According to the phase interpolation type frequency divider circuit 80, by using an interpolated clock signal phase-divided with high resolution, the width of frequency fluctuation due to delta-sigma modulation can be reduced, and phase noise can be reduced. It becomes possible to generate the clock signal CK.

For example, in FIG. 2, the phase is divided into four by the multiphase clock signal generation circuit 82, and the phase is divided into eight by the interpolation circuit 87, thereby performing phase division into 32 divisions. Then, an interpolation control code CF based on the integrated value of the integrator 164 that integrates the output of the delta-sigma modulator 162 selects one of these 32-divided phase clock signals and outputs it as the frequency-divided clock signal DVCK. be done. In this case, the phase is integrated by the integrator 164 that integrates the output of the delta-sigma modulator 162, and for example, at the timing of transition from 31 of the 32 phase divisions to 0, that is, at the timing when the phase completes one cycle, As shown at H1 in FIG. 3, a carry signal is output from the control circuit 160 to the frequency divider 84. As a result, the integer frequency division ratio of the frequency divider 84 is carried up from N to N+1, as shown by H2. Note that at the timing of transition from 0 to 31 of the 32 phase divisions, a carry-down signal is output from the control circuit to the frequency divider 84, and the integer frequency division ratio of the frequency divider 84 is carried down. become.

FIG. 4 is a diagram illustrating processing in the control circuit 160 and interactions between the control circuit 160 and the frequency dividing circuit 80. The control circuit 160 generates the above-mentioned integer frequency division control code CN and interpolation control code CF based on the frequency division ratio setting code CDV, and outputs them to the frequency division circuit 80. The frequency division ratio setting code CDV is the number of frequency division settings used when the frequency division circuit 80 of the PLL circuit 150 divides the frequency of the comparison clock signal FBCK. Specifically, the frequency division ratio setting code CDV is a positive number, and may be an integer or a number including a decimal part. The frequency division ratio setting code CDV is a code that can be used by the circuit device 20 to output a clock signal CK of a desired frequency, and can be set by the user, for example.

The integer frequency division control code CN is a code that can be used to adjust the integer part of the frequency division number when the frequency division circuit 80 divides the clock signal CK. Therefore, the integer frequency division control code CN is an integer. The interpolation control code CF is a code that can be used to adjust the fractional part of the frequency division number when the frequency division circuit 80 divides the frequency of the clock signal CK. That is, the frequency dividing circuit 80 can perform integer frequency division processing based on the integer frequency division control code CN, and can perform more detailed phase adjustment based on the interpolation control code CF.

In FIG. 4, a given frequency division ratio setting code CDV is input to the control circuit 160. The frequency division ratio setting code CDV is a positive number as described above, but in FIG. 4, the integer part is N, the decimal part is f, and N. It is expressed as f. Further, in the arithmetic processing shown in the control circuit 160, QUOTIENT indicates an operation for obtaining the integer part of the quotient of division, and MOD is an operation for obtaining the remainder of division. The + written inside the circle corresponds to the adder. For example, although adder 161 and adder 163 are shown as adders in FIG. 4, addition operations in adder 161 and adder 163 are realized by time-sharing processing, etc. of the same adder. Good too. This point also applies to FIGS. 5 and 10 to 11, which will be described later.

First, the control circuit 160 outputs the frequency division ratio setting code CDV. When f is given, the calculation of QUOTIENT (N.f/2) shown by b in FIG. 4 is performed. That is, the control circuit 160 has N. Find the quotient when f is divided by 2. For example, N. When f is 10.3, 5 is obtained by the operation indicated by b. Then, the control circuit 160 outputs the calculation result to the adder 163. In addition, in the calculation shown in b, the frequency division ratio setting code CDV, N. The reason why the integer part N of f is not directly used corresponds to the fact that the clock signal CK output from the voltage controlled oscillation circuit 74 is first halved in frequency and then divided by N.

Next, the control circuit 160 controls the N. Perform the calculation f-QUOTIENT(N.f/2)×2. That is, the control circuit 160 controls the N. From f, N. Subtract the number obtained by multiplying the quotient of f/2 by 2. For example, as above, N. When f is 10.3, 0.3 is obtained by the calculation indicated by a. That is, the calculation shown in a is performed using the frequency division ratio setting code CDV. When f is given, a process is performed to extract f, which is the decimal part. The decimal part of the frequency division ratio setting code CDV obtained by the calculation shown in a is written as u. Then, the control circuit 160 inputs the calculation result u to the calculation processes shown in c and d.

In the calculation shown in c, the control circuit 160 performs MOD(u/0.0625)×16. That is, an operation is performed in which the remainder when the operation result u shown in a is divided by 0.0625 is multiplied by 16. N. When f is 10.3, 0.8 is obtained by the calculation indicated by c. Control circuit 160 then outputs the calculation result to delta-sigma modulator 162.

In the calculation shown in d, the control circuit 160 performs QUOTIENT (u/0.0625). That is, a calculation is performed to find the quotient when the calculation result u shown in a is divided by 0.0625. N. When f is 10.3, 4 is obtained by the operation indicated by d. Then, the control circuit 160 outputs the calculation result to the adder 161.

Next, the control circuit 160 uses the delta-sigma modulator 162 to process the calculation result of c. FIG. 5 shows a configuration example of a first-order delta-sigma modulator, which is the most basic configuration of the delta-sigma modulator 162. The delta-sigma modulator 162 can be configured with an adder, a quantizer, and a delay device. Note that the high-order delta-sigma modulator 162 described with reference to FIGS. 10 and 11 also includes a differentiation circuit in addition to these. The quantizer performs processing to output input and output signals as quantized discrete values. Here, noise when the input signal is quantized in the quantizer 172 is referred to as quantization noise Q1. For example, when a quantizer quantizes an input signal using discrete values such as 1, 2, 3, etc., if the input signal X is 0.8, a quantized value of 1 is output. The difference between 0.8 of the input and 1 of the output, 0.2, becomes the quantization noise Q1. Further, the delay device performs processing to delay the phase of the clock signal by one clock. Note that a delay of one clock refers to a delay of one signal period. As shown in FIG. 5, the first-order delta-sigma modulator 162 has a basic circuit configuration in which an adder 171 and a quantizer 172 are provided in series. The configuration is such that the results of processing by an adder 173 and a delay device 174 provided in parallel are fed back to the adder 171. As shown in FIG. 5, when X is input to the input of the delta-sigma modulator 162, the output Y1 of the delta-sigma modulator 162 becomes X+(1-Z ⁻¹ )Q1 in a steady state. Note that the delta-sigma modulator 162 used in this embodiment is assumed to be a second-order or higher-order delta-sigma modulator that will be explained later with reference to FIGS. 10 and 11.

Then, in FIG. 4, the delta-sigma modulator 162 inputs the output result to the adder 161. Adder 161 adds the calculation result indicated by d and the output of delta-sigma modulator 162, and outputs the result to integrator 164.

The accumulator 164 performs a process of accumulating the calculation results sequentially input from the adder 161. Specifically, the accumulator 164 accumulates the calculation results sequentially output from the adder 161, and generates the integer frequency division control code CN and the interpolation control code CF through processing based on the accumulation results. As explained in FIG. 2, in the frequency dividing circuit 80, the multiplexer 86 and the interpolation circuit 87 can generate a clock signal whose phase is changed at intervals of 2π/32 for a clock signal whose period is 2×TVCO. . The phase interpolation circuit 88 of the frequency dividing circuit 80 can generate a clock signal having a predetermined interpolation phase based on the interpolation control code CF set by the integrator 164. In FIG. 4, the output signal Sum from the integrator 164 to the phase interpolation circuit 88 corresponds to the interpolation control code CF to the phase interpolation circuit 88.

Further, the integrated value in the integrator 164 may be 32 or more. For example, when the integrated value is 32 and the phase is (2π/32)×32=2π, the phase shift is exactly one cycle. In this case, integrator 164 outputs CarryUp, which is a carry-up signal, to adder 163. The carry-up signal is a signal that increases the integer frequency division control code CN by 1. As described above, when the integrated value exceeds a value corresponding to one period, that is, 32, which is the upper limit of the range, the process in which the control circuit 160 increases the integer frequency division control code CN by 1 is referred to as third process P3. When the integrated value becomes a number greater than 32, for example 35, the integrator 164 performs a third process P3 of outputting a carry-up signal to the adder 163, and interpolates 3, which is the amount exceeding 32 and requiring phase interpolation. It is output to the phase interpolation circuit 88 as a control code CF. On the other hand, the calculation result indicated by b and the carry-up signal of the multiplier 164 are input to the adder 163, and an addition process is performed thereon. Then, the adder 163 outputs the addition result to the frequency divider 84 of the multiphase clock signal generation circuit 82. By processing the frequency division ratio setting code CDV in this way, the control circuit 160 generates the integer frequency division control code CN and the interpolation control code CF, and based on these, the frequency division circuit 80 uses the clock signal CK is divided to a desired frequency division ratio.

2. Processing in Control Circuit Next, detailed processing contents of the control circuit 160 in this embodiment will be described using FIG. 6. The arithmetic processing shown in FIG. 6 differs from the one described in FIG. 4 in the arithmetic processing regarding carry-up. In the arithmetic processing shown in FIG. 4, the integrator 164 outputs a carry-up signal when the integrated value exceeds 0 to 31, and the integer frequency division control code CN is incremented by +1. However, in reality, the integrated value of the integrator 164 may become a negative value. If the integrated value becomes a negative value, for example, the calculation result at d may be added to the output of the delta-sigma modulator, resulting in a negative value. Further, there are cases where the integrated value corresponds to two cycles or more, that is, 64 or more. A case where the integrated value becomes +64 or more is, for example, a case where the integrated value still becomes 32 or more even if carry-up calculation processing is performed and the integer frequency division control code CN is increased by +1.

When the high-order delta-sigma modulator 162 is used in this manner, the output range of the delta-sigma modulator 162 is expanded, and the input range to the phase interpolation circuit 88 is also expanded accordingly. In this case, in the phase interpolation circuit 88, in order to expand the input range and achieve the same resolution, it becomes necessary to generate an interpolated clock signal by repeating collisions of more signals, and the frequency-divided clock signal is The phase error of DVCK becomes larger. In order to eliminate such a problem, the processing of the control circuit 160 shown in FIG. 6 is improved from the processing of the control circuit 160 described in FIG. 4. Specifically, it is possible to handle not only carry-up of integer frequency division control code CN by +1, but also arithmetic processing of incrementing integer frequency division control code CN by -1 or +2.

In the arithmetic processing shown in FIG. 6, in order to cope with the case where the integrated value of the integrator 164 becomes a negative value, a carry-down arithmetic processing is provided in which the integer frequency division control code CN is decreased by one. In this way, when the integrated value in the integrator 164 becomes a negative value, the process of subtracting the integer frequency division control code CN by 1 is called a first process P1. Further, in order to cope with the case where the integrated value of the integrator 164 becomes +64 or more, an arithmetic process called carry-up +1 is provided in which the integer frequency division control code CN is increased by +2. That is, when the integrated value after the third processing P3 described above exceeds 32, which is the range width corresponding to one cycle, carry-up +1 is performed to increase the integer frequency division ratio by +2 for the integer frequency division control code CN. . This carry-up +1 process is referred to as fourth process P4. In this way, regarding the range of the integer frequency division control code CN, if the integrated value becomes a negative value from the range of 0 to +1, which is assumed to fluctuate in the range of 0 to 31, or 64 or more. The range has been expanded to correspond to -1 to +2 even when

The arithmetic processing shown in FIG. 6 differs from that in FIG. 4 in the arithmetic processing from the integrator 164 to the frequency dividing circuit 80. Specifically, in the arithmetic processing shown in FIG. 6, an adder 163, adders 165 to 168 are provided, and delay devices 169 and 170 are provided. Additionally, selectors e to h are newly provided. These are divided into a part that is responsible for adjusting the interpolation control code CF shown by block A, and a part that is responsible for adjusting the integer frequency division control code CN shown by block B. Regarding the part indicated by A, the adder 167 and selector g are responsible for the processing required to adjust the interpolation control code CF when carry-down is selected, and the adder 168 and selector h are responsible for the processing necessary for adjusting the interpolation control code CF when carry-down is selected. It is responsible for the processing required to adjust the interpolation control code CF when +1 is selected. Regarding the part indicated by B, the adder 165, the delay device 169, and the selector e are responsible for the processing required to adjust the integer frequency division control code CN when carry-down is selected. 166, delay device 170, and selector f are responsible for the processing required to adjust the integer frequency division control code CN when carry-up +1 is selected. The arithmetic processing from the integrator 164 to the frequency dividing circuit 80 will be specifically described below.

First, a case where the integrated value is a value from 0 to 31 will be explained. The multiplier 164 multiplies the calculation results sequentially output from the adder 161, as in the case shown in FIG. If the integrated value is a value between 0 and 31, none of carry-up, carry-down, or carry-up +1 is selected, and the process of adjusting the integer frequency division control code CN is not performed. That is, 0 is output as the signal SGN from the integrator 164. The signal SGN is then input to block B, which is responsible for adjusting the integer frequency division control code CN. On the other hand, the integrator 164 outputs an integrated value ranging from 0 to 31 to the adder 167. That is, the integrated value is outputted to the adder 167 as the signal SGF from the integrator 164 . The signal SGF is then input to block A, which is responsible for adjusting the interpolation control code CF.

In the block A responsible for adjusting the interpolation control code CF, the adder 167 receives a value of 0 or +32 by the selector g. Selector g selects and outputs +32 when carrying up, and selects and outputs 0 at other times. In this way, the signal SGF output from the integrator 164 and the output of the selector g are input to the adder 167, and the adder 167 performs a process of adding them. If the integrated value is between 0 and 31, carrydown is not selected, so selector g outputs 0. As a result, the adder 167 adds the signal SGF of the integrator 164 and the 0 output by the selector g, and the adder 167 outputs the integrated value of the integrator 164 as it is to the adder 168 as a calculation result. Further, the adder 168 receives a value of either 0 or -32 via the selector h. The selector h is set to 1 when the integrator 164 selects carry-up +1, and 0 when the integrator 164 does not select carry-up +1. is an operation for inputting 0 to the adder 167. In this way, the signal SGF output from the adder 167 and the calculation result of the selector h are input to the adder 168, and the adder 168 performs a process of adding the results. When the integrated value is between 0 and 31, carry-up +1 is not selected, so selector h outputs 0 to adder 168 as the calculation result of h. As a result, the adder 168 adds the signal SGF output from the adder 167 and 0, which is the calculation result of h. In this way, when the integrated value is between 0 and 31, in block A, which is responsible for adjusting the interpolation control code CF, the signal SGF output from the integrator 164 is added or subtracted in the adders 167 and 168. The signal is output as is to the phase interpolation circuit 88 as the interpolation control code CF without being changed.

On the other hand, in block B, which is the part responsible for adjusting the integer frequency division control code CN, first, 0, which is the value of the signal SGN output from the integrator 164, and the calculation result of b are sent to the adder 163. It is input and addition processing is performed. Therefore, the adder 163 outputs the calculation result at b as is. Further, as described above, the adder 165, the delay device 169, and the selector e are responsible for the processing required to adjust the integer frequency division control code CN when carry-down is selected. Similarly to the operation of g, the selector e sets 1 when carry-down is selected and 0 when carry-down is not selected, and outputs +1 to the delay device 169 when it is 1, and outputs +1 to the delay device 169 and 0. In this case, the calculation is such that 0 is output to the delay device 169. When the integrated value is a value between 0 and 31, carry-down is not selected, so 0 is output to the delay device 169 as the calculation result of e. Then, the delay device 169 delays the phase of the signal, which is the result of the calculation of e, by one clock, and the signal is input to the adder 165. Therefore, the adder 165 outputs the calculation result at b as is. The operations of the adder 166, the delay device 170, and the selector f are responsible for the processing required to adjust the integer frequency division control code CN when carry-up +1 is selected. In the calculation of selector f, as in the calculation of h, if carry-up +1 is selected, it is set to 1, if carry-up +1 is not selected, it is set to 0, and if it is 1, +1 is output to delay device 170. , 0, outputs 0 to the delay device 170. When the integrated value is between 0 and 31, carry-up +1 is not selected, and therefore 0 is output to the delay device 170 as the result of the calculation of f. Then, the delay device 170 processes the phase of the signal, which is the calculation result of e, to be delayed by one clock, and the signal is input to the adder 166. Therefore, the adder 165 outputs the calculation result at b as is. In this way, when the integrated value is a value from 0 to 31, in block B, which is the part responsible for adjusting the integer frequency division control code CN, the calculation result in b is directly passed to the frequency divider 84 as the integer frequency division control code CN. is output to.

Next, consider the case where the integrated value is a negative value. First, in the integrator 164, carry-down is selected from among carry-up, carry-down, and carry-up+1 according to the integrated value, as in the case where the integrated value is a value from 0 to 31 described above. That is, -1 is output as the signal SGN output from the integrator 164. The signal SGN is then input to block B, which is responsible for adjusting the integer frequency division control code CN. On the other hand, the integrator 164 inputs the negative integrated value as a signal SGF to the block A responsible for adjusting the interpolation control code CF.

Even if the integrated value is a negative value, processing is performed in block A in the same way as when the integrated value is from 0 to 31, but because carry-down is selected in the arithmetic processing with selector g. 32 is output to the adder 167. Therefore, the negative integrated value that is the signal SGF and 32 that is the calculation result at g are input to the adder 167, and addition processing is performed. As a result, the adder 167 outputs a value obtained by adding 32 to the negative integrated value. Then, the added value and the calculation result of the selector h are inputted to the adder 168. In the arithmetic processing at h, carry-up +1 is not selected, so 0 is output. Therefore, the adder 168 performs a process of adding 0 to the addition result of the adder 167, and outputs the addition result to the phase interpolation circuit 88 as an interpolation control code CF. In this way, when the integrated value in the integrator 164 is a negative value, in block A, 32 is added to the negative integrated value, and as a result, the value between 0 and 31 becomes the interpolation control code. It will be input to the phase interpolation circuit 88 as CF.

Then, in block B, the calculation result in b and -1, which is the signal SGN output from the multiplier 164, are input to the adder 163, and addition processing is performed. That is, the value obtained by subtracting 1 from the calculation result at b is output from the adder 163 and input to the adder 165. Further, the calculation result at e is input to the adder 165 through processing at the delay unit 169. In the arithmetic processing at e, since carry-down is selected, +1 is output as the arithmetic result. Then, the phase of the signal resulting from the calculation is delayed by one clock in the delay device 169, and the signal is input to the adder 165. That is, in the adder 165, 1 is subtracted from the calculation result of b in the signal period in which the integrated value in the integrator 164 becomes a negative value, that is, in the calculation cycle, and the signal is delayed by one period from the signal period. In other words, in the next calculation cycle, 1 is added to the output of the integrator 164 in the next calculation cycle. Thereafter, the output of adder 165 is input to adder 166. Further, the calculation result at f is input to the adder 166 via processing in the delay device 170. In the arithmetic processing at f, carry-up +1 is not selected, so 0 is output as the arithmetic result, the signal is delayed by one clock in the delay device 170, and is input to the adder 166. Therefore, the adder 166 performs a process of adding 0 to the addition result of the adder 165, and outputs the addition result to the frequency divider 84 as an integer frequency division control code CN. In this way, when the integrated value in the integrator 164 is a negative value, in block B, in the calculation cycle in which carry-down is selected, 1 is subtracted from the calculation result in block B. , in the next calculation cycle, 1 is added to the output from the integrator 164 in the next calculation cycle, and the result is input to the frequency divider 84 as an integer frequency division control code CN.

Next, consider the case where the integrated value is in the range of 32 to 63. First, the integrator 164 selects a carry-up corresponding to an integrated value in the range of 32 to 63. That is, the integrator 164 outputs +1 as the signal SGN. The signal is then input to block B, which is responsible for adjusting the integer frequency division control code CN. On the other hand, the integrator 164 subtracts 32, which is a range corresponding to one cycle, from the integrated value and inputs the result to block A, which is responsible for adjusting the interpolation control code CF. That is, in order to subtract 32 from the integrated value of the integrator 164, a value in the range of 0 to 31 is input to block A. First, in the arithmetic processing of selector g, carry-up is selected, so 0 is output to adder 167. Therefore, the adder 167 receives a value in the range of 0 to 31 and 0, which is the calculation result of g, and outputs the value output from the integrator 164 as is as the result of the addition process. Then, the integrated value and the calculation result of the selector h are inputted to the adder 168. In the arithmetic processing at h, carry-up +1 is not selected, so 0 is output. Therefore, the adder 168 performs a process of adding 0 to the addition result of the adder 167, and outputs the addition result to the phase interpolation circuit 88 as an interpolation control code CF. That is, the value obtained by subtracting 32 from the integrated value of the integrator 164 is directly input to the phase interpolation circuit 88.

Then, in block B, the calculation result in b and +1, which is the output of the multiplier 164, are input to the adder 163, and the addition process is performed and the result is input to the adder 165. Further, the calculation result at e is input to the adder 165 through processing at the delay unit 169. In the arithmetic processing at e, carry-down is not selected, so 0 is output as the arithmetic result. Then, the phase of the signal resulting from the calculation is delayed by one clock in the delay device 169, and the signal is input to the adder 165. The result of the addition of the adder 163 and the delay device 169 in the adder 165 is input to the adder 166. Then, the calculation result at f is input to the adder 166 through processing in the delay device 170. In the arithmetic processing at f, carry-up +1 is not selected, so 0 is output as the arithmetic result, the signal is delayed by one clock in the delay device 170, and is input to the adder 166. Therefore, the adder 166 performs a process of adding 0 to the addition result of the adder 165, and outputs the addition result to the frequency divider 84 as an integer frequency division control code CN. In this way, when the integrated value in the integrator 164 is a value in the range of 32 to 63, carry-up is performed, and the value obtained by adding +1 to the calculation result of b is used as the integer frequency division control code CN to the frequency divider 84. is input.

Finally, the case where the integrated value is 64 or more will be explained. First, in the integrator 164, if the integrated value is 64 or more, carry-up +1 is selected. That is, the integrator 164 outputs +2 as the signal SGN. The signal is then input to block B. On the other hand, the integrator 164 inputs a value obtained by subtracting 32 corresponding to carry-up from the integrated value, which is a value of 64 or more, to the block A as a signal SGF. That is, for example, if the integrated value of the integrator 164 is 67, 35, which corresponds to 1 clock out of the carry-up +1 and whose phase is ahead by 2 clocks or more, is subtracted, and the result is 35, which is sent to the adder 167 as the signal SGF. is input.

In block A, carry-down is not selected in the arithmetic processing of selector g, so 0 is output to adder 167. Therefore, when the integrated value of the integrator 164 is 67, 35, which is obtained by subtracting 32 from the integrated value, and 0, which is the calculation result at g, are input to the adder 167, and addition processing is performed. As a result, the adder 167 outputs the 35 input to the block A as is. Then, 35 and the calculation result at h are input to the adder 168. In the arithmetic processing at h, carry-up +1 is selected, so -32 is output. Therefore, the adder 168 performs a process of subtracting 32 from 35, which is the addition result in the adder 167, and outputs the calculation result, 3, to the phase interpolation circuit 88 as the interpolation control code CF. In this way, when the integrated value in the integrator 164 is 64 or more, block A subtracts 32, and as a result, the phase interpolator 88 receives a value between 0 and 31 as the interpolation control code. It will be input as CF.

Then, in block B, the calculation result in b and +2, which is the signal SGN output from the integrator 164, are input to the adder 163, and addition processing is performed. That is, a value obtained by adding 2 to the calculation result at b is output from the adder 163 and input to the adder 165. Further, the calculation result at e is input to the adder 165 via processing at a delay unit 169. In the arithmetic processing at e, carry-down is not selected, so 0 is output as the arithmetic result. Then, the phase of the signal resulting from the calculation is delayed by one clock in the delay device 169, and the signal is input to the adder 165. That is, the adder 165 always outputs the calculation result of the adder 163 as is. Thereafter, the output of adder 165 is input to adder 166. The result of the operation at f is input to the adder 166 through processing in the delay unit 170. In the arithmetic processing at f, carry-up +1 is selected, so -1 is output as the arithmetic result, the signal is delayed by one clock in the delay device 170, and is input to the adder 166. Therefore, the adder 166 performs a process of adding -1 to the addition result of the adder 165, and outputs the addition result to the frequency divider 84 as an integer frequency division control code CN. That is, when the integrated value in the integrator 164 is 64 or more, in block B, in the calculation cycle in which carry-up +1 is selected, 2 is added to the calculation result in block B. will be done. Then, in the next calculation cycle, 1 is subtracted from the signal SGN output from the integrator 164 in the next calculation cycle. In this way, the integer frequency division control code CN for the calculation cycle in which carry-up +1 is selected and the next calculation cycle is set and input to the frequency divider 84.

Here, the significance of the addition processing by adders 167 and 168 in block A and the addition processing by adders 165 and 166 in block B will be explained.

As explained in FIGS. 2 and 3, the interpolated clock signal causes the i-th divided clock signal PCK1 selected by the multiplexer 86 to collide with the i+1-th divided clock signal PCK2 in the phase interpolation circuit 88. It is generated by Specifically, an interpolated clock signal is generated by colliding two signals to create an intermediate waveform. For example, if P0 and P90 collide, the middle, ie, the fourth, interpolated clock signal can be generated. Then, when P0 and the fourth interpolated clock signal collide, an intermediate interpolated clock signal, that is, a second interpolated clock signal is generated. Here, when two signals are collided to generate an interpolated clock signal with an intermediate phase, the phase of the generated interpolated clock signal has a certain error from the intermediate phase of the two original signals. have That is, when the i-th frequency-divided clock signal PCK1 and the i+1-th frequency-divided clock signal PCK2 are repeatedly collided to generate an interpolated clock signal in which the phase difference between the two signals is divided by 8, the phase difference of each interpolated clock signal is Has an error. The more the signals collide, the larger this phase error becomes. The more the signal collisions are repeated in this way, the worse the phase linearity becomes, making it difficult to perform accurate phase comparison of the frequency control circuit 52, leading to deterioration of the jitter performance of the PLL circuit 150.

Therefore, when the integrated value of the integrator 164 is a negative value, carry-down is performed to reduce the integer frequency division control code CN by 1, and instead, processing is performed to add 32 to the interpolation control code CF. To explain using FIG. 6, when the integrated value of the integrator 164 is a negative value, the adder 167 performs a process of adding 32, and outputs it to the phase interpolation circuit 88 as an interpolation control code CF, and the integrator 164 outputs a value subtracted by 1 as a carry-down to the frequency divider 84 as an integer frequency division control code CN. That is, when the interpolation control code CF expands to a negative value, by performing the process of adding 32, the interpolation control code CF can be kept within the range of 0 to 31. Then, by carrying down the integer frequency division control code CN by an amount equal to 32 added to the interpolation control code CF, the balance between the interpolation control code CF and the integer frequency division control code CN is maintained.

Furthermore, if the integrated value of the integrator 164 is 64 or more, carry-up +1 processing is performed to increase the integer frequency division control code CN by 2, and instead, processing is performed to subtract 32 from the interpolation control code CF. conduct. To explain using FIG. 6, when the integrated value of the integrator 164 is 64 or more, the adder 168 subtracts 32 and outputs it to the phase interpolation circuit 88 as an interpolation control code CF. 164 outputs the value obtained by adding 2 as carry-up +1 to the frequency divider 84 as an integer frequency division control code CN. That is, when the interpolation control code CF exceeds 64, which corresponds to two cycles, and becomes a large value, the interpolation control code CF can be reduced to within the range of 0 to 31 by decreasing the interpolation control code CF by 32. Then, the balance between the interpolation control code CF and the integer frequency division control code CN is maintained by performing carry-up +1 processing on the integer frequency division control code CN by an amount equal to 32 subtracted from the interpolation control code CF. In this way, by providing the adders 167 and 168 in block A and controlling the interpolation control code CF input to the phase interpolation circuit 88 so that it falls within the range of 0 to 31, the phase division in the phase interpolation circuit 88 can be performed. can be kept within a certain range. That is, as described above, since the number of collisions between the i-th frequency-divided clock signal PCK1 and the i+1-th frequency-divided clock signal PCK2 can be reduced, the phase difference that occurs when generating a signal with an intermediate phase can be reduced. Errors can be reduced.

On the other hand, the adders 165 and 166 of block B play the role of adding the calculation result of e or f to the signal input from the multiplier 164 with a one-clock delay, as described above. The adders 165 and 166 are provided to perform phase adjustment in the phase interpolation circuit 88. The roles of the adders 165 and 166 and the delay devices 169 and 170 will be specifically explained below using FIGS. 7 to 9.

7 and 8, when the input signal input from the multiphase clock signal generation circuit 82 to the phase interpolation circuit 88 is P0, and the output signal after phase adjustment by the phase interpolation circuit 88 is PI_OUT, FIG. 3 is a diagram illustrating the relationship among an input signal Pin, an output signal PI_OUT, and a reference clock signal RFCK. FIG. 7 is a diagram illustrating how the basic signal waveform changes when phase adjustment is performed in the phase interpolation circuit 88 in this embodiment. In FIG. 7, the symbol N indicates that the input signal output from the multiphase clock signal generation circuit 82 is a signal obtained by dividing the clock signal CK output from the voltage controlled oscillation circuit 74 by N. ing. In FIG. 7, the input signal Pin has a shorter signal period than the reference clock signal RFCK and is out of phase with the reference clock signal RFCK. Therefore, by generating the output signal PI_OUT by delaying the rising timing indicated by i in the waveform of the input signal Pin to the timing indicated by j by the phase interpolation circuit 88, the rising timing k and the rising timing of the reference clock signal RFCK are delayed. Match. The phase change indicated by the dashed arrow in FIG. 7 corresponds to this. In this way, the phase interpolation circuit 88 adjusts the phase so as to reduce the difference between the reference clock signal RFCK and the comparison clock signal FBCK that enter the frequency control circuit 52.

FIGS. 8 and 9 are diagrams illustrating phase adjustment processing when carry-down occurs. In FIGS. 8 and 9, as in FIG. 7, the input signal Pin and the reference clock signal RFCK are originally different in frequency and out of phase. For this reason, processing is performed by the phase interpolation circuit 88 to delay the rise timing of the input signal Pin.

In FIGS. 8 and 9, the period of the input signal Pin becomes shorter in the calculation cycle in which the first process P1 of changing the frequency division number from N to N-1 is performed. As described above, in this case, the interpolation control code CF performs a large phase adjustment to balance the amount. In FIG. 8, the broken line arrow from the rising timing of the input signal Pin indicated by o to the rising timing of the output signal PI_OUT indicated by p corresponds to this. Thereby, the frequency and phase of the output signal PI_OUT and the reference clock signal RFCK can be matched in the calculation cycle in which the carry-down is performed. However, in the next calculation cycle after performing the first process P1, the frequency division number is not incremented by 1 but becomes N, so that the period of the next calculation cycle remains short until the next calculation cycle. In other words, since the calculation cycle following the calculation cycle in which the carry-down was performed starts after the signal with a short frequency division number, the phase must be changed in order to match the rising timing of the reference clock signal RFCK in the next calculation cycle. The amount of adjustment becomes extremely large. This corresponds to the broken line arrow from the rising timing of the input signal Pin indicated by r in FIG. 8 to the rising timing of the output signal PI_OUT indicated by s. If such a large phase adjustment were possible, it would be possible to match the phase with t, the rising timing of the reference clock signal RFCK, but since it is outside the range of the interpolation control code, the phase cannot be adjusted and the output frequency will be shifted.

FIG. 9 is a diagram showing a method for solving the phase adjustment problem described in FIG. 8. In the phase control shown in FIG. 9, the frequency division number is set to N+1 in the calculation cycle following the calculation cycle in which carry-down was performed. As a result of such processing, carry-down occurs, and in the next calculation cycle after the calculation cycle in which the frequency division number is set to N-1, the period of the signal waveform of the input signal Pin becomes longer corresponding to the frequency division number N+1. Become. Therefore, a small amount of adjustment is sufficient to match the phases of the output signal PI_OUT and the reference clock signal RFCK. In this way, a process in which carry-down occurs in the first process P1 and the frequency division number is set to N+1 in the next calculation cycle after the calculation cycle in which the frequency division number is set to N-1 is called a second process P2. By performing the second process P2 after the first process P1 is performed, it is possible to easily adjust the phase in the calculation cycle following the first process P1.

In order to execute such first processing P1 and second processing P2, delay devices 169 and 170 are provided in block B to adjust the integer frequency division control code CN. For example, in the example of FIG. 8, when carry-down occurs, the second process P2 of adding 1 to the integer frequency division control code CN is performed in the next calculation clock. In this process, when carrydown occurs in FIG. It corresponds to that. On the other hand, when carry-up +1 is selected, a fifth process P5 is performed in which 1 is subtracted from the integer frequency division control code CN at the next calculation clock. This fifth process P5 corresponds to the fact that -1 is selected in the calculation indicated by f in FIG. In this way, the phase interpolation circuit 88 is intended only to adjust the phase, and the frequency divider 84 sets the frequency. Therefore, the output of the integer frequency division control code CN performed by the integrator 164 is basically 0 or 1. If -1 or +2 other than this is used, the effect will be ignored in the next calculation cycle. cancel.

Next, the delta-sigma modulator 162 of this embodiment will be explained. FIG. 10 is a circuit diagram showing the configuration of a second-order delta-sigma modulator. The secondary delta-sigma modulator basically has a configuration in which two primary delta-sigma modulators described in FIG. 5 are provided in parallel. That is, the second-order delta-sigma modulator shown in FIG. 10 is composed of a delta-sigma modulator shown by C and a part of the delta-sigma modulator shown by D. Then, the outputs Y1_2 and Y2_3 of each delta-sigma modulator are added by an adder 191 and output as an output Y. The delta-sigma modulator indicated by C is different from the first-order delta-sigma modulator described in FIG. 5 in that a delay device 175 is provided. The output X2 of the delay device 174 of the delta-sigma modulator shown in C is input to the delta-sigma modulator shown in D. A differentiation circuit 183 is provided at a node corresponding to the delay device 175 of the delta-sigma modulator shown in C, so that the output of the quantizer 178 is differentiated and subjected to high-order modulation processing. Note that, as in the case of FIG. 5, Q1 and Q2 are quantization noise of the quantizers LQ1 and LQ2, respectively.

FIG. 11 is a circuit diagram showing the configuration of a third-order delta-sigma modulator. The third-order delta-sigma modulator has a configuration in which delta-sigma modulators indicated by E, F, and G are provided in parallel. Then, the outputs of each delta-sigma modulator are added by adders 190 and 191, and the result is output as an output Y. The delta-sigma modulator shown in FIG. A delay device 182 is provided in front of the . Delay devices 175, 176, and 182 are provided to adjust the phase of the output signal of each delta-sigma modulator arranged in parallel in this manner. The delta-sigma modulator shown in G is configured to receive the output X3 from the delay circuit 181 of the delta-sigma modulator shown in F. The circuit configuration surrounded by the broken line in G is basically the same as the delta-sigma modulator shown in E and F, but the delta-sigma modulator in G has two differentiating circuits, and high-order modulation processing is performed. It is now possible.

Next, the third-order delta-sigma modulator shown in FIG. 11 will be specifically considered using a transfer function. First, the output Y1 of the delta-sigma modulator shown in E is expressed as Y1=X+(1-Z ⁻¹ )Q1. Furthermore, the outputs Y2 and Y3 of the delta sigma modulator shown in F and G are respectively Y2=-Z ^-1 Q1+(1-Z ^-1 )Q2, Y3=-Z ^-1 Q2+(1-Z ^-1 )Q3 , is expressed as Therefore, if the delay devices 175 and 176 of E, the delay device 182 of F, the differential circuit 183, and the differential circuits 188 and 189 of G are not provided, the output Y is outputted by the adders 190 and 191 to Y1, Y2, and It can be found by adding Y3. In this case, the output Y is expressed by equation (1).

However, when each of Y1, Y2, and Y3 is processed by a delay device or a differential circuit as shown in FIG. 11, the output Y is expressed by equation (2).

When the above Y1, Y2, and Y3 are substituted into equation (2), the output Y is expressed as shown in equation (3).

From equation (3), the quantization noise Q1 in the first-stage delta-sigma modulator, denoted by E, and the quantization noise Q2, denoted by F, in the second-stage delta-sigma modulator are canceled, and what remains as the output is G. It is shown that only the quantization noise Q3 of the third-stage delta-sigma modulator shown in FIG. That is, noise shaping is performed to give the quantization noise a third-order high-pass characteristic, and the quantization noise can be suppressed to only the quantization noise Q3 of the third-stage delta-sigma modulator indicated by G.

FIG. 12 is a diagram showing an example of numerical changes at each node in a third-order delta-sigma modulator. The top row shows each node in the third-order delta-sigma modulator and how the values at these nodes change over time. The example shown in FIG. 12 is an example where the input signal to the delta-sigma modulator 162 is 0.3. First, when time is 1, that is, in the initial state when an input signal is input to the delta-sigma modulator 162, X=0.3, and all other nodes are 0. In the initial state, the input signal has not yet propagated to each node, and is zero at nodes other than X. However, as time passes, for example, when time reaches 4, nodes Y2, Y3, Y3_2, and Y3_3 of the higher-order delta-sigma modulation part begin to show a value of 1. Then, when a certain period of time has elapsed, for example, when time becomes 16, the output Y1_3 of the first-stage delta-sigma modulator indicated by E and the output Y2_3 of the second-stage delta-sigma modulator indicated by F become 1. -1, and the output Y of the delta-sigma modulator 162 remains the third-order delta-sigma modulator output Y3_3 indicated by G. That is, if a high-order delta-sigma modulator is used as shown in equation (3), the quantization noise can be suppressed to only the noise in the high frequency band of the third-order delta-sigma modulator shown by G.

Here, we will discuss issues when using a high-order delta-sigma modulator. In the configuration using the high-order delta-sigma modulator 162, it is possible to perform noise shaping to give the quantization noise a high-order high-pass characteristic, as explained in FIGS. By processing in the loop filter circuit 72, it is possible to reduce the quantization noise collected in the high frequency band and generate a low noise signal.

On the other hand, Non-Patent Document 1 states that when a second-order or higher-order delta-sigma modulator is used, the output range of the delta-sigma modulator is expanded compared to a first-order delta-sigma modulator, and as a result, the phase It has been pointed out that the input range to interpolation circuit 88 is expanded. Specifically, when using a high-order delta-sigma modulator, the integrated value output from the integrator may have a negative phase, or two or more periods of phase adjustment may be required. In order to cope with the expansion of the input range to the phase interpolation circuit 88, it is necessary to generate an interpolated clock signal by repeating collisions of more signals. The error will be larger. Therefore, the phase linearity deteriorates, and the jitter performance of the phase interpolation circuit 88 deteriorates. When using a high-order delta-sigma modulator, it is important to solve such problems.

In this regard, the present embodiment eliminates such problems through processing within the control circuit 160, which is the logic control side. That is, by processing the division ratio setting code CDV in the control circuit 160, the input range of the phase interpolation circuit 88 is controlled within the range of 0 to 31, thereby suppressing the phase error of the frequency division clock signal DVCK. This allows the PLL circuit 150 using the phase interpolation circuit 88 to use the high-order delta-sigma modulator 162 without expanding the dynamic range of the phase interpolation circuit 88. In this way, deterioration of phase linearity and deterioration of jitter performance of the phase interpolation circuit 88 is suppressed.

That is, the circuit device 20 includes a frequency control circuit 52 , a voltage controlled oscillation circuit 74 , a multiphase clock signal generation circuit 82 , a phase interpolation circuit 88 , and a control circuit 160 . The frequency control circuit 52 generates a frequency control voltage based on the comparison result between the reference clock signal RFCK and the comparison clock signal FBCK. The voltage controlled oscillation circuit 74 generates a clock signal CK having a frequency corresponding to the frequency control voltage. The multiphase clock signal generation circuit 82 generates a plurality of divided clock signals DVCK which are obtained by dividing the clock signal CK by an integer frequency division ratio based on an integer frequency division control code CN indicating an integer frequency division ratio. A plurality of different divided clock signals DVCK are output. The phase interpolation circuit 88 generates a plurality of interpolated clock signals generated by phase interpolation based on the i-th frequency-divided clock signal and the i+1-th frequency-divided clock signal of the multiple frequency-divided clock signals DVCK, based on the interpolation control code CF. The comparison clock signal FBCK is selected from . The control circuit 160 includes a delta-sigma modulator 162 that performs second-order or higher-order delta-sigma modulation based on the frequency division ratio setting code CDV, and an integrator 164 that integrates the output from the delta-sigma modulator 162. Further, the control circuit 160 outputs an integer frequency division control code CN and an interpolation control code CF based on the integrated value of the integrator 164. Then, when the integrated value is below the lower limit of the range, the control circuit 160 performs a first process P1 of subtracting the integer frequency division ratio by 1 for the integer frequency division control code CN.

In this way, by processing the division ratio setting code CDV in the control circuit 160, the input range of the phase interpolation circuit 88 can be controlled within the range of 0 to 31, and the input range of the phase interpolation circuit 88 can be controlled to a high level without expanding the input range. It becomes possible to use the following delta-sigma modulator 162: Therefore, deterioration of phase linearity and deterioration of jitter performance of the phase interpolation circuit 88 can be suppressed. Further, regarding the quantization noise of the delta-sigma modulator 162, the quantization noise can be collected in a high frequency band using the high-order delta-sigma modulator 162 and attenuated by the loop filter circuit 72. Thereby, a highly accurate circuit device 20 can be realized.

In the present embodiment, the control circuit 160 of the circuit device 20 adds a value corresponding to the range width to the integrated value in the first process P1 and outputs the result as an interpolation control code CF.

In this way, when the integrated value in the integrator 164 is a negative value, the input value of the phase interpolation circuit 88 can be controlled within the range of 0 to 31 by adding a value corresponding to the range width. be able to.

Further, in the present embodiment, the control circuit 160 of the circuit device 20 performs a second process P2 for increasing the integer frequency division ratio by 1 for the integer frequency division control code CN in the next calculation cycle after performing the first process P1. conduct.

In this way, even if the first process P1 that reduces the frequency division number by 1 is performed and the period of the input signal Pin becomes shorter, the second process P2 that increases the frequency division number by 1 in the next calculation cycle is performed, and the cycle of the input signal Pin returns to the cycle before the first process P1. Therefore, it becomes easy to adjust the rising timings of the reference clock signal RFCK and the comparison clock signal FBCK to match in the next calculation cycle after the first processing P1 has been performed.

Further, in this embodiment, when the integrated value exceeds the upper limit of the range, the control circuit 160 of the circuit device 20 performs a third process P3 of increasing the integer frequency division ratio by 1 for the integer frequency division control code CN.

In this way, it becomes possible to increment the integer frequency division control code CN by 1 for integrated values of one cycle or more, and input only the integrated value exceeding the upper limit of the range to the phase interpolation circuit 88.

In the present embodiment, the control circuit 160 of the circuit device 20 subtracts a value corresponding to the range width from the integrated value in the third process P3, and outputs the result as an interpolation control code CF.

In this way, when the integrated value of the integrator 164 exceeds the upper limit of the range, by subtracting the value corresponding to the range width, the input value of the phase interpolation circuit 88 is set in the range of 0 to 31. can be controlled.

Further, in the present embodiment, when the integrated value after the third process P3 exceeds the upper limit of the range, the control circuit 160 of the circuit device 20 controls the integer frequency division control code CN by increasing the integer frequency division ratio by two. Process P4 is performed.

In this way, for integrated values of two cycles or more, it becomes possible to increase the integer frequency division control code CN by 2 and input only the part exceeding the range width of two cycles to the phase interpolation circuit 88.

Further, in the present embodiment, in the fourth process P4, the control circuit 160 of the circuit device 20 subtracts a value corresponding to the range width from the integrated value after the third process P3, and outputs the result as an interpolation control code CF. .

In this way, if the value after subtracting the value corresponding to the range width from the integrated value in the integrator 164 is still above the range upper limit, by subtracting the value corresponding to the range width, , the input value of the phase interpolation circuit 88 can be controlled within the range of 0 to 31.

In the present embodiment, the control circuit 160 of the circuit device 20 performs a fifth process P5 in which the integer frequency division ratio is reduced by 1 for the integer frequency division control code CN in the next calculation cycle after performing the fourth process P4. I do.

In this way, even if the fourth process P4 that increases the frequency division number by +2 is performed and the period of the input signal Pin becomes longer, the fifth process P5 that decreases the frequency division number by 1 is performed in the next calculation cycle. Then, the cycle of the input signal Pin returns to the cycle before the fourth process P4. Therefore, it becomes easy to adjust the rise timings of the reference clock signal RFCK and the comparison clock signal FBCK to match in the next calculation cycle after the fourth process P4 is performed.

Further, in this embodiment, the frequency dividing circuit 80 of the circuit device 20 generates a plurality of frequency-divided clock signals DVCK from the frequency-divided clock signal DVCK obtained by dividing the frequency of the clock signal CK by two.

In this way, based on the divided clock signal DVCK obtained by dividing the clock signal CK by two, the divided clock signals P0, P90, P180, which have a phase shift corresponding to a half wavelength of the period TVCO of the clock signal CK, P270 and P360 can be generated.

Further, in the circuit device 20 of this embodiment, when the integer part of the frequency division ratio setting code CDV is N and the decimal part is f, the integer frequency division ratio indicated by the integer frequency division control code CN is (N.f). It is the quotient of /2.

The frequency FVCO of the clock signal CK output from the voltage controlled oscillation circuit 74 is first divided by two in the frequency divider 83. Therefore, if the quotient of (N.f)/2 is used as the integer frequency division control code CN, it is possible to generate the comparison clock signal FBCK to be compared with the reference clock signal RFCK.

3. Detailed Configuration Example of Circuit Device FIGS. 13, 14, and 16 show detailed configuration examples of the circuit device 20 of this embodiment. The circuit device shown in FIG. 13 is a first configuration example of this embodiment. In the first configuration example, the circuit device 20 includes a phase comparison circuit 51, a charge pump circuit 61, a clock signal generation circuit 70, an output circuit 78, and a frequency division circuit 80. Clock signal generation circuit 70 includes a loop filter circuit 72, a voltage controlled oscillation circuit 74, and a buffer circuit 76. Here, the phase comparison circuit 51, charge pump circuit 61, and loop filter circuit 72 correspond to the frequency control circuit 52 of the circuit device 20 shown in FIG. In the configuration example shown in FIG. 13, a buffer circuit 76 and an output circuit 78 are provided on the output node side of the voltage controlled oscillation circuit 74. Note that the configuration examples shown in FIGS. 13, 14, and 16 include a control circuit 160 like the circuit device shown in FIG. 1, but its description is omitted in the drawings. 13, FIG. 14, and FIG. 16, the voltage controlled oscillation circuit 74 and the frequency dividing circuit 80 have the same configuration as the voltage controlled oscillating circuit 74 and the frequency dividing circuit 80 shown in FIG. 1, respectively.

The phase comparison circuit 51 outputs a phase difference signal PDS based on a phase comparison between the reference clock signal RFCK and the comparison clock signal FBCK. For example, the phase comparison circuit 51 outputs an up signal or a down signal as the phase difference signal PDS based on the phase comparison between the reference clock signal RFCK and the comparison clock signal FBCK. For example, if the comparison clock signal FBCK is behind the reference clock signal RFCK, the phase comparison circuit 51 outputs an up signal, and if the comparison clock signal FBCK is ahead of the reference clock signal RFCK in phase, the phase comparison circuit 51 outputs an up signal. If it is, output a down signal.

The charge pump circuit 61 performs a charge pump operation according to the phase difference signal PDS from the phase comparison circuit 51. For example, when the up signal is input as the phase difference signal PDS, the charge pump circuit 61 charges the up current flowing from the high potential side power supply to the output node of the charge pump circuit 61 during the active period of the up signal. Generate as pump current. Furthermore, when a down signal is input as the phase difference signal PDS, the charge pump circuit 61 directs the down current flowing from the output node of the charge pump circuit 61 to the low potential side power source during the active period of the down signal to the charge pump circuit 61. Generate as electric current.

The clock signal generation circuit 70 generates a clock signal CK whose frequency is controlled based on the output of the charge pump circuit 61. For example, the clock signal generation circuit 70 generates a clock signal CK whose frequency is controlled based on the charge pump current of the charge pump circuit 61. For example, the circuit device 20 performs a synchronous operation in a feedback loop including a phase comparison circuit 51, a charge pump circuit 61, and a clock signal generation circuit 70. The synchronous operation is, for example, an FLL (Frequency Locked Loop) operation. The clock signal generation circuit 70 generates a clock signal CK having a frequency controlled based on the charge pump current of the charge pump circuit 61 during the synchronous operation.

As described above, the frequency dividing circuit 80 has the same configuration as the frequency dividing circuit 80 in the circuit device 20 of FIG. 1, but in the configuration example of FIG. do.

Loop filter circuit 72 generates a control voltage that controls the oscillation frequency of voltage controlled oscillation circuit 74. For example, the loop filter circuit 72 generates a control voltage by integrating and smoothing the charge pump current from the charge pump circuit 61. The loop filter circuit 72 can be realized by, for example, an RC low-pass filter composed of a capacitor and a resistor. The buffer circuit 76 buffers the oscillation signal generated by the voltage controlled oscillation circuit 74 to generate the clock signal CK. For example, when the voltage controlled oscillation circuit 74 generates a differential oscillation signal, the buffer circuit 76 generates and outputs a rectangular wave clock signal CK based on this differential sine wave oscillation signal.

The output circuit 78 buffers the clock signal CK and outputs the output clock signal CKQ to the outside. For example, the output circuit 78 outputs the output clock signal CKQ in a single-ended CMOS signal format. Alternatively, the output circuit 78 may output the output clock signal CKQ in a signal format such as LVDS (Low Voltage Differential Signaling) or PECL (Positive Emitter Coupled Logic).

In this way, in the first configuration example, the clock signal generation circuit 70 includes a loop filter circuit 72 that outputs a control voltage with an oscillation frequency based on the output of the charge pump circuit 61, and a clock signal CK with an oscillation frequency corresponding to the control voltage. It includes a voltage controlled oscillation circuit 74 that generates. In this way, a synchronous operation in a feedback loop including the phase comparator circuit 51, charge pump circuit 61, and clock signal generation circuit 70 becomes possible.

FIG. 14 shows a second configuration example of this embodiment. The second configuration example differs from the first configuration example in the configuration of the feedback loop within the PLL circuit 150. In addition to the feedback loop in the first configuration example, the second configuration example includes a first feedback loop that passes through the slope signal generation circuit 22, the first phase comparison circuit 30, and the first charge pump circuit 40. In the second configuration example, a feedback loop including the second phase comparison circuit 50, the second charge pump circuit 60, and the clock signal generation circuit 70 is referred to as a second feedback loop. Further, in the second configuration example, a second phase comparison circuit 50 and a second charge pump circuit 60 are provided as circuits corresponding to the phase comparison circuit 51 and charge pump circuit 61 of the first configuration example. The output signal of the frequency dividing circuit 80 is input to a pulse width expanding circuit 90.

The slope signal generation circuit 22 generates a slope signal SLP based on a comparison clock signal FBCK of the clock signal CK. The slope signal generation circuit 22 is, for example, a circuit called LSG (Linear Slope Generator). The comparison clock signal FBCK is a clock signal obtained by feeding back the clock signal CK. For example, in FIG. 1, the comparison clock signal FBCK is a clock signal obtained by feeding back the clock signal CK generated by the clock signal generation circuit 70 to the input side via the frequency dividing circuit 80 or the like. The comparison clock signal FBCK is a rectangular wave clock signal, and the slope signal generation circuit 22 generates a slope signal SLP having a linear slope from this rectangular wave comparison clock signal FBCK. Note that the slope signal SLP only needs to have a substantially linear slope. For example, the slope signal generation circuit 22 generates a slope signal SLP by tilting the edges of the rectangular wave comparison clock signal FBCK.

The first phase comparison circuit 30 includes a sampling circuit 32 that samples the slope signal SLP based on the reference clock signal RFCK, and outputs a sampling voltage VSA of the sampling circuit 32. For example, the sampling circuit 32 samples the slope signal SLP at the edge timing of the reference clock signal RFCK. The first phase comparison circuit 30 then outputs the voltage obtained by sampling the slope signal SLP by the sampling circuit 32 as the sampling voltage VSA. The reference clock signal RFCK is a clock signal generated by, for example, vibrating a vibrator as described later.

The pulser circuit 24 outputs a pulse signal PLS based on the reference clock signal RFCK. For example, the pulser circuit 24 outputs a pulse signal PLS having a predetermined pulse width that becomes active every time the reference clock signal RFCK becomes active. For example, the pulser circuit 24 includes a first delay circuit and a second delay circuit. The pulser circuit 24 becomes active at a timing delayed by the first delay time of the first delay circuit from the timing when the reference clock signal RFCK becomes active, and remains active during the second delay time of the second delay circuit. A pulse signal PLS is output. Note that the active level is either high level or low level, and the inactive level is the other of high level or low level.

The first charge pump circuit 40 outputs a current according to the sampling voltage VSA during the active period of the pulse signal PLS. For example, the first charge pump circuit 40 outputs a current that increases as the sampling voltage VSA increases to the clock signal generation circuit 70 as a charge pump current during an active period in which the pulse signal PLS is active. As a result, the clock signal generation circuit 70 outputs a clock signal CK having a frequency corresponding to this charge pump current.

The pulse width expansion circuit 90 expands the pulse width of the frequency-divided clock signal DVCK and outputs it as a comparison clock signal FBCK. For example, when the clock pulse width of the frequency-divided clock signal DVCK is PW1 and the clock pulse width of the comparison clock signal FBCK is PW2, the pulse width expansion circuit 90 expands the pulse width so that PW2>PW1 holds. The comparison clock signal FBCK is output. For example, when the duty ratio of the frequency-divided clock signal DVCK is DTY1 and the duty ratio of the comparison clock signal FBCK is DTY2, the pulse width expansion circuit 90 outputs the comparison clock signal FBCK in which DTY2>DTY1 holds. This comparison clock signal FBCK is then input to the slope signal generation circuit 22 and the like.

The second phase comparison circuit 50 includes a dead zone detection circuit 53 and an enable signal generation circuit 54. The dead zone detection circuit 53 detects whether the phase difference between the reference clock signal RFCK and the comparison clock signal FBCK falls within a dead zone. The phase difference can also be called a phase error. The dead zone is a dead zone, and is, for example, a range in which the phase difference between the reference clock signal RFCK and the comparison clock signal FBCK is equal to or less than a threshold value. The dead zone detection circuit 53 performs such dead zone generation processing and determines whether the phase difference between the reference clock signal RFCK and the comparison clock signal FBCK falls within the dead zone. The dead zone is generated based on the delay time of a delay circuit provided in the dead zone detection circuit 53.

The enable signal generation circuit 54 generates an enable signal ENSP for the pulser circuit 24 and an enable signal ENCP for the second charge pump circuit 60. The enable signal ENSP is, for example, a first enable signal, and is a signal for enabling or disabling the operation of the pulser circuit 24, for example. The enable signal ENCP is, for example, a second enable signal, and is a signal for enabling or disabling the operation of the second charge pump circuit 60, for example. The enable signal generation circuit 54 generates an enable signal ENSP and an enable signal ENCP based on the dead zone detection result. The enable signal generation circuit 54 may generate an inverted signal of the enable signal ENSP as the enable signal ENCP, or may generate the enable signal ENSP and the enable signal ENCP separately.

For example, the enable signal generation circuit 54 generates the enable signal ENSP that becomes active during a dead zone period in which the phase difference between the reference clock signal RFCK and the comparison clock signal FBCK falls within the dead zone. In this way, the enable signal ENSP becomes active during the dead zone period, so that the pulser circuit 24 outputs the pulse signal PLS. This enables SPLL operation, which is the first synchronous operation, in the first feedback loop including the first phase comparison circuit 30, the first charge pump circuit 40, and the clock signal generation circuit 70.

FIG. 15 is a signal waveform diagram illustrating the operation of the circuit device 20 of this embodiment. For example, after the power is turned on, the circuit device 20 performs the FLL operation, which is the second synchronous operation in the second feedback loop. For example, the second charge pump circuit 60 performs a charge pump operation based on the up signal UP and down signal DN output by the second phase comparison circuit 50 based on the phase comparison between the reference clock signal RFCK and the comparison clock signal FBCK. The charge pump current resulting from this charge pump operation is input to the loop filter circuit 72 to generate a control voltage, and the clock signal CK is generated by the oscillation operation of the voltage controlled oscillation circuit 74 based on this control voltage. This clock signal CK is fed back to the second phase comparison circuit 50 as a comparison clock signal FBCK via the frequency dividing circuit 80 and the like. As a result, as shown in A1 of FIG. 3, an FLL operation is performed in which the frequency of the comparison clock signal FBCK approaches the frequency of the reference clock signal RFCK. Note that a frequency dividing ratio setting code for setting the clock signal CK to a target frequency is set in the frequency dividing circuit 80. For example, when the frequency of the clock signal CK is fck, the frequency of the reference clock signal RFCK is frf, and the frequency division ratio is DV, the relationship fck=DV×frf holds true.

Specifically, the dead zone detection circuit 53 detects whether the phase difference between the reference clock signal RFCK and the comparison clock signal FBCK falls within the dead zone, and determines whether or not the phase difference between the reference clock signal RFCK and the comparison clock signal FBCK falls within the dead zone, and detects a non-dead zone period during which the phase difference does not fall within the dead zone. In this case, the second charge pump circuit 60 performs the charge pump operation, thereby performing the FLL operation in the second feedback loop. Note that in A2 and A3 of FIG. 15, the SPLL operation enable signal ENSP is transiently active, but this is because even if the reference clock signal RFCK and the comparison clock signal FBCK have different frequencies, the phase is 360 degrees. This is because if the frequencies are rotating twice, it is determined that the frequencies are the same.

Through such FLL operation, it is detected that the frequency of the comparison clock signal FBCK approaches the frequency of the reference clock signal RFCK and the phase difference enters the dead zone, as shown at A4. During the dead zone period in which the phase difference enters the dead zone, the enable signal ENSP becomes active. As a result, the pulser circuit 24 outputs the pulse signal PLS, and the first charge pump circuit 40 outputs a charge pump current according to the sampling voltage VSA of the sampling circuit 32 of the first phase comparison circuit 30 during the active period of the pulse signal PLS. will now be output. This charge pump current is input to the loop filter circuit 72 to generate a control voltage, and the clock signal CK is generated by the oscillation operation of the voltage controlled oscillation circuit 74 based on this control voltage. As a result, as shown at A5 in FIG. 3, phase synchronization by SPLL is performed to bring the reference clock signal RFCK and comparison clock signal FBCK closer in phase.

In this way, in FIG. 15, the FLL operation is performed by the second feedback loop until the phase difference between the reference clock signal RFCK and the comparison clock signal FBCK enters the dead zone. When it is detected that the phase difference has entered the dead zone, the FLL operation using the second feedback loop is switched to the SPLL operation using the first feedback loop. According to the SPLL operation in the first feedback loop, the gain in the PLL can be increased compared to the FLL operation in the second feedback loop, and the in-band noise of the PLL can be reduced. That is, the gain in the SPLL operation is set by the slope of the slope signal SLP, the transconductance Gm of the amplifier circuit AP, the length of the active period of the pulse signal PLS, and the like. For example, the gain can be set high by increasing the slope of the slope signal SLP, increasing the transconductance Gm, or lengthening the active period of the pulse signal PLS. As a result, even if, for example, the phase difference between the reference clock signal RFCK and the comparison clock signal FBCK increases, the phase difference can be brought closer in a short time due to the high PLL gain, and in-band noise is reduced compared to FLL operation. It becomes possible to reduce the By reducing the in-band noise, the phase noise of the clock signal CK can be reduced, and a clock signal CK with good noise characteristics can be generated.

As described above, according to the present embodiment, the first synchronous operation in the first feedback loop including the first phase comparison circuit 30, the first charge pump circuit 40, and the clock signal generation circuit 70, and the second phase comparison circuit 50 , the second charge pump circuit 60, and the clock signal generation circuit 70, it is possible to realize a PLL circuit that performs a second synchronous operation in a second feedback loop. In this case, in this embodiment, the pulse width expansion circuit 90 expands the pulse width of the divided clock signal DVCK from the frequency division circuit 80 and outputs it as the comparison clock signal FBCK. As a result, even if the frequency-divided clock signal DVCK is a clock signal with a duty ratio smaller than 50%, for example, the comparison clock signal FBCK obtained by expanding the pulse width of the frequency-divided clock signal DVCK can be used by the slope signal generation circuit. 22 can now be entered. Therefore, the slope signal generation circuit 22 generates the slope signal SLP based on the comparison clock signal FBCK whose pulse width has been expanded, and the sampling circuit 32 of the first phase comparison circuit 30 samples the slope signal SLP. The voltage VSA can now be output to the first charge pump circuit 40. As a result, even when the frequency-divided clock signal DVCK is a clock signal with a narrow pulse width, the sampling voltage VSA with voltage fluctuations suppressed is output to the first charge pump circuit 40, and the first charge pump circuit 40 is properly controlled. This makes it possible to realize charge pump operation.

That is, the frequency-divided clock signal DVCK output by the frequency dividing circuit 80 is often a narrow pulse signal with a duty ratio of less than 50%, and depending on the circuit configuration, the frequency-divided clock signal DVCK may become a clock signal with a very small pulse width. . Furthermore, as the oscillation frequency of the voltage controlled oscillation circuit 74 of the clock signal generation circuit 70 increases, the pulse width of the frequency-divided clock signal DVCK becomes even smaller. For example, in the PLL circuit of the circuit device 20 of this embodiment, a clock signal CK of, for example, several GHz is generated based on a reference clock signal RFCK of a frequency of, for example, about 100 to 200 MHz, which is generated using a vibrator or the like. In this case, the pulse width of the divided clock signal DVCK may be several clocks of the clock signal CK depending on the circuit configuration of the frequency dividing circuit 80. For example, the pulse width of the divided clock signal DVCK may be as narrow as several ns. In some cases, the clock signal becomes a pulse-width clock signal. When the slope signal generation circuit 22 generates the slope signal SLP based on the frequency-divided clock signal DVCK having such a narrow pulse width, and the sampling circuit 32 performs a sampling operation of the slope signal SLP, problems such as fluctuations in the sampling voltage VSA occur. occurs. In this case as well, in this embodiment, the pulse width expansion circuit 90 expands the pulse width of the frequency-divided clock signal DVCK from the frequency division circuit 80, and the comparison clock signal FBCK with the expanded pulse width is sent to the slope signal generation circuit. 22, it is possible to prevent the above problems from occurring.

FIG. 16 is a third configuration example of this embodiment. The third configuration example is a circuit device 20 of a subsampling PLL. The third configuration example, which is a subsampling PLL, differs from the second configuration example in the configuration of the feedback loop within the PLL circuit 150. Specifically, the third configuration example has a first feedback loop that passes through the first phase comparison circuit 30 and the first charge pump circuit 40. Further, unlike the configuration of the second configuration example, the oscillation signal VCOS from the voltage controlled oscillation circuit 74 of the clock signal generation circuit 70 is fed back to the first phase comparison circuit 30. Further, the configuration of the first phase comparator circuit 30 is also different from the second configuration example. The third configuration example is not provided with the slope signal generation circuit 22 and the pulse width expansion circuit 90 that are provided in the second configuration example. Note that in the third configuration example, the oscillation signal VCOS of the VCO is input to the first phase comparator circuit 30 via the buffer circuit BUF, but a configuration in which the buffer circuit BUF is not provided is also possible.

In the third configuration example, which is a subsampling PLL, the sine wave oscillation signal VCOS from the voltage controlled oscillation circuit 74, which is a VCO, is input to the first phase comparison circuit 30 as a feedback signal FBSG. A sampling circuit 32 samples the oscillation signal VCOS based on the reference clock signal RFCK. The slope of the sine wave oscillation signal VCOS, for example, at the zero-crossing point serves the same function as the slope of the slope signal SLP in the second configuration example. In this case, in the third configuration example, sampling is performed every M sine wave waveforms of the oscillation signal VCOS. For example, a fractional-N type subsampling PLL can be realized by setting the sampling timing of the oscillation signal VCOS using a time-to-digital converter (DCT) having a delta-sigma modulator.

The third configuration example, which is a subsampling PLL, has the advantage that noise caused by the frequency dividing circuit 80 can be reduced because the frequency dividing circuit 80 is not provided in the first feedback loop. On the other hand, the first phase comparator circuit 30 needs to perform sampling processing on the oscillation signal VCOS having a high frequency of, for example, several GHz, which makes operation and design using a CMOS circuit difficult.

4. Oscillator FIG. 17 shows a first configuration example of the oscillator 4 of this embodiment. The oscillator 4 of this embodiment includes a circuit device 20 of this embodiment and a resonator 10 for generating a reference clock signal RFCK. For example, in FIG. 17, the vibrator 10 is electrically connected to the circuit device 20. For example, the vibrator 10 and the circuit device 20 are electrically connected using internal wiring of a package housing the vibrator 10 and the circuit device 20, bonding wires, metal bumps, or the like.

The vibrator 10 is an element that generates mechanical vibrations based on electrical signals. The vibrator 10 can be realized by, for example, a vibrating piece such as a crystal vibrating piece. For example, the vibrator 10 can be realized by a crystal vibrating piece with a cut angle of AT cut or SC cut that vibrates through thickness shear, a tuning fork type crystal vibrating piece, a twin tuning fork type crystal vibrating piece, or the like. For example, the resonator 10 may be a resonator built into an SPXO (Simple Packaged Crystal Oscillator) oscillator, or a resonator built into a temperature compensated crystal oscillator (TCXO) that does not have a constant temperature oven. The vibrator may be built in a constant temperature oven type crystal oscillator (OCXO) equipped with a constant temperature oven. Note that the vibrator 10 of this embodiment may be realized by various types of vibrating pieces, such as a vibrating piece other than a thickness-shear vibrating type, a tuning fork type, or a double tuning fork type, or a piezoelectric vibrating piece formed of a material other than crystal. It is possible. For example, as the vibrator 10, it is also possible to employ a SAW (Surface Acoustic Wave) resonator, a MEMS (Micro Electro Mechanical Systems) vibrator as a silicon vibrator formed using a silicon substrate, or the like.

The circuit device 20 in FIG. 17 includes an oscillation circuit 130, a PLL circuit 150, a control circuit 160, and an output circuit 180. The oscillation circuit 130 is a circuit that causes the vibrator 10 to oscillate. For example, the oscillation circuit 130 generates an oscillation signal by causing the vibrator 10 to oscillate. For example, the oscillation circuit 130 can be realized by an oscillation drive circuit electrically connected to one end and the other end of the vibrator 10, and passive elements such as a capacitor and a resistor. The drive circuit can be realized by, for example, a CMOS inverter circuit or a bipolar transistor. The drive circuit is a core circuit of the oscillation circuit 130, and causes the vibrator 10 to oscillate by driving the vibrator 10 with voltage or current. As the oscillation circuit 130, various types of oscillation circuits can be used, such as an inverter type, Pierce type, Colpitts type, or Hartley type. Note that the connection in this embodiment is an electrical connection. Electrical connection is a connection that allows transmission of electrical signals, and is a connection that allows transmission of information by electrical signals. The electrical connection may be through a passive element or the like.

The PLL circuit 150 is a PLL circuit realized by each circuit of this embodiment described in FIG. 1 and the like. A clock signal based on an oscillation signal generated by the oscillation circuit 130 that causes the vibrator 10 to oscillate is input to the PLL circuit 150 as a reference clock signal RFCK. Then, the PLL circuit 150 compares the phases of the reference clock signal RFCK based on the oscillation signal of the vibrator 10 and the comparison clock signal FBCK, and generates the clock signal CK by a charge pump operation or the like. Then, when the phase difference between the reference clock signal RFCK and the comparison clock signal FBCK is not within the dead zone, the PLL circuit 150 performs a synchronization operation by the FLL operation of the second feedback loop, and the phase difference between the reference clock signal RFCK and the comparison clock signal FBCK is within the dead zone. In this case, a synchronous operation is performed using the SPLL operation of the first feedback loop.

The control circuit 160 is a logic circuit and performs various control processing and calculation processing. For example, the control circuit 160 controls the entire circuit device 20 and controls the operation sequence of the circuit device 20. Further, the control circuit 160 performs various processes for controlling the oscillation circuit 130. The control circuit 160 can be realized by, for example, an ASIC (Application Specific Integrated Circuit) circuit such as a gate array that is automatically placed and routed.

Control circuit 160 includes a delta-sigma modulator 162 and an integrator 164. For example, when the frequency divider circuit 80 of this embodiment is a phase interpolation type frequency divider circuit, the delta-sigma modulator 162 performs delta-sigma modulation based on the fractional part of the frequency division ratio of the frequency division ratio setting code. , an integrator 164 performs an integration process on the output of the delta-sigma modulator 162. Based on the interpolation control code based on the integration result of the integrator 164, processing for selecting the frequency-divided clock signal DVCK from a plurality of interpolated clock signals is performed. Integer frequency division is performed by the integer frequency divider of the frequency division circuit 80 based on the integer part of the frequency division ratio of the frequency division ratio setting code.

Output circuit 180 buffers clock signal CK from PLL circuit 150 and outputs output clock signal CKQ. This output clock signal CKQ becomes the external output clock signal of the oscillator 4. This output circuit 180 corresponds to output circuit 78 in FIG. Further, the output circuit 180 receives an external output enable signal OE, and outputs an output clock signal CKQ when the output enable signal OE is active. As a result, the output clock signal CKQ is outputted to the outside of the oscillator 4. On the other hand, when the output enable signal OE is inactive, the output terminal of the output clock signal CKQ is set to a fixed voltage such as a low level.

Note that in FIG. 17, a temperature compensation circuit is not provided, and in this case, the oscillator 4 becomes an SPXO oscillator. Specifically, the oscillator 4 is a programmable SPXO that can output an output clock signal CKQ of any frequency according to a division ratio setting code set in the PLL circuit 150. However, in the configuration of FIG. 17, the oscillator 4 of the TCXO may be configured by providing a temperature compensation circuit that performs temperature compensation processing based on the temperature detection result of the temperature sensor. In this case, the oscillation circuit 130 may be provided with a variable capacitance circuit whose capacitance is controlled by the temperature compensation voltage from the temperature compensation circuit.

FIG. 18 shows a second configuration example of the oscillator 4. The oscillator 4 in FIG. 18 includes a vibrator 10, a circuit device 20 that is a first circuit device, and a circuit device 20 of this embodiment that is a second circuit device.

Circuit device 20 includes an oscillation circuit 130, a temperature compensation circuit 140, a temperature sensor 148, a control circuit 160, and an output circuit 180. Note that the configurations of the control circuit 160 and the output circuit 180 are the same as those in FIG. 17, so detailed explanations will be omitted.

Oscillation circuit 130 includes a variable capacitance circuit 132. The variable capacitance circuit 132 is provided at at least one of one end and the other end of the vibrator 10 and is a circuit for adjusting the load capacitance of the vibrator 10. By adjusting the capacitance of the variable capacitance circuit 132, the oscillation frequency of the oscillation circuit 130 is adjusted. The variable capacitance circuit 132 can be realized by, for example, a variable capacitance element such as a varactor. For example, the variable capacitance circuit 132 can be realized by a variable capacitance element whose capacitance is controlled based on a temperature compensation voltage. Alternatively, the variable capacitance circuit 132 may be realized by a capacitor array and a switch array connected to the capacitor array. In this case, the capacitance of the variable capacitance circuit 132 is controlled by turning on or off a plurality of switches included in the switch array using, for example, a digital control signal.

The temperature compensation circuit 140 is a circuit that performs temperature compensation for the oscillation frequency of the oscillation circuit 130. For example, the temperature compensation circuit 140 outputs a temperature compensation signal that temperature-compensates the oscillation frequency of the oscillation circuit 130 based on the temperature detection result of the temperature sensor 148. Temperature compensation is a process of suppressing and compensating for fluctuations in oscillation frequency due to temperature fluctuations, for example. That is, the temperature compensation circuit 140 performs temperature compensation on the oscillation frequency of the oscillation circuit 130 so that the oscillation frequency remains constant even when there is a temperature fluctuation. Specifically, the temperature compensation circuit 140 generates a temperature compensation voltage as a temperature compensation signal. Then, by controlling the capacitance of the variable capacitance circuit 132 using this temperature compensation voltage as a capacitance control voltage, temperature compensation processing of the oscillation frequency is realized. As the temperature compensation circuit 140, for example, a temperature compensation circuit that performs analog temperature compensation using polynomial approximation can be used. For example, when the temperature compensation voltage that compensates for the frequency-temperature characteristics of the vibrator 10 is approximated by a polynomial, the temperature compensation circuit 140 performs analog temperature compensation based on coefficient information of the polynomial. Analog temperature compensation is realized by, for example, addition processing of current signals and voltage signals, which are analog signals.

Temperature sensor 148 is a sensor that detects temperature. Specifically, the temperature sensor 148 outputs a temperature-dependent voltage that changes depending on the temperature of the environment as a temperature detection voltage that is a temperature detection signal. For example, the temperature sensor 148 generates a temperature detection voltage, which is a temperature detection signal, using a circuit element having temperature dependence. Specifically, the temperature sensor 148 outputs a temperature detection voltage whose voltage changes depending on the temperature, for example, by using the temperature dependence of the forward voltage of a PN junction.

In FIG. 18, the temperature compensation circuit 140 performs the first temperature compensation process based on the temperature detection result by the temperature sensor 148. As a result, the first temperature compensation process is performed on the clock signal CK1 generated by oscillating the vibrator 10 by the oscillation circuit 130, and the clock signal CK1 after the first temperature compensation process is output from the circuit device 20. Ru. The clock signal CK1 after the first temperature compensation process is input to the circuit device 20.

Circuit device 20 includes a PLL circuit 250, a control circuit 260, a temperature sensor 248, and an output circuit 280.

The PLL circuit 250 is a PLL circuit realized by each circuit of this embodiment described in FIG. 1 and the like. A clock signal CK1 based on the oscillation signal of the vibrator 10 is input to the PLL circuit 250 from the circuit device 20 as a reference clock signal RFCK. Then, the PLL circuit 250 compares the phases of the reference clock signal RFCK based on the oscillation signal of the vibrator 10 and the comparison clock signal FBCK, and generates the clock signal CK by a charge pump operation or the like. Then, when the phase difference between the reference clock signal RFCK and the comparison clock signal FBCK does not fall within the dead zone, the PLL circuit 250 performs a synchronization operation using the FLL operation of the second feedback loop, so that the phase difference falls within the dead zone. In this case, a synchronous operation is performed using the SPLL operation of the first feedback loop.

The output circuit 280 buffers the clock signal CK from the PLL circuit 250 and outputs the output clock signal CKQ. This output clock signal CKQ becomes the external output clock signal of the oscillator 4.

The control circuit 260 includes a delta-sigma modulator 262 and an arithmetic circuit 263, and the arithmetic circuit 263 includes an integrator 264. The configurations and operations of the delta-sigma modulator 262 and integrator 264 are similar to those of the delta-sigma modulator 162 and integrator 164 in FIG. 17, so detailed explanations will be omitted.

The circuit device 20 also performs a second temperature compensation process. This second temperature compensation process is performed, for example, by the arithmetic circuit 263 of the control circuit 260. That is, the circuit device 20 performs the second temperature compensation process on the clock signal CK1 after the first compensation process performed by the circuit device 20. For example, the circuit device 20 performs the second temperature compensation process based on the temperature detection result of the temperature sensor 248 or the like. Specifically, the arithmetic circuit 263 of the circuit device 20 performs the second temperature compensation process by neural network calculation or the like based on the temperature detection results from the temperature sensor 248 or the temperature sensor 148 and information on the learned model. For example, a storage circuit (not shown) stores information about a trained model that has been subjected to machine learning so that a temperature compensation value corresponding to the temperature measurement result can be obtained. The arithmetic circuit 263 performs a second temperature compensation process to obtain a temperature compensation value corresponding to each temperature based on the temperature detection result and the learned model information in the storage circuit.

As described above, in FIG. 18, the circuit device 20 performs the first temperature compensation process and outputs the clock signal CK1 to the circuit device 20, and the circuit device 20 performs the second temperature compensation process and outputs the output clock signal CKQ. As a result, the output clock signal CKQ, which has been subjected to the first temperature compensation process by the circuit device 20 and the second temperature compensation process by the circuit device 20, is output from the oscillator 4. By doing so, the oscillator 4 can output an output clock signal CKQ with reduced phase noise and the like while realizing more accurate temperature compensation processing. Note that the circuit device 20 may be provided with a heater control circuit that controls the temperature of the thermostatic oven to realize the OCXO oscillator 4.

As described above, the circuit device of this embodiment includes a frequency control circuit, a voltage controlled oscillation circuit, a multiphase clock signal generation circuit, a phase interpolation circuit, and a control circuit. The frequency control circuit generates a frequency control voltage based on a comparison result between the reference clock signal and the comparison clock signal. The voltage controlled oscillation circuit generates a clock signal with a frequency corresponding to the frequency control voltage. A multiphase clock signal generation circuit generates multiple divided clock signals that are obtained by dividing a clock signal by an integer frequency division ratio based on an integer frequency division control code that indicates an integer frequency division ratio, and that has multiple divided clock signals with different phases. Outputs a frequency clock signal. The phase interpolation circuit generates a signal for comparison from a plurality of interpolated clock signals generated by phase interpolation based on an i-th divided clock signal and an i+1-th divided clock signal of the plurality of divided clock signals, based on an interpolation control code. Select a clock signal. The control circuit includes a delta-sigma modulator that performs second-order or higher-order delta-sigma modulation based on a frequency division ratio setting code, and an integrator that integrates the output from the delta-sigma modulator. The control circuit also outputs an integer frequency division control code and an interpolation control code based on the integrated value of the integrator. The control circuit is related to a circuit device that performs a first process P1 of subtracting the integer frequency division ratio by 1 for the integer frequency division control code when the integrated value is below the lower limit of the range.

According to this embodiment, by processing the division ratio setting code in the control circuit, the input range of the phase interpolation circuit can be controlled within a range corresponding to one cycle, and the input range of the phase interpolation circuit can be controlled to a high level without expanding the input range of the phase interpolation circuit. It becomes possible to use the following delta-sigma modulators: Therefore, deterioration of phase linearity and deterioration of jitter performance of the phase interpolation circuit can be suppressed. Furthermore, regarding the quantization noise of the delta-sigma modulator, it is possible to collect the quantization noise in a high frequency band using a high-order delta-sigma modulator and attenuate it using a loop filter circuit. Thereby, a highly accurate circuit device can be realized.

In the circuit device of this embodiment, the control circuit can also add a value corresponding to the width of the range to the integrated value in the first process and output the result as an interpolation control code.

In this way, when the integrated value in the integrator is a negative value, by adding the value corresponding to the range width, the input value of the phase interpolator can be brought within the range corresponding to one cycle. can be controlled.

In the present embodiment, the control circuit of the circuit device can also perform a second process of increasing the integer frequency division ratio by 1 on the integer frequency division control code in the next calculation cycle after performing the first process.

In this way, even if the first process of decreasing the frequency division number by 1 is performed and the period of the input signal becomes shorter, the second process of increasing the frequency division number by 1 is performed in the next calculation cycle, and the input signal is The period of the signal returns to the period before the first processing. Therefore, it becomes easy to adjust the rise timings of the reference clock signal and the comparison clock signal to match in the calculation cycle following the first processing.

In the present embodiment, the control circuit of the circuit device can also perform a third process of increasing the integer frequency division ratio by 1 for the integer frequency division control code when the integrated value exceeds the upper limit of the range.

In this way, it becomes possible to increment the integer frequency division control code by 1 for integrated values corresponding to one period or more, and input the amount exceeding the upper limit of the range to the phase interpolation circuit.

In the present embodiment, the control circuit of the circuit device can also subtract a value corresponding to the range width from the integrated value in the third process and output the result as an interpolation control code.

In this way, when the integrated value in the integrator exceeds the upper limit of the range, by subtracting the value corresponding to the range width, the input value of the phase interpolation circuit 88 is adjusted to the range corresponding to one cycle. Can be controlled within a range.

Further, in this embodiment, the control circuit of the circuit device performs a fourth process of increasing the integer frequency division ratio by 2 on the integer frequency division control code when the integrated value after the third process exceeds the upper limit of the range. You can also do it.

In this way, it becomes possible to increment the integer frequency division control code by 2 for integrated values corresponding to two cycles or more, and input the part exceeding the range width corresponding to two cycles to the phase interpolation circuit. .

In the present embodiment, the control circuit of the circuit device can also subtract a value corresponding to the range width from the integrated value after the third process in the fourth process, and output the result as an interpolation control code.

In this way, if the value after subtracting the value corresponding to the range width from the integrated value in the integrator is still a value that exceeds the range upper limit, by subtracting the value corresponding to the range width, The input value of the phase interpolation circuit 88 can be controlled within a range corresponding to one cycle.

Furthermore, in the present embodiment, the control circuit of the circuit device may perform a fifth process of reducing the integer frequency division ratio by 1 on the integer frequency division control code in the next calculation cycle after performing the fourth process. .

In this way, even if the fourth process of increasing the frequency division number by 2 is performed and the period of the input signal Pin becomes longer, the fifth process of decreasing the frequency division number by 1 is performed in the next calculation cycle, The cycle of the input signal Pin returns to the cycle before the fourth process. Therefore, it becomes easy to adjust the rise timings of the reference clock signal and the comparison clock signal to match in the next calculation cycle after the fourth process is performed.

Further, in this embodiment, the frequency dividing circuit of the circuit device generates a plurality of frequency-divided clock signals from a frequency-divided clock signal obtained by dividing the clock signal by two.

In this way, a frequency-divided clock signal having a phase shift corresponding to a half wavelength of the period of the clock signal CK can be generated based on a frequency-divided clock signal obtained by dividing the clock signal by two.

Further, in this embodiment, in the circuit device, when the integer part of the frequency division ratio setting code is N and the decimal part is f, the integer frequency division ratio indicated by the integer frequency division control code is (N.f)/2. is the quotient of

In this way, it is possible to generate a comparison clock signal corresponding to the clock signal whose frequency has been divided by two in the frequency divider.

Further, the oscillator of this embodiment includes the circuit device described above and a vibrator for generating a reference clock signal.

Although the present embodiment has been described in detail as above, those skilled in the art will easily understand that many modifications can be made without substantially departing from the novelty and effects of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, a term that appears at least once in the specification or drawings together with a different term with a broader or synonymous meaning may be replaced by that different term anywhere in the specification or drawings. Furthermore, all combinations of this embodiment and modifications are also included within the scope of the present disclosure. Further, the configuration and operation of the circuit device and the oscillator are not limited to those described in this embodiment, and various modifications are possible.

4... Oscillator, 10... Vibrator, 20... Circuit device, 22... Slope signal generation circuit, 24... Pulser circuit, 30... First phase comparison circuit, 32... Sampling circuit, 40... First charge pump circuit, 50... 2-phase comparison circuit, 51... Phase comparison circuit, 52... Frequency control circuit, 53... Dead zone detection circuit, 54... Enable signal generation circuit, 60... Second charge pump circuit, 61... Charge pump circuit, 70... Clock signal generation Circuit, 72... Loop filter circuit, 74... Voltage controlled oscillation circuit, 76... Buffer circuit, 78... Output circuit, 80... Frequency divider circuit, 82... Multiphase clock signal generation circuit, 83... Frequency divider, 84... Frequency divider 86... multiplexer, 87... interpolation circuit, 88... phase interpolation circuit, 90... pulse width expansion circuit, 130... oscillation circuit, 132... variable capacitance circuit, 140... temperature compensation circuit, 148... temperature sensor, 150... PLL Circuit, 160...Control circuit, 161...Adder, 162...Delta sigma modulator, 163...Adder, 164...Integrator, 165...Adder, 166...Adder, 167...Adder, 168...Adder, 169 ...Delay device, 170...Delay device, 171...Adder, 172...Quantizer, 173...Adder, 174...Delay device, 175...Delay device, 176...Delay device, 178...Quantizer, 180...Output circuit , 181... Delay circuit, 182... Delay device, 183... Differential circuit, 188... Differential circuit, 189... Differential circuit, 190... Adder, 191... Adder, 248... Temperature sensor, 250... PLL circuit, 260... Control circuit , 262...Delta-sigma modulator, 263...Arithmetic circuit, 264...Integrator, 280...Output circuit, AP...Amplifier circuit, BUF...Buffer circuit, CDV...Division ratio setting code, CF...Interpolation control code, CK...Clock Signal, CK1...clock signal, CKQ...output clock signal, CN...integer frequency division control code, DN...down signal, DVCK...frequency division clock signal, ENCP...enable signal, ENSP...enable signal, FBCK...comparison clock signal, FBSG...feedback signal, FF...flip-flop circuit, FVCO...frequency, Gm...transconductance, OE...output enable signal, P0...divided clock signal, P1...first processing, P180...divided clock signal, P2...second Processing, P270...divided clock signal, P3...third process, P360...divided clock signal, P4...fourth process, P5...fifth process, P90...divided clock signal, PCK1...divided clock signal, PCK2... Divided clock signal, PDS...phase difference signal, PI_OUT...output signal, PLS...pulse signal, Pin...input signal, Q1 to Q3...quantization noise, RFCK...reference clock signal, SGF...signal, SGN...signal, SLP... Slope signal, TVCO...cycle, UP...up signal, VCOS...oscillation signal, VSA...sampling voltage, XCK...clock signal, e...selector, f...selector, g...selector, h...selector

Claims (11)

a frequency control circuit that generates a frequency control voltage based on a comparison result between a reference clock signal and a comparison clock signal;
a voltage controlled oscillator circuit that generates a clock signal with a frequency corresponding to the frequency control voltage;
Based on an integer frequency division control code indicating an integer frequency division ratio, output a plurality of frequency divided clock signals obtained by dividing the clock signal by the integer frequency division ratio, the plurality of frequency divided clock signals having different phases. a multiphase clock signal generation circuit,
Based on the interpolation control code, the comparison clock signal is obtained from a plurality of interpolated clock signals generated by phase interpolation based on the i-th divided clock signal and the i+1th divided clock signal of the plurality of divided clock signals. The phase interpolation circuit to select,
a delta-sigma modulator that performs second-order or higher-order delta-sigma modulation based on a frequency division ratio setting code; and an integrator that integrates the output from the delta-sigma modulator; a control circuit that outputs the interpolation control code based on the integrated value;
including;
The control circuit includes:
A circuit device characterized in that, when the integrated value is below a lower limit of a range, a first process is performed on the integer frequency division control code to reduce the integer frequency division ratio by 1. The circuit device according to claim 1,
The control circuit includes:
A circuit device characterized in that, in the first process, a value corresponding to the width of the range is added to the integrated value and output as the interpolation control code. The circuit device according to claim 1,
The control circuit includes:
A circuit device characterized in that, in a calculation cycle subsequent to performing the first processing, a second processing is performed on the integer frequency division control code to increase the integer frequency division ratio by +1. The circuit device according to any one of claims 1 to 3,
The control circuit includes:
A circuit device characterized in that, when the integrated value exceeds the upper limit of the range, a third process of increasing the integer frequency division ratio by 1 is performed on the integer frequency division control code. The circuit device according to claim 4,
The control circuit includes:
A circuit device characterized in that, in the third process, a value corresponding to the width of the range is subtracted from the integrated value and output as the interpolation control code. The circuit device according to claim 4,
The control circuit includes:
A circuit device characterized in that, when the integrated value after the third processing exceeds the upper limit of the range, a fourth processing is performed on the integer frequency division control code to increase the integer frequency division ratio by +2. The circuit device according to claim 6,
The control circuit includes:
In the fourth process, a value corresponding to the width of the range is subtracted from the integrated value after the third process, and the result is output as the interpolation control code. The circuit device according to claim 6,
The control circuit includes:
A circuit device characterized in that, in the arithmetic cycle following the execution of the fourth process, a fifth process of subtracting the integer frequency division ratio by 1 is performed on the integer frequency division control code. The circuit device according to any one of claims 1 to 3,
The frequency dividing circuit is
A circuit device characterized in that the plurality of frequency-divided clock signals are generated from a frequency-divided clock signal obtained by dividing the frequency of the clock signal by two. The circuit device according to any one of claims 1 to 3,
When the integer part of the frequency division ratio setting code is N and the decimal part is f,
A circuit device characterized in that the integer frequency division ratio indicated by the integer frequency division control code is a quotient of (N.f)/2. The circuit device according to any one of claims 1 to 3,
a vibrator for generating the reference clock signal;
An oscillator comprising:

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