JP5853034B2 - High linearity phase frequency detector - Google Patents

Description

  The present invention relates generally to the field of phase-locked loops, and in particular to the field of fractional-N phase-locked loop frequency synthesizers.

  Current phase-locked loop (PLL) circuits can include a function for comparing the phase of an output signal from a voltage-controlled oscillator (VCO) with the phase of an input reference frequency to the PLL. Such a circuit can include a phase frequency detector for generating an error signal that represents the proportionality of the phase difference between the output signal and the input reference frequency. In addition, current PLL circuits can also include a function for supplying an error signal to the low pass filter and then to the VCO so that the generated output signal is synchronized with the input reference frequency to the PLL. Current PLL circuits provide a negative feedback loop method that allows an error signal to be generated by feeding back the output from the VCO to the input of the phase frequency detector and coupling the output signal from the VCO to the input reference frequency. Can be used. Some current PLL circuits can provide an output signal to a divider circuit, thus producing an integer multiple of the input reference frequency. When the phase locked state is reached, the output signal from the VCO is equal to N times the input reference frequency, where N is the divider ratio of the divider circuit. Therefore, the current PLL circuit generates a frequency that is an integer multiple of the input reference frequency.

  Those frequency synthesizers can only generate an integer multiple of the input reference frequency. To circumvent such constraints, the frequency synthesizer can further include a ΣΔ modulator to modulate the division value per frequency cycle to obtain a fractional value. Such a frequency synthesizer is called a fractional N frequency synthesizer. The fractional N frequency synthesizer has the frequency

Can be generated, where INT, FRAC, and MOD are integers, and thus F _VCO is not necessarily an integer multiple of the _reference frequency F _reference . The existing ΣΔ modulation can continuously generate a time difference at the input of the phase frequency detector, and this time difference is in turn converted to a charge amount by a charge pump. The ΣΔ modulator shapes the fractional N modulation power to a high frequency, thereby moving the extra noise that gets worse outside the loop filter bandwidth of the feedback loop and removing the extra noise. The conversion from the time difference at the phase frequency detector input to the amount of charge in the loop filter can be performed in a highly linear manner, so that the noise shaping spectral characteristics resulting from using the ΣΔ modulator will cause some noise. As a result, no changes are introduced to the PLL loop. By preventing such noise from being introduced into the PLL loop, the phase noise performance resulting from using fractional N modulation implemented with a divider and ΣΔ modulator is maintained. In other words, various types of ΣΔ modulator noise shaping techniques can be known for this purpose, in order to prevent deterioration of the phase noise spectral characteristics, especially in fractional N PLL synthesizers. However, there is no known highly linear conversion method for converting the phase difference detected by the phase frequency detector into the charge amount in the loop filter connected to the VCO.

  Accordingly, the present invention introduces a novel linearization system and method that substantially eliminates one or more problems due to the limitations and disadvantages of the related art, and a fractional N frequency in a phase locked loop circuit. The present invention relates to a system and method for implementing a synthesizer.

In one embodiment, the present invention provides a phase frequency detector circuit that is applied to a phase-locked loop (PLL) circuit to provide a charge pump and a VCO for providing a VCO output signal. (Voltage-controlled oscillator), an N divider for providing an N divided output signal having an input for receiving a VCO output signal, and for modulating the N divided output signal A first input for receiving a signal oscillating at a reference frequency and a second input for receiving an N-divided output signal having a modulator, a reference frequency supplier, and a loop filter And an Up signal output and a Down signal output. The VCO is in series with the charge pump and loop filter, followed by an N divider, the VCO is configured to receive the regulated voltage signal from the loop filter, and the configuration of the Up and Down signals is Can be a feature. In the phase frequency detector circuit, the Up signal always rises when the second input rises, the Up signal output always falls when the second input falls, and the Down signal Down signal output when the second input is increased to rise, with a mode in which the Down signal output when the first input is increased is lowered.

  In yet another embodiment, the present invention provides a phase frequency detector circuit, the phase frequency detector circuit having a VCO with a positive coefficient between the control voltage of the VCO and the frequency of the VCO output signal. It is applied to a lock loop circuit and includes an Up signal that drives the Up source of the charge pump and a Down signal that drives the Down source of the charge pump. The configuration of the Up signal and the Down signal can be implemented as described above.

  In yet another embodiment, the present invention provides a phase frequency detector circuit, the phase frequency detector circuit having a VCO with a negative coefficient between the control voltage of the VCO and the frequency of the VCO output signal. This is applied to a lock loop circuit, and includes an Up signal for driving the Down source of the charge pump and a Down signal for driving the Up source of the charge pump. The configuration of the Up signal and the Down signal can be implemented as described above.

  In yet another embodiment, the present invention provides a phase frequency detector circuit, the phase frequency detector circuit including two PLL circuits that change between them over time for a fast lockup and toward a lockup state. The Up signal is applied to the PLL circuit associated with the above modes, so that the configuration described above is realized only in the final mode when the PLL is near or within the lockup state. And a changeable configuration of the Down signal. In the preceding mode, when the PLL is near the lock-up state or not in the lock-up state, the configuration of the Up signal and the Down signal is different.

  In a further embodiment, the present invention provides a method implemented using a phase locked loop circuit, the method comprising providing a VCO output signal by a VCO (Voltage-Controlled Oscillator), Receiving at an N divider, the N divider providing an N divided output signal; modulating the N divided output signal; Receiving at an input, the signal oscillating at a reference frequency, receiving an N-divided output signal at a second input, and a first input at the phase frequency detector and the charge pump. Comparing the phase of the second input and the phase of the second input. In the phase frequency detector, the Up signal rises when the second input rises, the Up signal falls when the second input falls, and the Down signal rises when the second input rises. It can be characterized by a particular linearity system having a configuration of Up and Down signals in which the Down signal falls when the first input rises. The VCO can be in series with a loop filter and an N divider, and the VCO receives a regulated voltage signal from the loop filter.

  In yet another embodiment, the present invention provides a method implemented using a phase-locked loop circuit associated with more than one mode, wherein the method described above is in a final mode, Providing a changeable configuration of the Up and Down signals so that the PLL is locked in the preceding mode so that it is realized only when the PLL is sufficiently close or within the lockup state. When not close to up, the configuration of the Up and Down signals may be different.

  In a further embodiment, the present invention provides a phase frequency detector that receives a first input for receiving a signal oscillating at a reference frequency and an output signal divided by N. A first flip-flop for receiving at a first flip-flop trigger input a second input for performing an N-divided output signal, the first flip-flop including a reset input and a first flip-flop output A first flip-flop and a second flip-flop for receiving a signal oscillating at a reference frequency at a second flip-flop trigger input, the second flip-flop including a reset input and a second flip-flop output A NAND logic gate for receiving the first flip-flop output and the second flip-flop output; AND logic gate for receiving the output of the NAND logic gate and an inverter logic gate for receiving the output of the NAND logic gate, the output of the inverter logic gate being the reset of the first flip-flop A second input for receiving an N-divided output signal comprising the Up signal output of the phase frequency detector, including an inverter logic gate connected to the input and a reset input of the second flip-flop. The output of the AND logic gate comprises the Down signal output of the phase frequency detector.

  In a further embodiment, the present invention provides a phase frequency detector that receives a first input for receiving a signal oscillating at a reference frequency and an output signal divided by N. A first flip-flop for receiving at a first flip-flop trigger input a second input for performing an N-divided output signal, the first flip-flop including a reset input and a first flip-flop output A first flip-flop and a second flip-flop for receiving at its second flip-flop trigger input a signal oscillating at a reference frequency, the second flip-flop including a reset input and a second flip-flop output A NAND logic gate for receiving the first flip-flop output and the second flip-flop output; A first AND logic gate for receiving the flip-flop output and the frequency mode enable signal, a second AND logic gate for receiving the first flip-flop output and the NAND logic gate output, and a NAND logic gate An inverter logic gate, the output of the inverter logic gate being connected to the reset input of the first flip-flop and the reset input of the second flip-flop; An AND logic gate and an OR logic gate for receiving the N divided output signal, wherein the OR logic gate output includes a phase frequency detector Up signal output, the second AND logic gate of the second AND logic gate The output comprises the Down signal output of the phase frequency detector. The frequency mode enable signal can be used for a two-mode or multi-mode PLL.

  In a further embodiment, the present invention provides a method implemented using a phase frequency detector, the method receiving a signal oscillating at a reference frequency at a first input; Receiving the output signal at the second input and receiving the output signal divided by N at the first flip-flop trigger input of the first flip-flop, wherein the first flip-flop Receiving a signal oscillating at a reference frequency at a second flip-flop trigger input of a second flip-flop, the reset including a reset input and a first flip-flop output, wherein the second flip-flop is reset A step including an input and a second flip-flop output; and a first flip-flop output and Receiving the flip-flop output of 2 at the NAND logic gate, receiving the output of the first flip-flop output and the NAND logic gate at the AND logic gate, and receiving the output of the NAND logic gate at the inverter logic gate. An output of the inverter logic gate is connected to the reset input of the first flip-flop and the reset input of the second flip-flop, and receiving the output signal divided by N The second input of the second input comprises the Up signal output of the phase frequency detector and the output of the second AND logic gate comprises the Down signal output of the phase frequency detector.

  It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed invention.

The accompanying drawings are included to provide a further understanding of the invention, are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description, It serves to explain the principle of the invention.
FIG. 2 illustrates an exemplary embodiment of a phase-locked loop (PLL) circuit with a fractional N frequency synthesizer. 1 is a diagram illustrating an exemplary embodiment of a phase frequency detector of the present invention applied to a PLL circuit connected in series with a fractional N sigma delta (ΣΔ) modulator (only the phase frequency detector is in detail). It is shown). FIG. 4 exemplarily shows a signal diagram associated with fractional N modulation, including “Down” and “Up” outputs of a phase frequency detector according to the present invention (when in phase mode). FIG. 3 illustrates an exemplary embodiment of an equivalent description for the phase frequency detector of the present invention shown in FIG. 2, where the “frequency mode enable” shown in FIG. 2 is always low (ie, Similarly, an exemplary embodiment of a phase frequency detector is for a “single mode” PLL (only the phase frequency detector is shown in detail). FIG. 2 illustrates an exemplary embodiment of a conventional phase frequency detector and charge pump of a PLL circuit connected in series with a fractional N sigma delta (ΣΔ) modulator (both phase frequency detector and charge pump are Details are shown). FIG. 6 is a diagram illustrating Up signal values and Down signal values of the phase frequency detector of the present invention in relation to a reference clock and a divided VCO clock supplied to the phase frequency detector. FIG. 6 illustrates exemplary method steps for a phase frequency detector of the present invention (for a single mode PLL). FIG. 6 illustrates exemplary method steps for a phase frequency detector of the present invention (for dual or multimode PLLs). FIG. 4 illustrates example method steps for a conventional phase-locked loop circuit having a fractional-N modulator.

  Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous non-limiting but specific details are set forth to assist in understanding the invention presented herein. However, it will be apparent to those skilled in the art that various alternatives may be used without departing from the scope of the invention and that the invention may be practiced without these specific details. For example, it will be apparent to those skilled in the art that the present invention presented herein can be implemented in any type of phase-locked loop (PLL) circuit.

  FIG. 1 illustrates an exemplary embodiment 100 of a PLL circuit having a fractional N frequency synthesizer. In the exemplary embodiment 100, the reference clock signal 101 can be input to the phase frequency detector and charge pump 102 along with the output signal 108 from the N divider 107. The phase frequency detector and charge pump 102 can detect the phase difference between the reference clock signal 101 and the output signal 108. The output signal 103 from the phase frequency detector and charge pump 102 can be equal to the current pulse proportional to the input phase difference, and the output signal 103 is a frequency provided in a VCO (Voltage-Controlled Oscillator) 105. Can be integrated in the loop filter 104 to generate the regulated voltage needed to obtain. The loop filter 104 is generally a passive circuit that can include standard integrators, pole zeros, and post filters. The post filter may be a RLC (resistor-inductor-capacitor), an RC (resistor-capacitor), or an LC (inductor-capacitor). The loop filter 104 can improve the spectral purity of the VCO output signal 109 by filtering the current pulse of the charge pump 102.

  The first output signal 109 from the VCO 105 can be used, for example, as an input to a device connected to the VCO 105, where the device oscillates at a specific signal that is controlled by a regulated voltage input to the VCO 105. Receive. The second output signal 106 from the VCO 105 can be used to generate a negative feedback loop circuit that passes through the N divider 107 and is used as an input to the phase frequency detector and charge pump 102. The N divider 107 can divide the second output signal 106 by N times, where N is a division ratio corresponding to the N times the frequency of the reference clock signal 101. The output signal 108 from the N divider 107 can be used as a clock input to the ΣΔ modulator 110. The output of the ΣΔ modulator 110 can be input to an adder 111 that adds the output of the ΣΔ modulator 110 to the value of N. The output of the adder 111 can be input to the N frequency divider 107. Using the exemplary embodiment described above, the value of the division cycle associated with the divider circuit (comprising N divider 107, ΣΔ modulator 110, and adder 111) is modulated to obtain a fraction. Fractional N modulation can be implemented. Modulated signals that are at non-DC frequencies and that use fractional-N modulation may not exhibit power that can degrade the phase noise performance of the frequency synthesizer. Specifically, the ΣΔ modulator 110 can shape such power to a higher frequency, thereby moving the extra noise that gets worse outside the bandwidth of the loop filter 104 in the feedback loop. Let the excess noise be removed. The time difference can be generated using the ΣΔ modulator 110 and can be converted to an amount of charge by the phase frequency detector and associated charge pump 102. Because the transformation can be performed in a highly linear manner, the noise shaping spectral characteristics resulting from using the ΣΔ modulator 110 are not changed such that some noise is introduced into the PLL loop as a result. . By preventing such noise from being introduced into the PLL loop, the phase noise performance resulting from using fractional N modulation implemented using N divider 107 and ΣΔ modulator 110 is maintained. The

When the N divider 107, the ΣΔ modulator 110, and the adder 111 are used as the fractional N frequency synthesizer, the frequency of the fractional N frequency synthesizer is
F _VCO = F _Reference x (INT + FRAC / MOD)
A signal that takes the form

In the above equation, F _VCO does not necessarily have to be an integral multiple of the reference clock signal 101 represented by the variable F _Reference . Variables represented by INT, FRAC, and MOD can be integers.

  It should be noted here that in order to prevent deterioration of the phase noise spectral characteristics in a fractional N PLL synthesizer, in addition to the ΣΔ modulator noise shaping technique, various types are well known for this purpose. A highly linear conversion method from the phase difference detected in the frequency detector to the charge amount in the loop filter connected to the VCO is very important.

  FIG. 2 illustrates an exemplary embodiment 200 of a phase frequency detector 202 of a PLL circuit connected in series with a fractional N modulator. In the exemplary embodiment 200, individual elements of the phase frequency detector 202 are shown (individual charge pump elements are not shown). Specifically, phase frequency detector 202 includes an input of reference clock signal 201 and an input of a divided VCO clock signal 208. The input of the divided VCO clock signal 208 can be the output of a fractional N frequency synthesizer. The input of the divided VCO clock signal 208 can be connected to the trigger input of the first flip-flop 210 (ie, Down R1 flip-flop (FF)). The input of the divided VCO clock signal 208 can also be connected to the input of the OR logic gate 214. The first flip-flop 210 can include a reset-down input and an output of the first flip-flop 210. The input of the reference clock signal 201 can be connected to the trigger input of the second flip-flop 211 (ie, Up R1 FF). The second flip-flop 211 can include a re-setup input and a second flip-flop output. The first flip-flop 210 reset-down input and the second flip-flop 211 reset input can be connected to the output of the inverter logic gate 216. The input of the inverter logic gate can be the output of the NAND logic gate 215. The input of the NAND logic gate 215 can be the output of the first flip-flop 210 and the output of the second flip-flop 211. The first AND logic gate 217 can receive the output of the second flip-flop 211 and the frequency mode enable signal 212 as inputs. The output of NAND logic gate 215 can also be connected to the input of second AND logic gate 213. The second AND logic gate 213 can also receive the output of the first flip-flop 210. The OR logic gate 214 can also receive the output of the first AND logic gate 217 as an input.

  The phase frequency detector 202 can operate in two modes using the exemplary configuration described above. The two modes are sometimes called a phase mode and a frequency mode. In some embodiments, phase mode may be enabled if the value of frequency mode enable signal 212 is low, ie, “0”. In some embodiments, the frequency mode may be enabled if the value of the frequency mode enable signal 212 is high, ie, “1”. Since the first AND logic gate 217 receives the frequency mode enable signal 212 as one of its inputs, the output of the first AND logic gate 217 must always be low during the phase mode. As shown in FIG. 2, in the phase mode, the OR logic gate 214 always receives a low output that makes the VCO clock signal 208 transparent, ie, a “0” output, from the first AND logic gate 217. The output of the OR logic gate 214 (denoted “Up”) is always the divided VCO clock signal 208.

  In some embodiments, the high state, or “1” state, of the divided VCO clock signal 208 can be proportional to the period of the VCO. This is possible because the N divider 107 can be a VCO cycle counter, depending on its implementation. Thus, in some embodiments, the “Up” signal (the output of OR logic gate 214), which can be connected to the charge pump Up source (which may also be referred to as the “source” of the charge pump), is in each cycle. Can be on for α (ie, a fixed number) VCO cycles. Because the “Down” signal can be connected to the Down source of the charge pump (sometimes referred to as the “sink” of the charge pump) in some embodiments and can be controlled by the phase frequency detector 202. If the average is taken, the “Down” signal can cancel the “Up” signal. Since the second AND logic gate 213 can expect the reset of the first flip-flop 210, the reset delay of the down path does not depend on the state of the divided VCO clock signal 208. The reset timing of the first flip-flop 212 depends on the state of the divided VCO clock signal 208 in some embodiments.

  In some embodiments, the coefficient of the VCO between the input voltage and the output frequency is assumed to be positive (ie, the output frequency increases as the input voltage increases). By changing the connection between the phase frequency detector output pair and the charge pump source pair when the VCO has a negative coefficient (ie, the output frequency decreases as the input voltage increases) Various embodiments are also applicable. The Up signal can be connected to the Down source (or “sink”) of the charge pump, and the Down signal can be connected to the Up source (or “source”) of the charge pump. The assumption that the coefficient of the VCO is positive can also be applied to the other embodiments described, unless stated to negate it.

  FIG. 3 shows an exemplary diagram 300 of a signal diagram associated with fractional-N modulation having a “Down” output and an “Up” output of a phase frequency detector. In the exemplary diagram 300, the relationship between the divided VCO signal 301, the reference clock signal 302, the phase frequency detector “Down” signal 303, the phase frequency detector “Up” signal 304, and the charge pump current 305 is illustrated. Show. As shown in the exemplary diagram 300, the “Up” signal (source) 304 can provide a constant amount of charge (in some embodiments, a constant pulse) in each cycle, but “Down” The signal (source) can be modulated by a ΣΔ modulator sequence. As a result, high linearity in the charge pump (output) can be achieved despite the mismatch between the charge pump “Up” signal (source) and the “Down” signal (source). That is, since the “Down” source can be controlled by the phase frequency detector 202 in some embodiments, the “Down” source can cancel the “Up” source if averaged. Furthermore, the duration of the pulses in the “Up” signal can be tied to the divided VCO signal 301 so that the divided VCO signal 301 can compensate for any time variation due to fractional N modulation. In general, the “Up” source and the “Down” source can be in the high state at the same time, thus reducing the breakthrough of the reference clock signal 302. Any static phase error associated with this exemplary embodiment can be generated by the high state duration of the divided VCO signal 301 and can be independent of the charge pump current 305. In PLL embodiments where the charge pump settings are dynamically switched, the static phase error of such embodiments can remain unchanged and remain phase locked.

  In some embodiments, the maximum current for an “Up” source (eg, “Up” source 304) is equal to the nominal charge pump current (eg, charge pump current 305) divided by the duty of the divided VCO signal 301. Limited to cycles multiplied. Such an implementation may be restrictive, but it may be possible to switch to the frequency mode (described above). In the frequency mode, the “Up” source can be controlled by the second flip-flop 211 and the divided VCO clock signal 208 (as shown in the exemplary embodiment of FIG. 2). The range of phase frequency detectors (eg, phase frequency detector 202) in frequency mode can be extended to, for example, standard three-state phase frequency detector values and can be symmetric. In some embodiments, a non-linear response may make such an implementation inappropriate for phase-locked conditions. One such embodiment may be appropriate for a fast locking PLL with simultaneous low noise requirements. The initial stage of the locking process can be performed in frequency mode, thus ensuring optimal frequency and coarse phase reacquisition. Thereafter, the phase frequency detector 202 can be switched to a phase mode (as described above) to reach a stable phase lock state. Since the static phase error between the frequency mode and the phase mode can be the same, switching between the two modes may not cause a strong phase disturbance.

  FIG. 4 shows an exemplary embodiment of a PLL circuit phase frequency detector and charge pump connected in series with a fractional N modulator (as shown in FIG. 2), where the frequency mode signal is Always low, ie, “0”, and an exemplary embodiment of a phase frequency detector is for a “single mode” PLL. According to the logic circuit analysis already described with respect to FIG. 2, if the frequency mode enable signal 212 remains low, the logic circuit of FIG. 2 can be converted to the simpler circuit shown on the upper side of FIG. For PLL applications, there is not always a fast lock requirement, so the phase frequency detector circuit shown is applicable to PLLs that do not change modes, ie to single mode PLLs. It can be. The benefit of this embodiment of the phase frequency detector is that, as a result of the charge pump output, a highly linear from well-noise-shaped ΣΔ modulator to charge amount without incurring degradation in the loop filter connected to the VCO. Is to provide a conversion.

  FIG. 5 shows an exemplary embodiment 500 of a PLL circuit phase frequency detector and charge pump 502 in series with a fractional N modulator. The exemplary embodiment 500 includes a frequency detector and charge pump 502 where the “Up” and “Down” signals between the phase frequency detector and the charge pump are symmetrical. Through the configuration of the reference clock 501, the divided VCO clock 508, the first flip-flop 510, the second flip-flop 511, and the NAND logic gate 512, when the reference clock 501 rises, “Up” "Up" signal falls when the divided VCO clock 508 rises, "Down" signal rises when the divided VCO clock 508 rises, and the reference clock 501 When rising, the “Down” signal falls. When using fractional N modulation in a fractional N PLL frequency synthesizer where the divided VCO clock 508 is modulated by a ΣΔ modulator, both the pulse width of the “Up” signal and the pulse width of the “Down” signal are determined by the modulator. Modulated. Simultaneous modulation of the Up and Down signals produces a somewhat non-linear characteristic in some embodiments shown in FIG. 3 and described with respect to FIG. 3 has a symmetrical configuration of the Up signal (source) and the Down signal (source), but realizes a precisely symmetrical characteristic between the Up path and the Down path in an actual circuit. It becomes difficult. An illustrative explanation of the non-linearity is that the Up source (“source”) is composed of PMOS, the Down source (“sink”) is composed of NMOS, and the process of matching between PMOS and NMOS is usually It is a conventional configuration of a charge pump that is not very complete.

  FIG. 6 shows the Up signal value and the Down signal value in relation to the reference clock and the divided VCO clock supplied to the phase frequency detector (as shown in FIGS. 2 and 4). The “1” (high level) and “0” (low level) charts of FIG. 6 can be analyzed in conjunction with the logic circuit in the low frequency mode shown in FIG. 2 and by the logic circuit shown in FIG. it can. In some embodiments, as shown in FIG. 6, the Up signal is “up” when the divided VCO clock rises and “up” when the divided VCO clock falls. When the “Up” signal falls and the divided VCO clock rises, the “Down” signal rises, and when the reference clock rises, the “Down” signal falls. This configuration of the Up and Down signals is characterized by a linearity advantage beneficial to the fractional N PLL compared to the embodiment shown in FIG. The reason underlying the advantage is shown in FIG. 3, and as explained with respect to FIG. 3, the pulse width of the Down signal is affected by the ΣΔ modulator, while the pulse width of the Up signal is Even if it is modulated by the ΣΔ modulator, it is constant with respect to the divided VCO clock. In some embodiments, the Down path is “modulated” by a ΣΔ modulator, and the PLL is driven by a practical asymmetric characteristic between the Up path and the Down path placed between the phase frequency detector and the charge pump. Freed from nonlinear problems caused.

  FIG. 7 shows an example method step 700 for a phase frequency detector (for a single mode PLL). Phase frequency method step 700 is divided by N, step 701 receiving a signal oscillating at a reference frequency at a first input, and step 702 receiving an output signal divided by N at a second input. Receiving the output signal at a first flip-flop trigger input of the first flip-flop, wherein the first flip-flop includes a reset input and a first flip-flop output; Receiving 704 a signal oscillating at a reference frequency at a second flip-flop trigger input of the second flip-flop, the second flip-flop including a reset input and a second flip-flop output; 704, first flip-flop output and second flip Step 705 for receiving the rop output at the NAND logic gate, Step 706 for receiving the first flip-flop output and the output of the NAND logic gate at the second AND logic gate, and the output of the NAND logic gate for the inverter logic. Step 707, receiving at the gate, wherein the output of the inverter logic gate is connected to the reset input of the first flip-flop and the reset input of the second flip-flop.

  FIG. 8 shows exemplary method steps 800 for a phase frequency detector (for dual or multimode PLL). Phase frequency detector method step 800 includes step 801 for receiving a signal oscillating at a reference frequency at a first input, step 802 for receiving an N-divided output signal at a second input, and N minutes. Receiving a rounded output signal at a first flip-flop trigger input of a first flip-flop, wherein the first flip-flop includes a reset-down input and a first flip-flop output; 803 and receiving at 804 a signal oscillating at the reference frequency at the second flip-flop trigger input of the second flip-flop, the second flip-flop receiving the reset input and the second flip-flop output. Including step 804, first flip-flop output and first The first flip-flop output at the NAND logic gate, the step 806 for receiving the second flip-flop output and the frequency mode enable signal at the first AND logic gate, and the first flip-flop output and the NAND. Receiving the output of the logic gate at the second AND logic gate at step 807 and receiving the output of the NAND logic gate at the inverter logic gate at step 808, wherein the output of the inverter logic gate is the first flip-flop; Step 808 connected to the reset input of the second flip-flop and the reset input of the second flip-flop, and step 809 receiving the output of the first AND logic gate and the N-divided output signal at the OR logic gate.

  FIG. 9 shows exemplary method steps 900 for a PLL circuit having a fractional N modulator. The PLL method step 900 is divided by N by a step 901 for providing a VCO output signal by a voltage controlled oscillator (VCO), a step 902 for receiving the VCO output signal at an N divider, and an N divider. Providing the output signal, step 904 modulating the output signal divided by N by the modulator, receiving step 905 a signal oscillating at the reference frequency at the first input, and dividing by N The received output signal at a second input, a step 906, a first phase of a signal oscillating at a reference frequency, and a second phase of the N-divided output signal, a phase frequency detector and a charge And step 907 for comparing in the pump.

  It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover such modifications and variations as come within the scope of the appended claims and their equivalents.

Claims (6)

A phase frequency detector circuit applied to a fractional-N synthesizer PLL (phase-locked loop) circuit,
A charge pump,
A VCO (voltage-controlled oscillator) for providing a VCO output signal;
An N divider for providing an N divided output signal having an input for receiving the VCO output signal;
A modulator for modulating the N-divided output signal;
A reference frequency supply;
In a phase frequency detector circuit comprising a loop filter,
The phase frequency detector circuit is
A first input for receiving a signal oscillating at a reference frequency;
A second input for receiving the N divided output signal;
Up signal output,
A Down signal output,
It said phase frequency detector circuit, before Symbol always the Up signal output rises when the second input is increased, always the Up signal output is lowered when said second input is lowered,
Phase frequency before Symbol second input the Down signal output rises when raised, the Down signal output when said first input is increased to said <br/> to have a mode that drops Detector circuit.   Applied to a PLL circuit having the VCO with a positive coefficient between the control voltage of the VCO and the frequency of the VCO output signal, the Up signal output driving the Up source of the charge pump and the Down signal output 2. The phase frequency detector circuit of claim 1, wherein the phase frequency detector circuit drives a Down source of the charge pump.   Applied to the PLL circuit having the VCO whose coefficient between the control voltage of the VCO and the frequency of the VCO output signal is negative, the Up signal output drives the Down source of the charge pump, and the Down signal output 2. The phase frequency detector circuit of claim 1, wherein the phase frequency detector circuit drives an up source of the charge pump.   The PLL circuit is applied to the PLL circuit having two or more modes that change between them over time, the Up signal output and the Down signal output can be changed, and the PLL circuit is close to a lock-up state. The phase frequency detector circuit of claim 1, wherein the phase frequency detector circuit is in a lockup state. A first flip-flop for receiving the N-divided output signal at a first flip-flop trigger input, the first flip-flop including a reset input and a first flip-flop output;
A second flip-flop for receiving at a second flip-flop trigger input the signal oscillating at a reference frequency, the second flip-flop including a reset input and a second flip-flop output;
A NAND logic gate for receiving the first flip-flop output and the second flip-flop output;
An AND logic gate for receiving the first flip-flop output and the NAND logic gate output;
An inverter logic gate for receiving the output of the NAND logic gate, the output of the inverter logic gate being connected to the reset input of the first flip-flop and the reset input of the second flip-flop; And further comprising an inverter logic gate,
The second input for receiving the N divided output signal comprises the Up signal output of the phase frequency detector, and the output of the AND logic gate is the Down signal of the phase frequency detector. The phase frequency detector circuit of claim 1, comprising an output. A first flip-flop for receiving the N-divided output signal at a first flip-flop trigger input, the first flip-flop including a reset input and a first flip-flop output;
A second flip-flop for receiving at a second flip-flop trigger input the signal oscillating at a reference frequency, the second flip-flop including a reset input and a second flip-flop output;
A NAND logic gate for receiving the first flip-flop output and the second flip-flop output;
A first AND logic gate for receiving the second flip-flop output and a mode change signal;
A second AND logic gate for receiving the first flip-flop output and the NAND logic gate output;
An inverter logic gate for receiving the output of the NAND logic gate, the output of the inverter logic gate being connected to the reset input of the first flip-flop and the reset input of the second flip-flop; An inverter logic gate;
An OR logic gate for receiving the output of the first AND logic gate and the N divided output signal;
The output of the OR logic gate comprises an Up signal output of the phase frequency detector, and the output of the second AND logic gate comprises a Down signal output of the phase frequency detector. A phase frequency detector circuit according to claim 1.

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