JPS6142014A - Digital speed controller - Google Patents

Abstract

PURPOSE:To supply a reference signal as a digital signal and to realize completely digital constitution by providing a speed comparing means, frequency dividing means, and up/down counter, and further various arithmetic means and a large-small decision means. CONSTITUTION:A digital filter 8 used as a new component as a substitute for an analog compensating filter is provided between the digital speed comparing means 3 and a pulse width modulating means 4. Then, speed error information D1 of the speed comparing means 3 is used as an input digital signal and an output digital signal D2 or D4 given filter characteristics digitally is inputted to the pulse width modulating means 4 to perform conversion to the frequency signal of a pulse-width modulated wave. Fruther, the digital filter 8 is given the reference value in the form of a reference digital signal D0 and its filter characteristics are set with clock pulses CK3. Further, the output digital signal of an applied digital filter is obtained through counting operation although the input digital signal is discrete, so it varies not discretely, but continuously.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to digital speed control devices.

Configuration of conventional example and its problems Figure 1 shows a conventional example of a digital speed control device.
2 is a controlled object (a motor or a rotating body driven by a motor); 2 is a rotation detector (10) that detects the number of revolutions of the controlled object;
3 is a digital speed comparison means; 4 is a pulse width modulation means (hereinafter referred to as PWM), which is a type of digital-to-analog converter; 6 is a smoothing filter (hereinafter referred to as LPF); The analog compensation filter 7 is a driving means for driving the controlled object 1. .

With the above configuration, the rotational speed, that is, the rotational speed of the controlled object 1, is detected by the FG2 as a signal with a frequency proportional to the speed (FG multiplied signal Sl).Then, this FG signal S1 is input to the digital speed comparison means 3, clock pulse C
The frequency is digitally discriminated by K1, and digital speed error information D1 is detected. Since the obtained speed error information D1 is an N-bit binary signal, it is a PWM type S whose pulse width is modulated by the clock pulse CK2 using PWM4.
Convert to PwM. Since this PWM wave is a square wave, it is passed through the KLPF5 to convert it into a direct current.

The analog compensation filter 6 receives the output of the LPF 5 as an input, and is used to fix the DC potential in a steady state to a reference voltage vDD/2. The output of the compensation filter e is then guided to the drive means 7, and a waveform diagram of the drive means 7, FIG. 3 is a specific circuit example of the compensation filter 6, and FIG. 4 is a frequency characteristic curve diagram of the circuit of FIG.

In FIG. 2, the latch pulse "LA" is a latch pulse and a preset pulse created from the SLA, 5PRViF G signal S1 and the clock pulse CK1, and takes out the output of the digital speed comparison means 3 consisting of an M-bit binary counter. This is a preset pulse SPR for setting an initial value in the counter of the speed comparison means 3.The latch pulse "LAd" is also preceded by the preset pulse SPR in terms of timing. STZ is a trapezoidal wave that is an analog representation of the digital operation of the speed comparison means 3. T,
is the reference period for speed comparison, and TFG is the period of the FG signal S1. A is a state where FG>Ti, the rotational speed of the controlled object 1 is slower than the reference speed, and the trapezoidal wave STz
The "L" level of is latched (sampled and an acceleration command is issued. B is the state of "FG""i" where the rotational speed is equal to the reference speed, and the central position of the slope of the trapezoidal wave STz is latched.C is in the state of TFG and T, the rotation speed is slower than the reference speed, and the trapezoidal wave "TZ" is
``The level is latched and a deceleration command is issued. Therefore, when the steady state of B shifts to the transient state of A or C, the acceleration voice issues a deceleration command and operates to return the controlled body 1 to the steady state.

Here, in the speed comparison means 3, the output in steady state B is determined to be the median value, that is, the output of PWM4 has a duty of 60ch, but the PWM wave SPwM is
Even if the current is converted to direct current and immediately led to the driving means 7, this condition is not always met. This is because the controlled object 1 has unique input/output characteristics, and the compensation filter 6 is required.

The compensation filter 6 has the meaning of matching the digital speed comparison means 3 and the controlled object 1, and uses a general proportional-integral circuit shown in FIG. Since this circuit can make the gain in the DC region infinite (actually the DC gain of the operational amplifier) as shown in FIG. 4, the above-mentioned contradiction can be resolved. That is, an operational amplifier 8 as shown in FIG.
(D'iE 4 (Apply a reference voltage vDD/2 to the input terminal, one end is connected to the negative phase input -, the other end is the input terminal, and the input resistor R is connected between the output terminal and the negative phase input - A circuit consisting of a feedback resistor Rf and a feedback capacitor Cf connected in series is used.The reference voltage vDD/2 is the power supply voltage v of the circuit.
The value is 1/2 of DD, and corresponds to f 60 chi of PWM wave SFWM. In this way, the controlled object 1
Regardless of the characteristics of the FG signal S1, the output level of the LPFs can be made to match the reference voltage vDD/2.
can be controlled so that the period "FG" always matches the reference period Ti.

Here, the transfer function G (S
) and frequency f1. As is well known, f2 is calculated using the following formula.

(2) f1=7 and 7, however, T1==Ri・Cf and T2=Rf−CfSS are ゛plus operators.

Equation (1) can be further expanded into Equation K(4).

From this, it is clear that the circuit of FIG. 3 is a proportional-integral circuit having a proportional element (first term) and an integral element (second term). Furthermore, if Rf=O, it is an integrating circuit with only integral elements.

As is clear from the above explanation, the reference is ultimately given as an analog value VDD/2, and even though it is a digital speed control device, variations in the reference voltage VDD/2 and , PWM wave SPWM distortion,”
There were problems such as deviations due to factors such as irregularities in the L' and "H" levels, and being affected by temperature and changes over time.Objective of the InventionThe present invention solves the above-mentioned conventional problems. It is an object of the present invention to provide a digital speed control device that is not affected by analog elements by digitizing such a compensation filter. speed comparison means for digitally detecting; an up-down counter whose output is used as a clock signal and at least one most significant bit of the input digital signal is used as an up-down signal input, and the controlled object is controlled by the output digital signal of the up-down counter. By providing a reference value as a reference digital signal, it is possible to provide a completely digital speed control device that is not affected by analog elements. The reference digital signal can be set to an arbitrary value by newly providing a discrimination means and using the output of this magnitude discrimination means as the up-down signal input of the up-down counter.

Furthermore, a multiplication means for multiplying the input digital signal by a coefficient and an addition or subtraction means for adding or subtracting the output of the multiplication means and the output of the up-down counter are newly provided, and a proportional element is added to the above-mentioned integral element. can be taken.

DESCRIPTION OF THE EMBODIMENTS FIG. 5 is an electrical block diagram of a digital speed control device showing the basic configuration of the present invention. Figure 6.

FIG. 7 shows a specific example of the configuration of the digital filter 8 in FIG.

Fig. 6 The difference in configuration between the present invention and the conventional example shown in Fig. 1 is that the analog compensation filter 6 is removed and the digital filter 8 is used.
is used as a new component, the digital filter 8 is provided between the digital speed comparison means 3 and the PWM 4, and the speed error information D1 of the speed comparison means 3 is used as a human-powered digital signal, and the filter characteristics are digitally calculated. PWM4 output digital signal D2 or D4 with added
The configuration is such that the input signal is converted into a PWM wave SPWM.

Further, the digital filter 8 can provide a reference value with the reference digital signal D0, and can set its filter characteristics with the third clock pulse CK3.

A specific example of the digital filter 8 will be explained in detail below with reference to FIGS. 6 and 7.

In FIG. 6, 8a is a size discrimination means, 8b is a frequency dividing means, 8C is an up/down counter, 8d is a multiplication means, 8
e is an addition means.

The input digital signal D1, that is, the speed error information of the speed comparing means 3, is input to the magnitude determining means 8a, and the magnitude is determined from the reference digital signal D0. For example, when Do>D, "L" (or H), D0 “H” when ≦D1
(or “L”) output, or when DokuDl”
L'' (or H''), and when D0≧D1, an output of "H" (or "I,') is obtained. The frequency dividing means abK inputs the input digital signal D1, the reference digital signal D0, and the clock pulse CK3, Absolute value ID of the difference between Dl and Do
,-D.

The clock pulse CK3 is frequency-divided to a frequency proportional to , and a frequency-divided output S3 is obtained.

The up/down counter 8C uses the frequency division output S3 as a clock input and the magnitude discrimination output S2 as an up/down signal input, and counts up (or down) when the up/down signal is "L" and counts down when it is "H#". (or up).In this way, the up/down counter 8C is configured to count up the input digital signal D.
1 and the reference digital signal, the absolute value ID1-Dol
Amplification or down-counting operates depending on the size relationship. That is, an integral operation can be performed. This is the third
This is a digital implementation of the circuit operation shown in the figure.

Here, if Dl>Do is set as down, the polarity of the output digital signal D2 becomes negative, which is the same polarity as in the conventional example shown in FIG. Conversely, if the amplifier is set when D1〉Do, the polarity becomes positive. That is, it can be set to positive or negative polarity by setting up and down.

On the other hand, the input digital signal D1 is inputted to the multiplication means 8d, and an output digital signal D3 obtained by multiplying by a coefficient K is obtained. Furthermore, the 1 addition or subtraction means 8e adds or subtracts the output D2 of the up/down counter 8C and the output D3 of the multiplication means 8d to obtain an output digital signal D4.

Here, the addition or subtraction means 8e is configured to perform addition when the polarities of the up/down counter 8C and the multiplication means 8d are the same, and to perform subtraction when the polarities are opposite.

The output digital signal D2 of the up/down counter 8C thus obtained is an integrated output, and the output digital signal D3 of the multiplier 8d is a proportional output multiplied by a coefficient. However, the output digital signal D4 of the addition or subtraction means 8θ is a proportional-integral output. Therefore, when the digital filter 8 in FIG. 6 is a proportional-integral element, it is sufficient to use the output digital signal D4 of the addition or subtraction means 8e, and when it is only an integral element, the output digital signal D2 of the up-down counter 8C is used. Just use it. In the latter case, the multiplication means 8d and addition or subtraction means 8e
is unnecessary and can be deleted. FIG. 7 shows a second embodiment in which the configuration of FIG. 6 is simplified. That is, the size determining means 8a is removed, and at least one most significant bit S4 of the input digital signal D1 is used as an up-down signal input to the up-down counter 8C. For example, a reference digital signal. is the median value (1/
2) If it is set to 10 to 0 (or 01 to 1) and the most significant bit S4 of the input digital signal D1 is used as an up/down signal, it is possible to create a configuration in which the size determining means 8a is removed. . However, the size discrimination means 8a
The embodiment of FIG. 6 has the advantage that the reference digital signal D0 can be set to any value. However, in such a digital complete speed control device, since it is necessary to widen the dynamic range of the speed comparison means 3, it is desirable to use the median value of the input digital signal D1 as the reference digital signal D0, and in this respect, the configuration shown in FIG. It is enough.

In addition, the up/down counter Bat/ in FIGS. 6 and 7
For C, it is necessary to add measures against overflow and underflow. This means that when the counter output D2 reaches the maximum value with the up command, it will stop counting, and with the next down command, it will count down, and when it reaches the minimum value trap with the down command, the count will stop [11], and with the next up command, it will count down. Configure it to count up. Furthermore, the output D4 of the addition or subtraction means 8e may be configured to pass through a limiter circuit (not shown) so that it becomes equal to the number of bits of the input digital signal D1.

Transfer function G(S) of the digital filter 8 explained above
becomes. This converts equation (4) into T2/T1=, T1=1/
It is nothing but 2 when placed as f'cK3. here,
K is the coefficient of the multiplication means 8d, fcK3 is the clock pulse C
This is the minimum frequency of the divided output S3 obtained by dividing K3 by the frequency dividing means 8b, that is, the frequency of the divided output S3 when ID, -D01=1.

Note that digital filters having known integral characteristics and proportional-integral characteristics are usually achieved by cumulative addition. In this case, both the input and output digital signals change discretely,
You cannot get the smooth characteristics of analog type. On the other hand, in the case of the digital filter applied to the present invention, although the input digital signal is discrete, the output digital signal is obtained by a counting operation, and therefore changes more continuously rather than discretely. Therefore, a filter characteristic extremely close to that of an analog can be obtained.The digital speed control device of the present invention includes a speed comparison means, a division means, an up/down counter, a multiplication means, an addition or subtraction means, a magnitude By providing the discrimination means, the reference value can be given as a digital signal, and complete digitalization that is not affected by analog elements can be achieved. In addition, the characteristics of digital filters can be made very close to those of analog type, and the filter characteristics can be set by clock pulses and have many features such as being unaffected by temperature and changes over time. Its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is an electrical block diagram showing a conventional digital speed control device, FIG. 2 is an operating waveform diagram of the digital speed comparison means, and FIG. 3 is a circuit diagram showing an analog compensation filter.
Fig. 4 is a frequency class characteristic curve diagram of Fig. 3, Fig. 6 is an electrical block diagram showing a digital speed control device according to an embodiment of the present invention, and Figs. ．． FIG. 7 is an electrical block diagram showing a second specific example. 3... Digital speed comparison means, 8... Digital filter, 8a... Size discrimination means, 8b
・Frequency dividing means, 8C...up/down counter,
8d... Multiplication means, 8e... Addition or subtraction means. Figure 1 l Figure 5

Claims (2)

[Claims] (1) Speed comparison means for digitally detecting speed error information of a controlled object; the output of the speed comparison means is used as an input digital signal, and a clock pulse is generated at a frequency proportional to the absolute value of the difference from the reference digital signal. a frequency dividing means for dividing a frequency, and a magnitude determining means for determining the magnitude of at least one most significant bit of the input digital signal or the input digital signal and the reference digital signal, the output of the frequency dividing means being a clock input; 1. A digital speed control device comprising: an up-down counter whose output is an up-down signal input; the rotational speed of the controlled object is controlled by the output digital signal of the up-down counter. (2) A speed comparison means for digitally detecting speed error information of the controlled object; the output of the speed comparison means is used as an input digital signal, and a clock pulse is generated at a frequency proportional to the absolute value of the difference from the reference digital signal. a frequency dividing means for dividing a frequency, and a magnitude determining means for determining the magnitude of at least one most significant bit of the input digital signal or the input digital signal and the reference digital signal, the output of the frequency dividing means being a clock input; An up-down counter whose output is an up-down signal input, a multiplication means for multiplying the input digital signal by a coefficient, and an addition or subtraction means for adding or subtracting the output of the up-down counter and the output of the multiplication means. A digital speed control device, characterized in that the rotational speed of the controlled object is controlled by the output digital signal of the addition or subtraction means.