JPH0646872B2 - Digital speed controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital speed control device.

Configuration of Conventional Example and Its Problems FIG. 1 shows a conventional example of a digital type speed control device.
Is a controlled body (a motor or a rotating body driven by a motor), 2 is a rotation detector (hereinafter referred to as FG) for detecting the number of rotations of the controlled body 1, 3 is a digital speed comparison means, 4
Is a pulse width modulation means (hereinafter referred to as PWM), which is one type of digital-analog converter, 5 is a smoothing filter (hereinafter referred to as LPF), 6 is an analog compensation filter, and 7 drives the controlled object 1. It is a driving means.

With the above configuration, the rotation speed of the controlled object 1, that is, the rotation speed, is detected by the FG 2 as a signal (FG signal) S1 having a frequency proportional to the speed. Then, this FG signal S1 is input to the digital speed comparison means 3, and the clock pulse C
The frequency is digitally discriminated by K1, and the digital speed error information D1 is detected. Since the obtained speed error information D1 is an N-bit binary signal, the PWM signal S pulse-width-modulated by the clock pulse CK2 by PWM4 is used.
Convert to _PWM . Since this PWM wave S _PWM is a square wave, it is passed through the LPF 5 to convert it into a direct current. The analog compensation filter 6 receives the output of the LPF 5 and fixes the DC potential in the steady state to the reference voltage V _DD / 2. Then, the output of the compensation filter 6 is guided to the drive means 7, and the drive means 7 controls the rotation speed of the controlled body 1 to be constant.

2 is a waveform diagram showing the operation of the digital speed comparison means 3, FIG. 3 is a concrete circuit example of the compensation filter 6, and FIG. 4 is a frequency characteristic curve diagram of the circuit of FIG.

In FIG. 2, S _LA and S _PR are a latch pulse and a pull set pulse created from the FG signal S1 and the clock pulse CK1, and a latch for taking out the output of the digital speed comparison means 3 composed of an M-bit binary counter. It is a preset pulse S _PR for setting an initial value to the pulse S _LA and the counter of the speed comparison means 3. Latch pulse S
_LA precedes the preset pulse S _{PR in} timing. S _TZ is a trapezoidal wave in which the digital operation of the speed comparison means 3 is analog-displayed. T _i indicates the reference period for speed comparison, and T _FG indicates the period of the FG signal S1. A
Is a state in which the rotational speed of the controlled object 1 is slower than the reference speed in the state of T _FG > T _i , the “L” level of the trapezoidal wave S _TZ is latched (sampled), and an acceleration command is issued. In the state of T _FG > T _i , B is in a state where the rotation speed is equal to the reference speed and latches the central position of the inclined portion of the trapezoidal wave S _TZ .
C is a state in which T _FG <T _i and the rotation speed is slower than the reference speed, and the “H” level of the trapezoidal wave S _TZ is latched and a deceleration command is issued. Therefore, if the steady state of B shifts to the transient state of A or C, an acceleration or deceleration command is issued,
An operation for returning the controlled object 1 to the steady state is performed.

Here, in the speed comparison means 3, the output of the steady state B is determined to be the median value, that is, the output of the PWM 4 has a duty of 50%, but the PWM wave S _PWM is set to the LPF 5
This condition is not always met even if the current is converted into a direct current and is immediately guided to the driving means 7. This is because the controlled body 1 has unique input / output characteristics, and the compensation filter 6 is required.

The compensation filter 6 is controlled by the digital speed comparison means 3 and the controlled device.
It has the meaning of matching with the body 1, and is shown in Fig. 3.
The general proportional-integral circuit shown is used. This circuit is
As shown in the figure, the gain in the DC region is set to infinity (actually
The DC gain of the Peamplifier) can be used to solve the above contradiction.
It can be erased. That is, the positive voltage of the operational amplifier 8 as shown in FIG.
Reference voltage V for phase input +_DD/ 2 is applied to the negative-phase input-
Input resistance R whose ends are connected and whose other end is the input end_i,output
Feedback resistor R connected in series between the end and the negative-phase input- When
Feedback capacitor C A circuit formed by connecting is used. Standard
Voltage V_DD/ 2 is the power supply voltage V of the circuit_DDWith a value of 1/2 of
Yes, PWM wave S_PWMCorresponding to 50% duty
It In this way, regardless of the characteristics of the controlled object 1,
Without reference voltage V_DDThe output level of LPF5 matches / 2
Therefore, the period T of the FG signal S1 is_FGAlways
The reference period T_iCan be controlled to match
It

Here, the transfer function G _{(S) of the} frequency characteristic curve shown in FIG.
And frequencies ₁ and ₂ are calculated by the following equations as is well known.

However, T₁= R_i・ C , T_Two= C , S is Laplace
It is an arithmetic.

Equation (1) can be further expanded to equation (4).

From now on, the circuit shown in FIG. 3 has a proportional element (first term) and an integral element.
It is clear that it is a proportional-integral circuit that has a prime (second term)
Is. Also, R If = 0, the number of integration times of the integral element only
It is a road.

As is apparent from the above description, the reference is eventually given by the analog value V _DD / 2, and even if the speed control device is a digitalized one, there are variations in the reference voltage V _DD / 2. , PWM wave S _PWM distortion,
There have been problems such as deviation due to factors such as variations in the "L" and "H" levels, and the effects of temperature and changes over time.

An object of the present invention is to solve the above-mentioned conventional problems, and it is an object of the present invention to provide a digital speed control device which is not affected by analog elements by digitizing the compensation filter.

According to the present invention, a speed comparison means for digitally detecting speed error information of a controlled object, and an output of the speed comparison means as an input digital signal, a frequency proportional to an absolute value of a difference from a reference digital signal. Further comprising frequency dividing means for frequency-dividing the clock pulse, and an up / down counter for receiving the output of the frequency dividing means as a clock input and for inputting at least one most significant bit of the input digital signal as an up / down signal. The controlled object is controlled by the output digital signal of the up / down counter, and by providing the reference value with the reference digital signal, it is possible to provide a completely digital speed control device which is not influenced by analog elements.

The present invention also provides a magnitude discriminating means for discriminating between the input digital signal and the reference digital signal, and uses the output of the magnitude discriminating means as the up / down signal input of the up / down counter, thereby making the reference digital signal arbitrary. It can be set to any value.

Further, a multiplication means for multiplying the input digital signal by a coefficient and an addition or subtraction means for adding or subtracting the output of the multiplication means and the output of the up / down counter are newly provided, and a proportional element is added to the integral element. Can be taken.

Description of Embodiments FIG. 5 is an electrical block diagram of a digital speed control device showing the basic configuration of the present invention. 6 and 7 are the fifth
It is a specific configuration example of the digital filter 8 in the figure.

Fig. 5 Fig. 1 of the present invention Fig. 1 is different from the conventional example in that the analog compensation filter 6 is removed and the digital filter 8 is used.
The digital filter 8 is provided between the digital speed comparison means 3 and the PWM 4, and the speed error information D ₁ of the speed comparison means 3 is used as an input digital signal to digitally filter The output digital signal D ₂ or D ₄ to which the characteristic is added is converted into the PWM wave S _PWM as the input of the PWM ₄ .

Further, the digital filter 8 can give a reference value by the reference digital signal D ₀ and can set its filter characteristic by the third clock pulse CK3.

A specific example of the digital filter 8 will be described in detail below with reference to FIGS. 6 and 7.

In FIG. 6, 8a is a magnitude discriminating means, 8b is a frequency dividing means, 8c is an up / down counter, 8d is a multiplying means, and 8a.
e is an adding means.

The input digital signal D _1, that is, the speed error information of the speed comparing means 3 is input to the magnitude discriminating means 8a and discriminates the magnitude from the reference digital signal D _0. For example, when D ₀ > D ₁ , it is “L” (or “H”). "), When D ₀ ≤D ₁ " H "
(Or “L”) output, “L” (or “H”) when D ₀ <D ₁ , and “H” (or “L”) output when D ₀ ≧ D ₁ . The input digital signal D ₁ , the reference digital signal D ₀ and the clock pulse CK3 are input to the frequency dividing means 8b, and the absolute value of the difference between D ₁ and D ₀ | D ₁
The frequency of the clock pulse CK3 is divided into frequencies proportional to -D ₀ | to obtain the divided output S3.

The frequency-divided output S3 is used as a clock input and the magnitude discrimination output S2 is used as an up-down signal input to the up-down counter 8c. When the up-down signal is "L", up (or down) is counted, and when it is "H", down is performed. (Or up) Configure to count. In this way, the up / down counter 8c can receive the input digital signal D
Depending on the absolute value of the difference between ₁ and the reference digital signal | D ₁ -D ₀ | and the magnitude relationship, up or down counting is performed. That is, the integration operation can be performed. This is the third
The circuit operation in the figure is embodied digitally.

Here, when D ₁ > D ₀ is set to down, the polarity of the output digital signal D ₂ becomes negative and has the same polarity as the conventional example of FIG. On the contrary, if D ₁ > D ₀ is increased, the positive polarity is obtained. That is, the positive and negative polarities can be obtained by setting up and down.

On the other hand, the multiplication means 8d receives the input digital signal D _1, to obtain an output digital signal D ₃ multiplied by a factor K. Furthermore, the addition or subtraction unit 8e, the output D ₂ of the up-down counter 8c and the output D ₃ of the multiplier means 8d addition or subtraction to obtain an output digital signal D _4.

Here, the addition or subtraction means 8e is configured to perform addition when the polarities of the up-down counter 8c and the multiplication means 8d are the same, and to perform subtraction when the polarities are opposite.

The output digital signal D ₂ of the up / down counter 8c thus obtained is an integrated output, and the output digital signal D ₃ of the multiplication means 8d is a proportional output with a coefficient. Therefore, the output digital signal D ₄ of the adding or subtracting means 8e is a proportional integral output. Therefore, when the digital filter 8 of FIG. 5 is used as a proportional integration element, the output digital signal D ₄ of the addition or subtraction means 8e may be used, and when only the integration element is used, the output digital signal D ₂ of the up-down counter 8c is used. Should be used. In the latter case, multiplication means 8d and addition or subtraction means 8
e is unnecessary and can be deleted.

FIG. 7 shows a second embodiment in which the structure of FIG. 6 is simplified.
That is, the size discriminating means 8a is removed, and at least the most significant 1 bit S4 of the input digital signal D ₁ is used for the up / down signal input of the up / down counter 8c. For example, the reference digital signal D ₀ is the median value (1/2) 10 to 0 (or 01 to 1) of the input digital signal D _1.
And the most significant 1 bit S4 of the input digital signal D ₁ is used as an up / down signal. In this way, the size discriminating means 8a can be removed. However,
The embodiment of FIG. 6 having the magnitude discriminating means 8a has a feature that the reference digital signal D ₀ can be set to an arbitrary value. However, in such a digital speed control device, it is desirable to use the median value of the input digital signal D ₁ as the reference digital signal D _{0 because} the dynamic range of the speed comparison means 3 needs to be wide. Configuration is sufficient.

Note that it is necessary to add measures against overflow and underflow to the up / down counter 8c shown in FIGS. This is to count down when the counter output D ₂ reaches the maximum value by the up command, down count at the next down command, and stop when the down command reaches the minimum value, and up by the next up command. Configure to count. Further, the output D ₄ of the addition or subtraction means 8e may be passed through a limiter circuit (not shown) so as to be equal to the number of bits of the input digital signal D ₁ .

The transfer relationship G of the digital filter 8 described above
_(S) is Becomes This is expressed by equation (4) as follows: T ₂ / T ₁ = K, T ₁ = 1 /
It is nothing but the formula when it is put _as'CK3 . here,
K is a coefficient multiplication means _{8d, 'CK3} is divided output obtained by dividing the clock pulse CK3 by the division means 8b S3
Is the minimum frequency, that is, the frequency of the divided output S3 when | D ₁ −D ₀ | = 1.

Note that a known digital filter having an integral characteristic and a proportional integral characteristic is usually achieved by cumulative addition. In this case, both the input and output digital signals change discretely, and smooth characteristics like those of the analog type cannot be obtained. On the other hand, in the case of the digital filter applied to the present invention, although the input digital signal is discrete, since the output digital signal is obtained by the counting operation, it is not discrete and changes more continuously. Therefore, a filter characteristic extremely close to an analog type can be obtained.

According to the digital speed control device of the present invention, by providing the speed comparison means, the frequency division means, the up / down counter, the multiplication means, the addition or subtraction means, and the magnitude determination means, the reference value is a digital signal. Can be given by
It is possible to achieve complete digitalization without being affected by analog elements. Also, the characteristics of the digital filter can be made to be very similar to those of the analog type, and the filter characteristics can be set by the clock pulse and are not affected by temperature and changes over time. Is large.

[Brief description of drawings]

FIG. 1 is an electrical block diagram showing a conventional digital speed control device, FIG. 2 is an operation waveform diagram of a digital speed comparison means, and FIG. 3 is a circuit diagram showing an analog compensation filter.
FIG. 4 is a frequency characteristic curve diagram of FIG. 3, FIG. 5 is an electrical block diagram showing a digital speed control device of an embodiment of the present invention, and FIGS. 6 and 7 are digital filter first and first examples. It is an electrical block diagram which shows the 2nd example. 3 ... Digital speed comparing means, 8 ... Digital filter, 8a ... Size discriminating means, 8b ... Dividing means, 8c
... up-down counter, 8d ... multiplication means, 8e ...
… Addition or subtraction means.

Claims (2)

[Claims] 1. A speed comparison means for digitally detecting speed error information of a controlled object, a digital filter for digitally processing an output of the speed comparison means, and a controlled object of the controlled object according to an output of the digital filter. A digital speed control device having a drive means for controlling a rotation speed, wherein the digital filter uses an output of the speed comparison means as an input digital signal and has a frequency proportional to an absolute value of a difference from a reference digital signal. And a frequency dividing means for dividing the clock pulse, and at least the most significant 1 bit of the input digital signal (or an output of discriminating between the input digital signal and the reference digital signal) as an up / down switching signal. Up-down for switching the polarity of the clock signal and counting the output of the frequency dividing means as a clock input. Counter constituted by a, digital speed control the output of the up-down counter and an output of the digital filter. 2. A speed comparison means for digitally detecting speed error information of a controlled object, a digital filter for digitally processing an output of the speed comparison means, and a digital filter for the controlled object according to an output of the digital filter. A digital speed control device having a drive means for controlling a rotation speed, wherein the digital filter uses an output of the speed comparison means as an input digital signal and has a frequency proportional to an absolute value of a difference from a reference digital signal. And a frequency dividing means for dividing the clock pulse, and at least the most significant 1 bit of the input digital signal (or an output of discriminating between the input digital signal and the reference digital signal) as an up / down switching signal. Up-down for switching the polarity of the clock signal and counting the output of the frequency dividing means as a clock input. A counter, multiplication means for multiplying the input digital signal by a coefficient, and addition or subtraction means for adding or subtracting the output of the up / down counter and the output of the multiplication means, and the output of the addition or subtraction means A digital type speed control device as an output of the digital filter.