JP2009065515A - Digital filter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital filter which reduces a power consumption for computation at a low accuracy. <P>SOLUTION: The digital filter includes: a gate part 109 for inputting a lower bit of input data and a control signal; a gate part 110 for inputting a lower bit of a coefficient and the control signal; a register 106 for holding and outputting an upper bit of the input data and an output of the gate part 109; a register 107 for holding and outputting an upper bit of the coefficient and an output of the gate part 110; a multiplier 103 for multiplying an output of the register 106 by an output of the register 107; an adder 104 for adding the multiplication result to the calculation result; a gate part 111 for inputting a lower bit of the addition result and the control signal; a register 108 for holding an upper bit of the addition result and an output of the gate part 111 to output them as the calculation result; and a control part 105 for outputting the control signal so as to zeroize at least one output of the gate parts 109, 110, 111. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a digital filter.

  The digital filter converts the sampling frequency to an integral multiple by arithmetic processing and is also called an oversampling filter. An FIR (Finite Impulse Response) filter capable of obtaining a linear phase characteristic is used for processing an audio signal such as a CD.

ここでｙ_ｋは出力信号、ｘ_ｋ、ｘ_ｋ−１、…、ｘ_ｋ−ｎは入力信号、ｈ_０、…、ｈ_ｎはフィルタ係数、ｎはフィルタの次数である。フィルタの特性はフィルタの次数（加算の段数）、フィルタ係数の細かさ（桁数）、演算の丸め誤差に依存する。 The FIR filter can be expressed by the following non-recursive difference equation.

Here, y _k is an output signal, x _k , x _k−1 ,..., X _k−n is an input signal, h ₀ ,..., H _n are filter coefficients, and n is a filter order. The characteristics of the filter depend on the order of the filter (the number of stages of addition), the fineness of the filter coefficient (number of digits), and the rounding error of the operation.

  As the configuration of the FIR filter, a coefficient memory that holds coefficient data, a data RAM that holds input data, a multiplier that multiplies the coefficient and the input data, a multiplication result, and the previous calculation result are added. A device including an adder, a coefficient memory, a data RAM, and a register for holding the output of the adder is known.

  A system that performs both A / D conversion (analog / digital conversion, hereinafter referred to as ADC) and D / A conversion (digital / analog conversion, hereinafter referred to as DAC), which requires higher accuracy than ADC, using only one filter having such a configuration. Then, when ADC is performed, an arithmetic circuit (multiplier, adder) that gives a calculation accuracy higher than necessary is used, and wasteful power consumption occurs.

  There has been proposed an arithmetic device that reduces the power consumption by reducing the number of significant digits by making the arithmetic precision variable by masking the lower bit portion of the input data to 0 (for example, Patent Document 1). reference).

  Such a function can be applied to input data in the implementation of a digital filter, but cannot be applied to a coefficient that is a constant value that does not depend on a calculation result. For this reason, computation may be performed with an unnecessarily high calculation accuracy, and the power consumption of the digital filter cannot be sufficiently reduced.

Since the filter processing is a multi-stage circuit, the circuit scale is large, and in an audio system or the like, continuous processing for a long time is increased. Therefore, for example, mobile devices that operate on batteries are required to reduce power consumption.
Japanese Patent Laid-Open No. 7-146777

  An object of the present invention is to provide a digital filter with reduced power consumption.

  A digital filter according to an aspect of the present invention includes a data storage unit that stores given data, a coefficient storage unit that stores coefficients, a predetermined lower bit of the data output from the data storage unit, and a control signal. A first gate section that is input; a second gate section that receives a predetermined lower bit of the coefficient output from the coefficient storage section; and the control signal; and the data that is output from the data storage section. Other than the predetermined lower bits of the first and second outputs of the first gate unit given and held, and other than the predetermined lower bits of the coefficient output from the coefficient storage unit The output of the second gate unit is given and held, and the second register to be output is multiplied by the output of the first register and the output of the second register, and the multiplication result is output. An adder that adds the multiplication result and the operation result and outputs the addition result; and a third gate to which a predetermined lower bit of the addition result output from the adder and the control signal are input And a third register for receiving and holding the output of the third gate unit other than the predetermined lower bits of the addition result output from the adder and outputting the calculation result, And a control unit that outputs the control signal so that the output of at least one of the first, second, and third gate units is set to zero.

  The digital filter according to one aspect of the present invention includes a data storage unit that stores given data, a coefficient storage unit that stores coefficients, a predetermined lower bit of the data output from the data storage unit, and a control A first gate unit to which a signal is input, a second lower gate unit to which a predetermined lower bit of the coefficient output from the coefficient storage unit and the control signal are input, and a clock signal and the control signal, respectively. The third, fourth, and fifth gate units that are input and the other than the predetermined lower bits of the data that are output from the data storage unit in synchronization with the clock signal are given, held, and output. 1 register, a second register that outputs and holds the output of the first gate unit in synchronization with the output of the third gate unit, and a second register that outputs and holds the output in synchronization with the clock signal. Other than the predetermined lower-order bits of the coefficient output from the coefficient storage unit, the third register to be output and held, and the second gate unit in synchronization with the output of the fourth gate unit A fourth register that receives and holds the output, and a multiplier that multiplies the outputs of the first and second registers and the outputs of the third and fourth registers and outputs a multiplication result; An adder that adds the multiplication result and the operation result and outputs an addition result; a sixth gate unit to which a predetermined lower bit of the addition result output from the adder and the control signal are input; In synchronization with the clock signal, except for the predetermined lower bits of the addition result output from the adder, the fifth register that outputs and holds and synchronizes with the output of the fifth gate unit. Of the sixth gate portion A sixth register that receives and holds and outputs power, a connection unit that receives the outputs of the fifth and sixth registers, and outputs the calculation result, and the first to sixth gate units. And a control unit that outputs the control signal so that at least one of the outputs is set to zero.

  In addition, a digital filter according to an aspect of the present invention stores first and second gate portions to which an enable signal and a control signal are input, and stores higher-order bit data among the supplied data. A data storage unit having a lower side data region for storing the upper side data region and lower bit side data to which the output of the first gate unit is applied, and storing the upper bit side of the coefficients and providing the enable signal A coefficient storage unit having a lower coefficient region for storing the higher-order coefficient region and the lower-bit side, to which the output of the second gate unit is given, and receiving and holding and outputting the output of the data storage unit 1 register, the second register that receives and holds the output of the coefficient storage unit, and outputs the first register, the output of the first register, and the output of the second register And a multiplier for outputting the multiplication result, an adder for adding the multiplication result and the operation result, and outputting the addition result, and receiving and holding the addition result, and outputting the result as the operation result. 3 and a control unit that outputs the control signal so that at least one of the lower-order data area and the lower-order coefficient area becomes invalid.

  According to the present invention, power consumption can be reduced.

  Hereinafter, digital filters according to embodiments of the present invention will be described with reference to the drawings.

  (First Embodiment) FIG. 1 shows a schematic configuration of a digital filter according to a first embodiment of the present invention. The digital filter includes a data RAM (Random Access Memory) 101, a coefficient memory 102, a multiplier 103, an adder 104, a control unit 105, registers 106 to 108, and gate circuits 109 to 111.

  The data RAM 101 holds input data to be input for calculation. The coefficient memory 102 holds coefficient data that is a filter coefficient for calculation. The data width of the output signal of the data RAM 101 is a + 1 bits, the data width of the output signal of the coefficient memory 102 is b + 1 bits, and the data width of the output signals of the multiplier 103 and the adder 104 is c + 1 bits (a, b, c are Both are positive integers).

  Of the input data output from the data RAM 101, the upper data ([a: i] bits) is input to the register 106, and the lower data ([i−1: 0] bits) is registered via the gate circuit 109. 106 is input. i is a positive integer smaller than a.

  A control signal output from the control unit 105 is supplied to the gate circuit 109. The low-order data input to the register 106 can be fixed to 0 by the control signal.

  Of the coefficient data output from the coefficient memory 102, the upper data ([b: j] bits) is input to the register 107, and the lower data ([j-1: 0] bits) is input via the gate circuit 110. Input to the register 107. j is a positive integer smaller than b.

  A control signal output from the control unit 105 is given to the gate circuit 110. The low-order data input to the register 107 can be fixed to 0 by the control signal.

  Multiplier 103 multiplies the output of register 106 and the output of register 107, and outputs the multiplication result to adder 104.

  The adder 104 is given the multiplication result and the output of the register 108 (the calculation result of the previous adder 104), and adds these.

  Of the operation data output from the adder 104, the higher-order data ([c: k] bits) is input to the register 108, and the lower-order data ([k−1: 0] bits) is passed through the gate circuit 111. Input to the register 108. k is a positive integer smaller than c.

  A control signal output from the control unit 105 is given to the gate circuit 111. The low-order data input to the register 108 can be fixed to 0 by the control signal. The control unit 105 continues to output a constant control signal during the operation of the digital filter.

  When performing a calculation with low accuracy required, the outputs of the gate circuits 109, 110, and 111 are fixed to 0 by the control signal, so that the corresponding areas of the registers 106, 107, and 108, the multiplier 103, and the adder 104 The lower bit arithmetic circuit is not activated. As a result, the circuit is not partially operated, and power consumption can be suppressed.

  As described above, the digital filter according to the present embodiment can reduce power consumption and improve the operating frequency.

  Here, the bit width fixed at 0 by the control signal (the lower i bits of the input data, the lower j bits of the coefficient data, and the lower k bits of the operation data) affects the output accuracy when the required operation accuracy is low. No digits.

  The control unit 105 may be a circuit that writes settings from the CPU using a control register. If the external terminal input is used as it is as a control signal, the filter accuracy can be changed for each chipset by fixing the external terminal.

  In the above embodiment, the gate circuit and the register are provided in the subsequent stage of the data RAM 101, the coefficient memory 102, and the adder 104, but may be provided in the subsequent stage of the multiplier 103.

  Further, although the control signal output from the control unit 105 is commonly given to the gate circuits 109 to 111, each gate circuit may be controlled separately. With such a configuration, more flexible calculation accuracy can be controlled.

Further, as shown in FIG. 2, a plurality of gate circuits to which lower-order data is given may be provided, and a control signal may be output from the control unit 105 to each gate circuit. Of the signals output from the data RAM 101, the coefficient memory 102, or the adder 104, the bit width fixed to 0 can be made variable, and finer calculation accuracy can be controlled. In the example illustrated in FIG. 2, the bit widths fixed to 0 among the m + 1-bit data input to the register 120 using the gate circuits 121a to 121c are the lower q ₃ +1 bit, the lower q ₂ +1 bit, and the lower q _1. Either +1 bit can be set. Here, m, q ₁ , q ₂ and q ₃ are positive integers satisfying m> q ₁ > q ₂ > q ₃ .

  (Second Embodiment) FIG. 3 shows a schematic configuration of a digital filter according to a second embodiment of the present invention. The digital filter includes a data RAM (Random Access Memory) 201, a coefficient memory 202, a multiplier 203, an adder 204, a control unit 205, registers 206 to 211, gate circuits 212 to 217, and a connection unit 218.

  The data RAM 201 holds input data to be input for calculation. The coefficient memory 202 holds coefficient data that is a filter coefficient for calculation. The data width of the output signal of the data RAM 201 is a + 1 bits, the data width of the output signal of the coefficient memory 202 is b + 1 bits, and the data width of the output signals of the multiplier 203 and the adder 204 is c + 1 bits (a, b, c are Both are positive integers).

  Of the input data output from the data RAM 201, the upper data ([a: i] bits) is input to the register 206, and the lower data ([i−1: 0] bits) is registered via the gate circuit 212. 207 is input. i is a positive integer smaller than a.

  A control signal output from the control unit 205 is given to the gate circuit 212. Data input to the register 207 can be fixed to 0 by the control signal.

  The register 206 operates in synchronization with the clock signal CLK. The register 207 operates in synchronization with the output of the gate circuit 213 to which the clock signal CLK and the control signal are input.

  Of the coefficient data output from the coefficient memory 202, the upper data ([b: j] bits) is input to the register 208, and the lower data ([j-1: 0] bits) is input via the gate circuit 214. Input to the register 209. j is a positive integer smaller than b.

  A control signal output from the control unit 205 is given to the gate circuit 214. The data input to the register 209 can be fixed to 0 by the control signal.

  The register 208 operates in synchronization with the clock signal CLK. The register 209 operates in synchronization with the output of the gate circuit 215 to which the clock signal CLK and the control signal are input.

  Multiplier 203 multiplies the outputs of registers 206 and 207 and the outputs of registers 208 and 209 and outputs the multiplication result to adder 204.

  The adder 204 is given the multiplication result and the output of the concatenation unit 218 (the calculation result of the previous adder 204), and adds these.

  Of the operation data output from the adder 204, the upper data ([c: k] bits) is input to the register 210, and the lower data ([k−1: 0] bits) is input via the gate circuit 216. Input to the register 211. k is a positive integer smaller than c.

  A control signal output from the control unit 205 is given to the gate circuit 216. The low-order data input to the register 211 can be fixed to 0 by the control signal.

  The register 210 operates in synchronization with the clock signal CLK. The register 211 operates in synchronization with the output of the gate circuit 217 to which the clock signal CLK and the control signal are input.

  The control unit 205 continues to output a constant control signal during the operation of the digital filter. When the required calculation accuracy is low, the outputs of the gate circuits 212, 214, and 216 are fixed to zero.

  Here, the bit width fixed at 0 by the control signal (the lower i bits of the input data, the lower j bits of the coefficient data, and the lower k bits of the operation data) affects the output accuracy when performing a calculation with low required accuracy. The number of digits is not given.

  The connection unit 218 connects the outputs of the registers 210 and 211 and outputs the result.

  When performing a calculation with low required accuracy, the clock signals supplied to the registers 207, 209, and 211 are fixed by fixing the outputs of the gate circuits 213, 215, and 217 by the control signal. Power consumption in 211 can be reduced.

  Further, by fixing the outputs of the gate circuits 212, 214, and 216 to 0, the lower bit arithmetic circuits of the multiplier 203 and the adder 204 are not activated. As a result, the circuit is not partially operated, and power consumption can be suppressed.

  Thus, power consumption can be reduced by the digital filter according to the present embodiment.

  In the above embodiment, the gate circuit and the register are provided in the subsequent stage of the data RAM 201, the coefficient memory 202, and the adder 204, but may be provided in the subsequent stage of the multiplier 203.

  In addition, although the control signal output from the control unit 205 is commonly supplied to the gate circuits 212 to 217, each gate circuit may be controlled separately. With such a configuration, more flexible control can be performed.

  Further, by applying the configuration as shown in FIG. 2, it is possible to control the calculation accuracy further finely.

  (Third Embodiment) FIG. 4 shows a schematic configuration of a digital filter according to a third embodiment of the present invention. The digital filter includes a data RAM (Random Access Memory) 301, a coefficient memory 302, a multiplier 303, an adder 304, a control unit 305, gate circuits 306 and 307, and registers 308 to 310.

  The data RAM 301 holds input data that is an input for calculation. The coefficient memory 302 holds coefficient data that is a filter coefficient for calculation. The data width of the output signal of the data RAM 301 is a + 1 bits, the data width of the output signal of the coefficient memory 302 is b + 1 bits, and the data width of the output signals of the multiplier 303 and the adder 304 is c + 1 bits (a, b, c are Both are positive integers).

  The data RAM 301 has an upper data area 301a that holds upper data ([a: i] bits) of input data and a lower data area 301b that holds lower data ([i-1: 0] bits). Have The output of the data RAM 301 is input to the register 308. i is a positive integer smaller than a.

  An enable signal is applied to the upper data area 301a, and an enable signal is applied to the lower data area 301b via the gate circuit 306. A control signal output from the control unit 305 is supplied to the gate circuit 306. Enable control of the lower data area 301b can be performed by the control signal.

  The coefficient memory 302 includes an upper coefficient area 302a that holds upper data ([b: j] bits) of coefficient data and a lower coefficient area that holds lower data ([j-1: 0] bits). 302b. The output of the coefficient memory 302 is input to the register 309. j is a positive integer smaller than b.

  An enable signal is given to the higher coefficient region 302a, and an enable signal is given to the lower coefficient region 302b via the gate circuit 307. A control signal output from the control unit 305 is given to the gate circuit 307. The enable control of the lower coefficient region 302b can be performed by the control signal.

  When performing a calculation with low accuracy required, the lower-order data area 301b and the lower-order coefficient area 302b are fixed to disabled by the control signal, and the lower-order bit arithmetic circuits of the multiplier 203 and the adder 204 are activated. Do not let As a result, the circuit is not partially operated, and power consumption can be suppressed.

  Further, since no memory access is performed in the lower data area 301b and the lower coefficient area 302b, power consumption can be reduced.

  Here, the bit width (lower i bits of the input data, lower j bits of the coefficient data) of the memory area fixed to 0 by the control signal is set to the number of digits that does not affect the output accuracy when the required calculation accuracy is low. .

  Thus, the digital filter according to the present embodiment can reduce power consumption when performing low-accuracy calculations.

  Although the control signal output from the control unit 305 is commonly supplied to the gate circuits 306 and 307, each gate circuit may be controlled separately. With such a configuration, more flexible calculation accuracy can be controlled.

  In this embodiment, the enable signal is controlled by disabling the enable signal given to the lower data area and the lower coefficient area by the control signal. However, the enable signal is used as the clock signal, and the clock signal is output from the control signal. The supply control may be performed to enable control.

  Each of the above-described embodiments is an example and should be considered as not limiting. The technical scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a schematic block diagram of the digital filter by the 1st Embodiment of this invention. It is a schematic block diagram of the digital filter by a modification. It is a schematic block diagram of the digital filter by the 2nd Embodiment of this invention. It is a schematic block diagram of the digital filter by the 3rd Embodiment of this invention.

Explanation of symbols

101 Data RAM
102 Coefficient memory 103 Multiplier 104 Adder 105 Control unit 106, 107, 108 Register 109, 110, 111 Gate circuit

Claims (5)

A data storage unit for storing given data;
A coefficient storage unit for storing coefficients;
A first gate unit to which a predetermined lower bit of the data output from the data storage unit and a control signal are input;
A second gate unit to which a predetermined lower bit of the coefficient output from the coefficient storage unit and the control signal are input;
A first register that receives and holds the output of the data other than the predetermined lower-order bit of the data and the output of the first gate unit, and outputs the data.
A second register that receives and holds and outputs the other than the predetermined lower bits of the coefficient output from the coefficient storage unit and the output of the second gate unit;
A multiplier that multiplies the output of the first register and the output of the second register and outputs a multiplication result;
An adder for adding the multiplication result and the operation result and outputting the addition result;
A third gate unit to which a predetermined lower bit of the addition result output from the adder and the control signal are input;
A third register that outputs and outputs the calculation result other than the predetermined lower-order bits of the addition result output from the adder and the output of the third gate unit;
A control unit that outputs the control signal so that an output of at least one of the first, second, and third gate units is set to 0;
A digital filter comprising:   At least one of the first, second, and third gate units includes a plurality of gate circuits, and the plurality of gate circuits each include a plurality of bits of the predetermined lower bits and the control signal. The digital filter according to claim 1, wherein the digital filter is input. A data storage unit for storing given data;
A coefficient storage unit for storing coefficients;
A first gate unit to which a predetermined lower bit of the data output from the data storage unit and a control signal are input;
A second gate unit to which a predetermined lower bit of the coefficient output from the coefficient storage unit and the control signal are input;
Third, fourth and fifth gate portions to which a clock signal and the control signal are input,
A first register that receives and holds data other than the predetermined lower bits of the data output from the data storage unit in synchronization with the clock signal, and outputs the first register;
A second register for receiving and holding and outputting the output of the first gate portion in synchronization with the output of the third gate portion;
A third register that receives and holds and outputs other than the predetermined lower bits of the coefficient output from the coefficient storage unit in synchronization with the clock signal;
A fourth register for receiving and holding and outputting the output of the second gate portion in synchronization with the output of the fourth gate portion;
A multiplier that multiplies the outputs of the first and second registers and the outputs of the third and fourth registers and outputs a multiplication result;
An adder for adding the multiplication result and the operation result and outputting the addition result;
A sixth gate unit to which a predetermined lower bit of the addition result output from the adder and the control signal are input;
A fifth register for receiving and holding and outputting other than the predetermined lower bits of the addition result output from the adder in synchronization with the clock signal;
A sixth register for receiving and holding and outputting the output of the sixth gate portion in synchronization with the output of the fifth gate portion;
A concatenation unit that is provided with outputs of the fifth and sixth registers and outputs the calculation results;
A control unit that outputs the control signal so that the output of at least one of the first to sixth gate units is set to 0;
A digital filter comprising: First and second gate portions to which an enable signal and a control signal are input;
Of the applied data, the upper bit data is stored and the upper data area to which the enable signal is applied is stored, and the lower bit data is stored to store the lower bit data and the output of the first gate unit is provided. A data storage unit;
A coefficient storage unit that stores the upper bit side of the coefficient and stores the upper side coefficient region to which the enable signal is given and the lower bit side that stores the lower bit side and is supplied with the output of the second gate unit;
A first register for receiving and holding and outputting the output of the data storage unit;
A second register for receiving and outputting the output of the coefficient storage unit; and
A multiplier that multiplies the output of the first register and the output of the second register and outputs a multiplication result;
An adder for adding the multiplication result and the operation result and outputting the addition result;
A third register for giving and holding the addition result and outputting as the operation result;
A control unit that outputs the control signal so that at least one of the lower-side data region and the lower-side coefficient region becomes invalid;
Digital filter with   The digital filter according to claim 1, wherein the control signal output from the control unit is a constant value during operation.

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