JP2004289417A - Digital filter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital filter capable of considerably reducing the circuit scale and obtaining the output data with high accuracy. <P>SOLUTION: The digital filter is provided with: switches 111 to 11n that select a value twice the filter coefficients of coefficient registers 211 to 21n when the delay data have a one-value or select a value zero when the delay data are another value and provides the output of the selected value on the basis of delay data in each stage of a shift register 10 which receives the input data expressed in a binary value; an adder circuit 12 for summing the data selected by the switches 111 to 11n; a total sum register 20 for storing the total sum of the filter coefficients; and a subtractor 22 for subtracting the total data SKn of the total sum register 20 from the summated data AD received from the adder circuit 12. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a non-recursive digital filter in which a predetermined filter coefficient is set to a plurality of taps, and in particular, a digital signal quantized with a bit number lower than a predetermined bit number is input, and a predetermined bit number The present invention relates to improvement of a circuit configuration of a digital filter that converts a digital signal into a digital signal.
[0002]
[Prior art]
In recent years, with the progress of digital technology, digital recording has become mainstream in audio and video recording methods. As one of digital processing methods for audio signals, a method called an oversampling method or a delta-sigma method has been proposed and put to practical use. These methods are one method of AD (Analog Digital) conversion for converting an analog signal into a digital signal. In these methods, an analog audio signal is sampled at a frequency higher than a predetermined sampling frequency, and is quantized with a bit number lower than a predetermined bit number to be converted into a digital signal. Next, the digital signal is band-limited by a low-pass filter including a digital filter, and is converted into a digital signal having a predetermined sampling frequency and a predetermined number of quantization bits by a decimation (decimation) process. Specifically, when a predetermined digital signal having a sampling frequency of 48 KHz and a quantization bit number of 16 bits is obtained, for example, sampling is performed at a sampling frequency that is nearly 10 times as large as 48 KHz, and AD conversion is performed by 1-bit quantization. For the digital signal obtained by such AD conversion, the digital low-pass filter limits the band to correspond to a low sampling rate, increases the number of bits by digital filter operation, and sets the sampling frequency to 48 kHz and the quantum This makes it possible to obtain a digital signal having 16 bits.
[0003]
In addition, next-generation CDs and the like in which digital signals sampled at a higher frequency than the signal band and quantized with a lower bit number and recorded on an optical disk or the like as in these methods are also referred to as super audio CDs, for example. Called and proposed.
[0004]
In a method called an oversampling method or a delta-sigma method, a low-pass filter composed of a digital filter as described above is important in determining sound quality and the like. For this reason, such a digital low-pass filter is usually constituted by a non-cyclic FIR digital filter having a linear phase characteristic. Further, in order to realize a filter having ideal frequency characteristics, a transversal type filter having a multistage number of taps and a filter coefficient for performing predetermined weighting is set for each tap is used. That is, in order to realize an FIR digital filter having ideal frequency characteristics, it is necessary to increase the number of taps. When the number of taps is increased, the number of calculations with the filter coefficient increases. As a result, there is a problem that the number of multipliers for this operation increases, and the circuit scale including the adder and the delay circuit increases.
[0005]
In order to cope with such a problem, there has been proposed a method for improving the circuit configuration of a digital filter so as to obtain desired characteristics while reducing the circuit scale (for example, see Patent Document 1).
[0006]
FIG. 9 is a block diagram showing a configuration of a digital filter in a conventional example.
[0007]
In FIG. 9, input data quantized by one bit is shifted by n stages in the shift register 10 in synchronization with a clock. Delay data D1 to Dn output from each stage of the shift register 10 are supplied to switches 111 to 11n, respectively. The delay data D1 to Dn are used as switching control signals for the switches 111 to 11n, respectively. The switches 111 to 11n select zero data when the value of the delay data from the shift register 10 is “0”, and select the coefficient registers 191 to 19n when the value of the delay data from the shift register 10 is “+1”. Is selected for each of the coefficient data K1 to Kn stored in. The coefficient data K1 to Kn have an h-bit width and represent coefficient values “k1” to “kn” corresponding to each filter coefficient. That is, the switches 111 to 11n are equivalent to executing the multiplication of the delay data D1 to Dn from each stage and the coefficient data K1 to Kn. The outputs of the switches 111 to 11n are added in the adder circuit 12 and output as m-bit output data.
[0008]
In general, an FIR digital filter requires a plurality of stages of delay circuits corresponding to the bit width of input data provided by a shift register or the like, and further requires multiplication of delay data from each delay by coefficient data having a plurality of bit widths. At this time, if the number of delay stages, that is, the number of taps is large, the number of multipliers for performing the multiplication increases, and the circuit scale becomes very large. On the other hand, in the above-described conventional example, a shift register having a 1-bit width is used for the delay circuit, and a switch or a circuit equivalent thereto can be used as a multiplier. A suitable digital filter can be realized.
[0009]
[Patent Document 1]
JP-A-2-186710
[0010]
[Problems to be solved by the invention]
However, the digital filter as in the conventional example processes 1-bit input data, that is, processes the binary value of the data “+1” and “0”, and outputs “positive value” and “negative value”. Are not processed. For this reason, there is a problem that a positive offset component is superimposed on the output data of the filter, and output data having an accurate value cannot be obtained due to the offset component. In particular, since the offset component changes depending on the filter coefficient to be set, depending on the filter characteristics, the offset component becomes a DC noise component, and when audio digital signals are handled, sound quality may be deteriorated.
[0011]
On the other hand, when an FIR digital filter is configured for binary input data of “positive value” and “negative value”, there is a problem that the circuit scale increases due to expression of data itself and processing for negative values. there were. That is, when the input data is configured as a “positive value” and a “negative value”, a commonly used two's complement notation is used. "" Is represented as "01" and "negative value" is represented as "11", which requires two bits. Further, in the case of an arithmetic operation for handling a negative value in two's complement notation, an inverting circuit for converting a negative value into a positive value and an adding circuit of “+1” may be required. As described above, in the case of using a configuration in which a negative value is handled, the influence of the offset component is eliminated, but the circuit scale may be increased.
[0012]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a digital filter capable of suppressing an increase in circuit scale of a digital filter and obtaining accurate output data.
[0013]
[Means for Solving the Problems]
In order to solve the above problems, a digital filter according to the present invention includes: a shift register that stores input data expressed in binary while shifting the data by a plurality of stages; a plurality of coefficient registers that store a plurality of filter coefficients; Based on the delay data in each stage of the register, when this delay data is one value, the value of the filter coefficient of the coefficient register corresponding to that stage is selected, and when this delay data is the other value, a value of zero is set. A plurality of selection circuits for selecting and outputting selected values as selection data, an addition circuit for adding each selection data from the plurality of selection circuits and outputting an addition result as addition data, A sum register for storing a half value of the sum of the filter coefficients stored in the coefficient register as sum data; Subtracted over data, a configuration in which a subtractor that outputs a subtraction result as output data.
[0014]
With such a configuration, the selection circuit that selects a filter coefficient or zero in accordance with the delay data of each stage has a function equivalent to a multiplier and realizes a reduction in circuit scale. Further, the offset component superimposed on the output data is removed by subtracting a half value of the sum of the filter coefficients stored in the sum register from the addition data from the addition circuit. This makes it possible to suppress an increase in the circuit size of the digital filter and to realize a digital filter capable of obtaining accurate output data.
[0015]
Further, the digital filter of the present invention includes an input terminal for inputting input data, a coefficient input terminal for inputting a plurality of filter coefficients, and shifting input data represented by 1 bit supplied to the input terminal by a plurality of stages. And a plurality of coefficient registers for respectively storing the plurality of filter coefficients supplied to the coefficient input terminal. The delay data is one value based on the delay data in each stage of the shift register. A plurality of selection circuits for selecting the value of the filter coefficient of the coefficient register corresponding to the stage, selecting the value of zero when the delay data is the other value, and outputting the selected value as selection data. An addition circuit for adding each selection data from the plurality of selection circuits and outputting a value corresponding to the addition result as addition data, and a coefficient input terminal An accumulator that accumulates a plurality of supplied filter coefficients by a plurality of values, outputs a value corresponding to the result of the accumulative addition as sum data, and subtracts the sum data from the sum data and outputs a subtraction result. The configuration includes a subtractor that outputs data and an output terminal that outputs output data.
[0016]
With such a configuration, in parallel with the setting of each filter coefficient in a predetermined coefficient register, each filter coefficient is sequentially cumulatively added by an accumulator to obtain total data. In addition, there is no need to separately calculate the sum data, and the processing for this calculation can be reduced. Therefore, it is possible to realize a digital filter in which arbitrary filter characteristics can be set, to suppress an increase in the circuit scale of the digital filter, and to realize a digital filter capable of obtaining accurate output data.
[0017]
Further, the digital filter of the present invention includes an input terminal for inputting input data, a coefficient input terminal for inputting a plurality of filter coefficients, and shifting input data represented by 1 bit supplied to the input terminal by a plurality of stages. And a plurality of coefficient registers for respectively storing the plurality of filter coefficients supplied to the coefficient input terminal. The delay data is one value based on the delay data in each stage of the shift register. A plurality of selection circuits for selecting the value of the filter coefficient of the coefficient register corresponding to the stage, selecting the value of zero when the delay data is the other value, and outputting the selected value as selection data. An addition circuit that adds each selection data from the plurality of selection circuits and outputs a value corresponding to the addition result as addition data, The sum data is fetched and stored at a predetermined timing, stored, and a sum register that outputs a value corresponding to the fetched sum data as sum data, subtracts the sum data from the sum data, and outputs a subtraction result as output data It has a subtractor and an output terminal for outputting output data. Further, the shift register has a set input for outputting the one value from all stages that output delay data when a set command signal is input, and the sum register includes a set input of the shift register. Is configured to take in addition data in accordance with the timing at which the set command signal is input to the CPU.
[0018]
With such a configuration, each filter coefficient is set in a predetermined coefficient register, and a value obtained by adding all the filter coefficients is output from the addition circuit in accordance with the timing at which the set command signal is input. The summation register stores the summation data by taking in the value obtained by adding all the filter coefficients. Therefore, every time the filter coefficient is changed, it is not necessary to separately calculate the summation data. Can be reduced. Therefore, it is possible to realize a digital filter in which arbitrary filter characteristics can be set, to suppress an increase in the circuit scale of the digital filter, and to realize a digital filter capable of obtaining accurate output data.
[0019]
Further, the digital filter of the present invention has an input terminal for inputting input data, a coefficient input terminal for inputting a plurality of filter coefficients, and one or the other value represented by 1 bit supplied to the input terminal. A shift register that stores input data having a plurality of stages while shifting the data, and a first selection control signal for selection control, and the first selection control signal is invalid based on the first selection control signal. In the case of, the value of the delay data of the shift register corresponding to the stage is selected, and when the first selection control signal is valid, the one of the above values is selected, and the selected value is converted to the second selection control signal. A plurality of first selection circuits, a plurality of coefficient registers respectively storing a plurality of filter coefficients supplied to a coefficient input terminal, and a second selection control signal based on a second selection control signal. When the selection control signal has one value, the value of the filter coefficient of the coefficient register corresponding to that stage is selected. When the second selection control signal has the other value, a value of zero is selected. A plurality of second selection circuits that output as selection data, an addition circuit that adds each selection data from the plurality of second selection circuits, and outputs a value corresponding to the addition result as addition data; At the predetermined timing, stores the sum data, and outputs a value corresponding to the fetched sum data as sum data, and subtracts the sum data from the sum data, and outputs the subtraction result as output data. It has a subtractor for outputting and an output terminal for outputting output data. Further, the sum register is configured to take in the added data in accordance with the timing at which the first selection control signal becomes valid.
[0020]
With such a configuration, each filter coefficient is set in a predetermined coefficient register, and a value obtained by adding all the filter coefficients from the adder circuit is output according to the timing at which the first selection control signal becomes valid. Is done. The summation register stores the summation data by taking in the value obtained by adding all the filter coefficients. Therefore, every time the filter coefficient is changed, it is not necessary to separately calculate the summation data. Can be reduced. Therefore, it is possible to realize a digital filter in which arbitrary filter characteristics can be set, to suppress an increase in the circuit scale of the digital filter, and to realize a digital filter capable of obtaining accurate output data.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0022]
(Embodiment 1)
FIG. 1 is a block diagram illustrating an example of a configuration of a digital filter according to Embodiment 1 of the present invention. This digital filter performs a filter operation by performing weighted addition on delay data obtained by delaying binary input data over a plurality of stages, and outputs output data of a plurality of bit widths band-limited by the filter operation. Filter. An offset correction unit for removing a DC component superimposed on data obtained by weighted addition is provided.
[0023]
In FIG. 1, binary input data is supplied to an input terminal 30 as 1-bit width data. In the first embodiment, the two values are “1” and “0”, and one of the two values is described as “1” and the other is described as “0”. Indicated by parentheses ""). The input data supplied to the input terminal 30 is supplied to the shift register 10, and is sampled and shifted according to the clock supplied to the clock terminal 32. The shift register 10 includes n (n is an integer of 2 or more) stages, that is, n taps, and delay data D1 to Dn output from each stage are respectively connected to switches 111 to 11n as selection circuits. Supplied to The delay data D1 to Dn operate as switching control signals for the respective switches 111 to 11n. The switches 111 to 11n select data having a value of zero when the value of the delay data from the shift register 10 is “0”, and select the data when the value of the delay data from the shift register 10 is “1”. , Select data previously stored in the coefficient registers 211 to 21n, and output the selected data as selected data. Here, the switches 111 to 11n function as multipliers for weighting equivalently. The coefficient registers 211 to 21n are registers in which coefficient values corresponding to predetermined filter coefficients k1 to kn in the present digital filter are stored in advance. The filter coefficients k1 to kn are filter coefficients that determine the transfer characteristics of the present digital filter. By setting the filter coefficients k1 to kn to predetermined values, the frequency characteristics of the present digital filter are also determined. In the configuration shown in FIG. 1, for the predetermined filter coefficients k1 to kn, coefficient values “2xk1” to “2xkn” corresponding to twice the filter coefficients are used as the predetermined coefficient data K1 to Kn, respectively, and stored in the coefficient registers 211 to Kn. 21n. The predetermined coefficient values "2xk1" to "2xkn" stored in the coefficient registers 211 to 21n are output as coefficient data K1 to Kn having a bit width of h (h is an integer of 2 or more). The switches 111 to 11n supply zeros or coefficient data selected based on the delay data D1 to Dn to the adder circuit 12. The addition circuit 12 adds all the selection data supplied from the switches 111 to 11n, and outputs the addition result as addition data AD having an m-bit width. As described above, the shift register 10, the switches 111 to 11n, the coefficient registers 211 to 21n, and the adding circuit 12 constitute the FIR digital filter unit 100.
[0024]
The sum register 20 is a register in which data corresponding to the sum of the filter coefficients k1 to kn is stored in advance. That is, the sum register 20 stores a coefficient sum value “Σkn” corresponding to the sum (k1 + k2 + k3 +... + Kn) of the filter coefficients k1 to kn as the sum data SKn, and outputs the sum data SKn from the sum register 20. Is done. The subtractor 22 is a subtractor that subtracts the sum data SKn from the sum register 20 from the sum data AD from the adder circuit 12. The subtraction result obtained by the subtractor 22 is supplied to the output terminal 31. From the output terminal 31, data having a p-bit width is output as output data of the digital filter. As described above, the offset correction unit 200 is configured by the sum register 20 and the subtractor 22.
[0025]
The operation of the digital filter according to the first embodiment configured as described above will be described below with reference to a more specific example. Here, as a specific example, a case where the number of stages of the shift register 10 is n = 4, that is, four stages will be described.
[0026]
For example, in each delay data, when D1 = “1”, D2 = “0”, D3 = “1”, and D4 = “0”, the switch 111 sets the coefficient value because the delay data D1 is “1”. The switch 112 selects zero because the delay data D2 is “0”, and the switch 113 selects the coefficient data “2xk3” because the delay data D3 is “1”. , And the switch 114 selects zero because the delay data D4 is “0”. Thus, the addition circuit 12 performs an operation equivalent to the addition of the coefficient value “2 × k1” of the coefficient register 211 and the coefficient value “2 × k3” of the coefficient register 213. The addition circuit 12 outputs a value “2x (k1 + k3)” obtained by adding the coefficient value “2xk1” and the coefficient value “2xk3” as the addition data AD. On the other hand, in the sum register 20, a coefficient sum value “ΣKn” corresponding to the sum (k1 + k2 + k3 + k4) of the filter coefficients k1 to k4, that is, “k1 + k2 + k3 + k4” is set in advance. Therefore, the sum data SKn having the value “k1 + k2 + k3 + k4” is subtracted from the addition data AD having the value “2x (k1 + k3)” by the subtracter 22. That is, at this time, the digital filter outputs output data having a value of “{2 × (k1 + k3) − (k1 + k2 + k3 + k4)}”.
[0027]
As in the digital filter of the present invention, even if the input data is 1 bit, each of the coefficient data K1 to Kn is, for example, data of a high bit width as shown as h bits, and is output data. Can also be output data of a high bit width as shown as, for example, p bits. That is, the present digital filter converts the input data input at a low bit width but input at a high sampling rate so as to be able to cope with a low sampling rate by limiting the band by a filter operation. It can be said that the bit width has been traded off to a higher bit width. Utilizing such a principle, for example, from 1-bit input audio data of a sampling rate of 3.072 MHz to 16-bit PCM (Pulse Code Modulation) audio data of a sampling rate of 48 KHz and a sampling rate of 1/64, Used for conversion.
[0028]
Although the configuration and operation of the digital filter according to the first embodiment have been described above, the digital filter according to the present invention is configured based on a modification of a filter operation expression described below. Hereinafter, the operation principle of the digital filter of the present invention will be described according to a modification of the filter operation expression.
[0029]
Generally, a filter operation expression of an FIR digital filter by weighted addition using a filter coefficient kr (r is 1 to n) is such that each delayed data is dr (r is 1 to n) and the output is Y Then, it is expressed by the following equation 1.
[0030]
Y = {drxkr} Equation 1
Note that the symbol Σ indicates that r is an arithmetic operation in parentheses from 1 to n (n is an integer of 2 or more), and the sum is obtained. That is, the right side of Expression 1 indicates that the calculation of {(d1 × k1) + (d2 × k2) +... + (Dnxkn)} is performed.
[0031]
Equation 1 can be modified as follows.
[0032]
Y = {(dr + 1−1) xkr} Equation 2
Further, Equation 2 can be modified as follows.
[0033]
Y = {(dr + 1) xkr} − {kr} Equation 3
Here, it is assumed that each delayed data dr takes "-1" or "+1" as a binary value. Then, (dr + 1) in Equation 3 takes “0” or “2” as a binary value. In other words, according to the value “0” or “1” of each of the delay data D1 to Dn, the value of 0 times the filter coefficient or the value of 2 × kr of the filter coefficient is added, and the calculation of Expression 3 is performed. Then, a configuration equivalent to the FIR type digital filter shown in Expression 1 can be realized. That is, Equation 3 can be further transformed into the following Equation 4.
[0034]
Y = {(2 × kr) × Dr} − {kr} Equation 4
Further, Equation 4 can be modified as follows.
[0035]
Y = {(2 × Dr−1) × kr} Equation 5
Equation 4 is an equation showing the configuration of the digital filter of the first embodiment shown in FIG. 1, and is equivalent to the operation equation of the FIR digital filter shown in Equation 1. Also, according to the comparison between Expressions 1 and 5, dr = 2 × Dr−1 and the value of Dr is “0” or “1”, and therefore dr is “−1” or “+1”.
[0036]
In other words, the digital filter according to the configuration of the first embodiment uses the input data to the shift register as binary data including a negative value “−1” and a positive value “+1”, and performs a filter operation expressed by Expression 1. Is equivalent to the configuration of a digital filter that performs Therefore, according to the present invention, a digital filter equivalent to an FIR type digital filter that inputs binary “−1” and “+1” can be configured with a simple configuration. That is, when the binary values “−1” and “+1” are represented by a binary number of two's complement, a two-bit width is usually required. A filter can be realized.
[0037]
On the other hand, as described above, when the filter operation of the low-pass filter characteristic is performed with the values “0” and “1” as they are as 1-bit input data, the output data is affected by the offset component. That is, since the input data does not have a negative value, it has an offset component as a DC component in the positive direction, and this offset component passes through a filter having a low-pass filter characteristic. As a result, the output data also has this offset component. Influence of ingredients appears. On the other hand, in the digital filter of the present invention, the FIR digital filter unit 100 first performs the same filter processing as the conventional one, and furthermore, the offset correction unit 200 removes this offset component. And it is possible to obtain accurate output data in which the influence of is suppressed.
[0038]
As described above, since the digital filter of the present invention is configured based on such an operation principle, it is possible to suppress an increase in circuit scale and obtain accurate output data without being affected by an offset component.
[0039]
In the configuration example of the first embodiment described with reference to FIG. 1, an example in which the coefficient registers 211 to 21n store the coefficient values corresponding to twice the filter coefficients has been described. It is also possible to realize this. For example, coefficient values corresponding to the respective filter coefficients are stored in the coefficient registers 211 to 21n, and the coefficient data input to the switches 111 to 11n is shifted by one bit in the upper bit direction, or By shifting the added data AD by one bit in the upper bit direction, data corresponding to twice the filter coefficient may be realized.
[0040]
FIG. 2 is a block diagram showing a modification of the configuration described with reference to FIG. 1 as an example. 2, coefficient data K1 to Kn having respective coefficient values “k1” to “kn” corresponding to the respective filter coefficients k1 to kn are stored in the coefficient registers 211 to 21n. And a multiplier 23 for multiplying by a constant “2”. That is, the process of selecting and adding the coefficient values “2xk1” to “2xkn” corresponding to twice the filter coefficients in the configuration of FIG. 1 is performed by the coefficient value “k1” corresponding to each filter coefficient as in the configuration of FIG. After selecting and adding "" to "kn", the same result can be obtained in a process of outputting as multiplied data that is twice the added data. Therefore, even with the configuration of FIG. 2, the same output result is obtained although the configuration is different from that of FIG. Although FIG. 2 shows a configuration in which the data is doubled by the multiplier 23, the addition data AD from the addition circuit 12 is bit-shifted by one bit in the upper bit direction, and the least significant bit LSB is a logical value. By setting “0”, double calculation can be easily realized.
[0041]
Further, in Expressions 2 and 3 described above, “1” can be replaced by “(１ ／)”, which is half, and a configuration based on the expression can be realized. Equations 2 and 3 are replaced with the following equations 2 ′ and 3 ′.
[0042]
Y = {(dr + (1/2)-(1/2)) xkr} Equation 2 ′
Y = {(dr + (1/2)) xkr}-{(1/2) xkr} Equation 3 '
Here, even if it is assumed that each delayed data dr takes "-(1/2)" or "+ (1/2)" as a binary value, it is equivalent to Equation 1. That is, the coefficient registers 211 to 21n store coefficient data K1 to Kn having coefficient values “k1” to “kn” corresponding to the filter coefficients k1 to kn, and the sum register 20 stores the filter coefficients k1 to kn. May be stored such that the sum total data SKn having a value that is a half of the coefficient sum value “$ kn” corresponding to the sum of.
[0043]
In other words, it suffices that there is a relationship that the sum data SKn stored in the sum register 20 is one half of the sum of the coefficient data K1 to Kn stored in the coefficient registers 211 to 21n. That is, the sum data SKn satisfying the relationship of SKn = (1/2) × (K1 + K2 +... + Kn) may be stored in the sum register 20.
[0044]
Further, in the output of a plurality of adders provided inside the adder circuit 12, the lower bits are truncated or rounded to reduce the bit width and to save the circuit scale. In this case, for example, the data value may be expressed as being divided by 2 to the power of a by truncating or rounding the lower bits by a bits. For example, if the lower 2 bits of the data bus are truncated for a data value "64" on a data bus having a bit width of 8 bits, the data value after the truncation can be expressed as "16". It can be expressed that the value is divided by four or multiplied by one fourth. In such a case, needless to say, the sum data SKn of the sum register 20 described above and the sum of the coefficient data K1 to Kn of the coefficient registers 211 to 21n are no longer half. That is, it is necessary to provide an expression that takes into account bit truncation. In consideration of such a case, the digital filter according to the present invention uses the sum register 20 to calculate the sum of these filter coefficients for data obtained by dividing the result of weighting and adding by the filter coefficient corresponding to each delay by a constant M. Is divided by a constant 2M, which is twice the constant M, to store the data. In other words, in such a case, the total sum data SKn satisfying the relationship of SKn = {1 / (2 × M)} x (K1 + K2 +... + Kn) may be stored in the total sum register 20. Here, the constant M is a constant introduced in consideration of the amount of bit truncation, and may be any number other than zero.
[0045]
That is, the digital filter according to the present invention is a data filter in which input data expressed in binary is delayed in the order of input, weighted addition is performed by a filter coefficient corresponding to each delay, and a result obtained by dividing by a constant M is obtained. And an offset correction for subtracting data of a value obtained by dividing the sum of the filter coefficients by a constant 2M, which is twice the constant M, from the data output from the FIR digital filter 100. And thereby, the circuit scale is reduced, the offset component superimposed on the output data is removed, and the accuracy of the output data is improved.
[0046]
Also, the switches 111 to 11n in FIGS. 1 and 2 have been described as examples of the selection circuit using switches, but may be realized by a gate circuit or by using a transfer gate. FIG. 3 is a diagram illustrating a specific configuration example in which the switches 111 to 11n in FIG. 1 are realized using a gate circuit or a transfer gate.
[0047]
FIG. 3A shows an example in which an AND gate 80 performing an AND operation is used, and the switch 11n is shown as a representative. As the coefficient data Kn, an input data value “2xkn” twice the filter coefficient kn, a logical value “0” is input to the LSB which is the least significant bit, and each bit higher than the LSB has a filter coefficient kn. Corresponding logical values "Kn2" to "Knh" are input. Each bit indicating a logical value “Kn2” to “Knh” is connected to one input terminal of each AND gate 80, respectively. The delay data Dn from the shift register 10 is connected to the other input terminal of each AND gate 80. With such a configuration, when the delay data Dn has the logical value “0”, zero is output as the output data. When the delay data Dn has the logical value “1”, the coefficient value “2 × kn” is output as the output data.
[0048]
FIG. 3B shows an example in which transfer gates 81 and 82 capable of controlling signal transmission are used, and the switch 11n is shown as a representative. When the delay data Dn has the logical value "0", the output of the inverter 83, which is an inverting circuit, has the logical value "1", and each transfer gate 81 is turned on. Thus, when the delay data Dn has the logical value “0”, zero is output as the output data. Conversely, when the delay data Dn has the logical value "1", each transfer gate 82 is turned ON. Thus, when the delay data Dn has the logical value “1”, the coefficient value “2 × kn” is output as the output data.
[0049]
In the configuration described with reference to FIGS. 1 and 2, the output data from the output terminal 31 has the same sampling rate as the clock rate of the clock terminal 32. By thinning out at a fixed rate, a desired sampling rate output can be obtained. As a specific example, when 1-bit input audio data with a sampling rate of 3.072 MHz is used, for example, 16-bit audio output data with a sampling rate of 3.072 MHz is obtained from the output terminal 31. By taking in the data once every 64 times for this audio output data, 16-bit PCM audio data with a sampling rate of 48 KHz can be obtained.
[0050]
(Embodiment 2)
FIG. 4 is a block diagram illustrating an example of a configuration of a digital filter according to Embodiment 2 of the present invention. Compared with the digital filter according to the first embodiment, the digital filter according to the second embodiment can input each coefficient data from the outside, and each input coefficient data is set in each coefficient register. It is also supplied to an accumulator to be described and is cumulatively added. That is, in the first embodiment, each filter coefficient for determining a filter characteristic is stored in each register as a fixed coefficient value, whereas in the second embodiment, each filter coefficient can be arbitrarily set. And an arbitrary filter characteristic is obtained. With such a configuration, for example, even when a signal is deteriorated due to a time-varying transmission path characteristic, a digital filter that adaptively sets a filter coefficient that takes into account characteristics to correct the deterioration is used. Can be used as a filter. Although the second embodiment is based on the configuration described in FIG. 2 in the first embodiment and describes an improved example thereof, the present embodiment can also be applied to the configuration described in FIG. . In FIG. 4, components denoted by the same reference numerals as those in FIG. 2 have the same functions, and description thereof will be omitted.
[0051]
In FIG. 4, a coefficient input terminal 33 is an input terminal to which coefficient data K1 to Kn having coefficient values “k1” to “kn” corresponding to respective filter coefficients k1 to kn of the present digital filter are supplied. The coefficient registers 411 to 41n are registers for storing predetermined coefficient data K1 to Kn in the present digital filter. The coefficient data K1 to Kn sequentially supplied to the coefficient input terminal 33 are respectively transferred to predetermined coefficient registers 411 to 41n, and the coefficient data of predetermined coefficient values “k1” to “kn” are stored in the coefficient registers 411 to 41n. K1 to Kn are stored. The accumulator 40 has a function of sequentially accumulating the supplied data. That is, the coefficient data K1 to Kn supplied to the coefficient input terminal 33 are also transferred to the accumulator 40, and the accumulator 40 accumulates the sequentially transferred coefficient data K1 to Kn. With the digital filter according to the second embodiment having such a configuration, coefficient data corresponding to an arbitrary filter coefficient can be set, and by having such a function, an arbitrary filter characteristic can be set. Can be. In addition, by having such a function, for example, the filter can be used as a digital filter that changes filter coefficients as needed and adaptively obtains optimum filter characteristics.
[0052]
Hereinafter, an operation of setting arbitrary coefficient data by the configuration shown in FIG. 4 will be described. First, when setting predetermined filter coefficients k1 to kn, coefficient data K1 to Kn having coefficient values “k1” to “kn” corresponding to the respective filter coefficients k1 to kn are input to the coefficient input terminal 33, for example, K1, K2, and K3 are sequentially supplied to Kn. Thus, the coefficient data K1 to Kn sequentially supplied to the coefficient input terminal 33 are transferred to the corresponding coefficient registers 411 to 41n and also transferred to the accumulator 40. That is, coefficient data K1 to Kn corresponding to each of the coefficient registers 411 to 41n are stored in the coefficient register 411 in the order of a predetermined coefficient value “k1” and the coefficient register 412 in a predetermined coefficient value “k2”. . Along with such an operation, the coefficient data is transferred to the accumulator 40 up to Kn in the order of K1, K2, and K3, and the transferred coefficient data is converted into K1, K2, and K3 by the accumulative addition function of the accumulator 40. Are sequentially accumulated up to Kn. In this way, the accumulator 40 is finally set with the coefficient sum value “」 kn ”that is the value“ k1 + k2 + k3 +... + Kn ”obtained by adding the respective coefficient values“ k1 ”to“ kn ”of the respective coefficient data K1 to Kn. Is done. That is, the same sum data SKn as the sum register 20 in FIG. 2 is set in the accumulator 40, and the accumulator 40 outputs the sum data SKn having the coefficient sum value “Σkn”. According to such an operation, predetermined coefficient data K1 to Kn are set in coefficient registers 411 to 41n, and total sum data SKn obtained by accumulatively adding each coefficient value “k1” to “kn” is set in accumulator 40. When the same filter coefficient as that of the first embodiment is set, a digital filter having the same characteristics as the first embodiment can be realized. Further, with such a configuration, a digital filter whose arbitrary filter characteristics can be set can be realized. In particular, since the coefficient sum value “Σkn” is obtained by accumulative addition by the accumulator 40 in parallel with the setting of each of the coefficient data K1 to Kn, the coefficient sum value is separately calculated every time the filter coefficient is changed. It is not necessary to perform this operation, and the processing for this operation can be reduced.
[0053]
FIGS. 5 and 6 are different from the configuration shown in FIG. 4 described above. However, similarly to the configuration shown in FIG. 4, each coefficient data K1 to Kn input from the outside is stored in each register. FIG. 14 is a block diagram showing another configuration example having a function set to the function.
[0054]
In FIG. 5, the coefficient data K1 to Kn supplied to the coefficient input terminal 33 are transferred to predetermined coefficient registers 411 to 41n, respectively, as in the configuration described in FIG. Coefficient data K1 to Kn are stored. Further, the shift register 50 has a set input for controlling the output of the shift register 50 to be all “1” as compared with the shift register 10 described in FIG. The set input of the shift register 50 is connected to a set input terminal 34 to which an external set command signal is supplied. Further, in the configuration of FIG. 5, instead of the accumulator 40 described in FIG. 4, a sum register 20 is provided as in the configuration described in FIG.
[0055]
That is, when the set command signal is input to the set input terminal 34, all the delay data D1 to Dn from the shift register 50 are output as the value “1”. Therefore, the switches 111 to 11n all select the coefficient register side. Therefore, the output of the adder circuit 12 outputs a value “k1 + k2 + k3 +... + Kn” obtained by adding the respective coefficient values “k1” to “kn”, that is, a coefficient sum value “$ kn”. The sum register 20 captures the coefficient sum value “Σkn” at an appropriate timing, so that the sum register 20 stores the sum data SKn having the coefficient sum value “Σkn” in the same manner as the accumulator 40 shown in FIG. Is set. As described above, the shift register 50 is set at a predetermined timing, and the output of the adder circuit 12 is taken into the sum register 20 at an appropriate timing corresponding to this timing, thereby realizing the same function as the configuration shown in FIG. it can. In addition, as compared with the configuration of FIG. 4, the sum register 20 having a smaller circuit size than the accumulator 40 may be provided, so that the circuit size can be reduced.
[0056]
6, the coefficient data K1 to Kn supplied to the coefficient input terminal 33 are transferred to predetermined coefficient registers 411 to 41n, respectively, as in the configuration described with reference to FIG. Predetermined coefficient data K1 to Kn are stored. Further, the configuration of FIG. 6 is characterized in that switches 421 to 42n as first selection circuits are provided as compared with FIG. Control inputs of the switches 421 to 42n are connected to a coefficient load input terminal 35 to which a coefficient load command signal as a first selection control signal is supplied. Further, delay data D1 to Dn from the shift register 10 are respectively connected to one input of the switches 421 to 42n, and data of a value “1” as one of binary input values is connected to the other input. Is set. In addition, the configuration of FIG. 6 includes a sum register 20 in place of the accumulator 40 described in FIG. 4, similarly to the configurations described in FIGS.
[0057]
That is, when the coefficient load command signal input to the coefficient load input terminal 35 is valid, the switches 421 to 42n all select “1”. Therefore, the switches 111 to 11n as the second selection circuits all select the coefficient register side. Therefore, as in the case of FIG. 5, a value “k1 + k2 + k3 +... + Kn” obtained by adding the respective coefficient values is output to the output of the adding circuit 12. The sum register 20 takes in the value obtained by adding the respective coefficient values at an appropriate timing, so that the sum value of the respective coefficient values “k1 + k2 + k3 +...” Is stored in the sum register 20 similarly to the accumulator 40 shown in FIG. + Kn ”, that is, the sum total data SKn having the coefficient sum value“ $ kn ”is set. As described above, by inputting the coefficient load signal at a predetermined timing and taking in the output of the adder circuit 12 into the sum register 20 at an appropriate timing corresponding to this timing, the same function as the configuration shown in FIG. it can.
[0058]
7 and 8 are based on the configuration described with reference to FIG. 1, and are similar to the configurations shown in FIGS. 5 and 6, in which each coefficient data input from the outside is set in each register. FIG. 16 is a block diagram showing another configuration example having the following.
[0059]
The configuration in FIG. 7 is based on the configuration in FIG. 1 and uses a shift register 50 having a set input for controlling the outputs described in FIG. 5 to output all “1”. In the coefficient registers 411 to 41n, coefficient values “2xk1” to “2xkn” corresponding to twice the filter coefficients are set as coefficient data K1 to Kn from the coefficient input terminal 33. When the set command signal is input to the set input terminal 34, the delay data D1 to Dn from the shift register 50 all output the value "1", and the switches 111 to 11n all select the coefficient register side. Therefore, the output of the addition circuit 12 outputs a value twice as large as the value “k1 + k2 + k3 +... + Kn” obtained by adding the respective coefficient values, that is, a value twice as large as the total coefficient value “$ kn”. The summation register 20 first multiplies a value twice as large as the coefficient summation value "$ kn" by a multiplier 41 for multiplying a constant "1/2", and captures the multiplication result at an appropriate timing. Similarly to the sum register 20 shown in FIG. 1, the sum data SKn having the coefficient sum value “Σkn” is set. As described above, the same functions as those of the configuration shown in FIG. 4 can be realized by the configuration shown in FIG.
[0060]
The configuration in FIG. 8 is based on the configuration in FIG. 1 and includes switches 421 to 42n as first selection circuits, as in FIG. In the coefficient registers 411 to 41n, coefficient values “2xk1” to “2xkn” corresponding to twice the filter coefficients are set as coefficient data K1 to Kn from the coefficient input terminal 33. When a coefficient load command signal as a first selection control signal is input to the coefficient load input terminal 35, the switches 421 to 42n all select the value “1”, and the switches 111 to 42 as the second selection circuit. 11n all select the coefficient register side. Therefore, the output of the adder circuit 12 outputs a value twice as large as the value “k1 + k2 + k3 +... + Kn” obtained by adding the respective coefficient values, that is, a value twice as large as the total coefficient value “$ kn”. The summation register 20 first multiplies a value twice as large as the coefficient summation value "$ kn" by a multiplier 41 for multiplying a constant "1/2", and captures the multiplication result at an appropriate timing. Similarly to the sum register 20 shown in FIG. 1, the sum data SKn having the coefficient sum value “Σkn” is set. In this way, the same function as the configuration shown in FIG. 4 can be realized by the configuration shown in FIG.
[0061]
【The invention's effect】
As described above, according to the digital filter of the present invention, it is possible to suppress an increase in the scale of a circuit constituting the digital filter and obtain accurate output data.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a digital filter according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a modification of the configuration of the digital filter according to the first embodiment of the present invention;
FIG. 3A is a diagram showing an example in which switches 111 to 11n of FIG. 1 are configured using an AND gate;
(B) A diagram showing an example in which the switches 111 to 11n in FIG. 1 are configured using transfer gates.
FIG. 4 is a block diagram showing a configuration of a digital filter according to a second embodiment of the present invention.
FIG. 5 is a block diagram showing a modification of the configuration of the digital filter according to the second embodiment of the present invention;
FIG. 6 is a block diagram showing another modification of the configuration of the digital filter according to the second embodiment of the present invention;
FIG. 7 is a block diagram showing another modification of the configuration of the digital filter according to the second embodiment of the present invention;
FIG. 8 is a block diagram showing another modification of the configuration of the digital filter according to the second embodiment of the present invention;
FIG. 9 is a block diagram showing a configuration of a digital filter in a conventional example.
[Explanation of symbols]
10,50 shift register
12 Addition circuit
20 sum register
22 Subtractor
23 (2x) multiplier
30 input terminals
31 Output terminal
32 clock terminal
33 Coefficient input terminal
34 set input terminal
35 Coefficient load input terminal
40 accumulator
41 (1/2) Multiplier
80 AND gate
81, 82 transfer gate
83 inverter
100 FIR digital filter
111-11n, 421-42n switch
191-19n, 211-21n, 411-41n Coefficient register
200 offset correction unit

Claims (18)

A shift register for storing input data represented by one bit while shifting the data by a plurality of stages;
A plurality of coefficient registers each storing coefficient data corresponding to a filter coefficient for determining a transfer characteristic of the filter;
Based on the delay data in each stage of the shift register, when the delay data has one value, the value of the coefficient data of the coefficient register corresponding to that stage is selected, and when the delay data has the other value, zero is selected. A plurality of selection circuits for selecting the values of
An addition circuit that adds each selection data from the plurality of selection circuits and outputs an addition result as addition data;
A sum register for storing sum data corresponding to the sum of the filter coefficients;
A subtractor that subtracts the sum data from the addition data and outputs the subtraction result as output data,
The respective coefficient registers store a coefficient value that is twice the filter coefficient as coefficient data,
A digital filter, wherein the sum register stores a coefficient sum value, which is a sum value of the filter coefficients, as sum data. A shift register for storing input data represented by one bit while shifting the data by a plurality of stages;
A plurality of coefficient registers each storing coefficient data corresponding to a filter coefficient for determining a transfer characteristic of the filter;
Based on the delay data in each stage of the shift register, when the delay data has one value, the value of the coefficient data of the coefficient register corresponding to that stage is selected, and when the delay data has the other value, zero is selected. A plurality of selection circuits for selecting the values of
An addition circuit that adds each selection data from the plurality of selection circuits and outputs an addition result as addition data;
A multiplier for doubling the addition data and outputting the doubled addition data as multiplication data;
A sum register for storing sum data corresponding to the sum of the filter coefficients;
A subtractor that subtracts the sum data from the multiplied data and outputs a subtraction result as output data;
The respective coefficient registers store a coefficient value that is a value of the filter coefficient as coefficient data,
A digital filter, wherein the sum register stores a coefficient sum value, which is a sum value of the filter coefficients, as sum data. An FIR type digital filter unit that weights and adds the delay data obtained by delaying the input data expressed in binary in the order of input using filter coefficients corresponding to the respective delays and outputs the weighted addition result as addition data;
A digital filter, comprising: an offset correction unit that subtracts, from the addition data of the FIR digital filter unit, total data that is one half of the total sum of the filter coefficients. Weighted addition is performed on each delay data obtained by delaying input data expressed in binary in the order of input by using filter coefficients corresponding to each delay, and the weighted addition is reduced to 1 / M (M is a constant other than 0). An FIR type digital filter unit for outputting corresponding addition data,
An offset correction unit for subtracting, from the addition data of the FIR digital filter unit, total data which is 1 / 2M of the total of the filter coefficients (2M is a constant twice as large as M). And a digital filter. A shift register for storing input data represented by binary values while shifting the data by a plurality of stages;
A plurality of coefficient registers for storing a plurality of filter coefficients;
Based on the delay data in each stage of the shift register, when the delay data has one value, the value of the filter coefficient of the coefficient register corresponding to that stage is selected, and when the delay data has the other value, zero. A plurality of selection circuits for selecting the values of
An addition circuit that adds each selection data from the plurality of selection circuits and outputs an addition result as addition data;
A sum register for storing a half value of the sum of the filter coefficients stored in the plurality of coefficient registers as sum data;
A digital filter, comprising: a subtractor that subtracts the sum data from the added data and outputs a result of the subtraction as output data. A shift register for storing input data represented by binary values while shifting the data by a plurality of stages;
A plurality of coefficient registers for storing a plurality of filter coefficients;
Based on the delay data in each stage of the shift register, when the delay data has one value, the value of the filter coefficient of the coefficient register corresponding to that stage is selected, and when the delay data has the other value, zero. A plurality of selection circuits for selecting the values of
An addition circuit for adding each selection data from the plurality of selection circuits and outputting a value corresponding to 1 / M (M is a constant other than 0) of the addition result as addition data;
A sum register that stores a value of 1 / 2M (2M is a constant twice the M) of the sum of the filter coefficients stored in the plurality of coefficient registers as sum data;
A digital filter, comprising: a subtractor that subtracts the sum data from the added data and outputs a result of the subtraction as output data. 7. The method according to claim 4, wherein M in said 1 / M and 1 in 2M is a power of 2 (a is an integer), and is performed by bit shifting each data. Digital filter. The digital filter according to claim 3, wherein the input data represented by the binary is input data represented by one bit. An input terminal for inputting input data,
A coefficient input terminal for inputting a plurality of filter coefficients,
A shift register for storing input data represented by 1 bit supplied to the input terminal while shifting the data by a plurality of stages;
A plurality of coefficient registers each storing the plurality of filter coefficients supplied to the coefficient input terminal,
Based on the delay data in each stage of the shift register, when the delay data has one value, the value of the filter coefficient of the coefficient register corresponding to that stage is selected, and when the delay data has the other value, zero. A plurality of selection circuits for selecting the values of
An addition circuit that adds each selection data from the plurality of selection circuits and outputs a value corresponding to the addition result as addition data;
An accumulator that cumulatively adds the plurality of filter coefficients supplied to the coefficient input terminal by the plurality, and outputs a value corresponding to a result of the cumulative addition as total data;
A subtractor that subtracts the sum data from the addition data and outputs the subtraction result as output data;
An output terminal for outputting the output data. The addition circuit adds the selected data and outputs a value corresponding to 1 / M (M is a constant other than 0) of the addition result as addition data,
The accumulator accumulates the supplied plurality of filter coefficients by the number of accumulators, and sets a value of 1 / 2M (2M is a constant of twice the M) of a result of the accumulative addition as total data. 10. The digital filter according to claim 9, wherein the digital filter outputs. The addition circuit adds the selected data and outputs a value corresponding to 1 / M (M is a constant other than 0) of the addition result as addition data,
The accumulator accumulatively adds a value of 1 / 2M (2M is a constant twice the M) of the supplied plurality of filter coefficients for the plurality of filter coefficients, and sums a value of a result of the accumulative addition. The digital filter according to claim 9, wherein the digital filter outputs data. An input terminal for inputting input data,
A coefficient input terminal for inputting a plurality of filter coefficients,
A shift register for storing input data represented by 1 bit supplied to the input terminal while shifting the data by a plurality of stages;
A plurality of coefficient registers each storing the plurality of filter coefficients supplied to the coefficient input terminal,
Based on the delay data in each stage of the shift register, when the delay data has one value, the value of the filter coefficient of the coefficient register corresponding to that stage is selected, and when the delay data has the other value, zero. A plurality of selection circuits for selecting the values of
An addition circuit that adds each selection data from the plurality of selection circuits and outputs a value corresponding to the addition result as addition data;
A sum register for fetching the addition data from the addition circuit at a predetermined timing, storing the sum data, and outputting a value corresponding to the fetched addition data as sum data;
A subtractor that subtracts the sum data from the addition data and outputs the subtraction result as output data;
An output terminal for outputting the output data,
The shift register has a set input that outputs the one value from all stages that output the delayed data when a set command signal is input,
The digital filter, wherein the sum register takes in the addition data in accordance with a timing at which the set command signal is input to a set input of the shift register. The addition circuit adds the selected data and outputs a value corresponding to 1 / M (M is a constant other than 0) of the addition result as addition data,
13. The digital filter according to claim 12, wherein the sum register outputs a value of 1/2 M (2M is a constant twice as large as M) of the added data fetched at the predetermined timing as sum data. . An input terminal for inputting input data,
A coefficient input terminal for inputting a plurality of filter coefficients,
A shift register for storing input data represented by one bit supplied to the input terminal and having one or the other value while shifting the data by a plurality of stages;
A first selection control signal for selection control is input, and when the first selection control signal is invalid based on the first selection control signal, the value of the delay data of the shift register corresponding to that stage And when the first selection control signal is valid, a plurality of first selection circuits for selecting one of the values and outputting the selected value as a second selection control signal,
A plurality of coefficient registers each storing the plurality of filter coefficients supplied to the coefficient input terminal,
When the second selection control signal has one value based on the second selection control signal, the value of the filter coefficient of the coefficient register corresponding to that stage is selected, and the second selection control signal is set to the other value. A plurality of second selection circuits for selecting a value of zero and outputting the selected value as selection data,
An addition circuit that adds each selected data from the plurality of second selection circuits and outputs a value corresponding to the addition result as addition data;
A sum register for fetching the addition data from the addition circuit at a predetermined timing, storing the sum data, and outputting a value corresponding to the fetched addition data as sum data;
A subtractor that subtracts the sum data from the addition data and outputs the subtraction result as output data;
An output terminal for outputting the output data,
The digital filter according to claim 1, wherein the sum register takes in the addition data in accordance with a timing at which the first selection control signal becomes valid. The addition circuit adds the selected data and outputs a value corresponding to 1 / M (M is a constant other than 0) of the addition result as addition data,
15. The digital filter according to claim 14, wherein the sum register outputs a value of 1 / 2M (2M is a constant twice as large as M) of the added data acquired at the predetermined timing as the sum data. . An input terminal for inputting input data,
A coefficient input terminal for inputting a plurality of filter coefficients for determining a transfer characteristic of the filter,
A shift register for storing input data represented by 1 bit supplied to the input terminal while shifting the data by a plurality of stages;
A plurality of coefficient registers each storing a coefficient value that is twice the value of the plurality of filter coefficients supplied to the coefficient input terminal as coefficient data,
Based on the delay data in each stage of the shift register, when the delay data has one value, the value of the coefficient data of the coefficient register corresponding to that stage is selected, and when the delay data has the other value, zero is selected. A plurality of selection circuits for selecting the values of
An addition circuit that adds each selection data from the plurality of selection circuits and outputs an addition result as addition data;
A sum register that captures and stores a half value of the addition data from the addition circuit at a predetermined timing, and outputs the value of the captured addition data as total data;
A subtractor that subtracts the sum data from the addition data and outputs the subtraction result as output data,
The shift register has a set input that outputs the one value from all stages that output the delayed data when a set command signal is input,
A digital filter, wherein the sum register takes in a half value of the added data in accordance with a timing at which a set command signal is input to a set input of the shift register. An input terminal for inputting input data,
A coefficient input terminal for inputting a plurality of filter coefficients for determining a transfer characteristic of the filter,
A shift register for storing input data represented by one bit supplied to the input terminal and having one or the other value while shifting the data by a plurality of stages;
A first selection control signal for selection control is input, and when the first selection control signal is invalid based on the first selection control signal, the value of the delay data of the shift register corresponding to that stage And when the first selection control signal is valid, a plurality of first selection circuits for selecting one of the values and outputting the selected value as a second selection control signal,
A plurality of coefficient registers each storing a coefficient value that is twice the value of the plurality of filter coefficients supplied to the coefficient input terminal as coefficient data,
When the second selection control signal has one value based on the second selection control signal, the value of the coefficient register corresponding to the stage is selected, and the second selection control signal is set to the other value. Sometimes, a plurality of second selection circuits that select a value of zero and output the selected value as selection data,
An addition circuit that adds the respective selection data from the plurality of second selection circuits and outputs an addition result as addition data;
A sum register that captures and stores a half value of the addition data from the addition circuit at a predetermined timing, and outputs the value of the captured addition data as total data;
A subtractor that subtracts the sum data from the addition data and outputs the subtraction result as output data,
A digital filter, wherein the sum register takes in a half value of the added data in accordance with a timing at which the first selection control signal becomes valid. Weighted addition is performed on each delay data obtained by delaying input data expressed in binary in the order of input by using filter coefficients corresponding to each delay, and the weighted addition is reduced to 1 / M (M is a constant other than 0). Deriving the corresponding summation data;
Subtracting, from the added data, total data that is 1/2 M of the total of the filter coefficients (2M is a constant twice as large as M).

Images