JP2007129618A - alpha MULTIPLICATION CIRCUIT AND ARITHMETIC CIRCUIT OF GALOIS FIELD - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an α multiplication circuit and arithmetic circuit of Galois field capable of implementing a plurality of arithmetic functions. <P>SOLUTION: An arithmetic circuit of the Galois field comprises multiple steps of cascade connections of an α multiplication circuit 11 of the Galois filed for performing α multiplication or left rotating operation; a selector circuit 12 for outputting either a signal at one bit position of input signals or a register circuit output signal; an AND gate 13 for multiplying an output signal of the α multiplication circuit with a selector circuit output signal; an EOR gate 14 for adding a Galois field multiplication circuit output and an output of a previous step of the Galois filed adding circuit; and a register circuit 15 connected to the selector circuit. For example, the plurality of arithmetic functions require to implement a Reed-Solomon decoding circuit. A design is completed only by designing a cell of the arithmetic circuit, and attaching the cell as various kinds of functional circuits to wire. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a Galois field α multiplication circuit and an arithmetic circuit, and more particularly to a Galois field α multiplication circuit and an arithmetic circuit capable of realizing a plurality of arithmetic functions.

Conventionally, in order to realize a digital signal processing circuit such as a Reed-Solomon decoding circuit used in a digital communication device or the like, a multiplication circuit or the like on a Galois field is required. Patent Document 1 below discloses an example of a multiplication circuit on a Galois field. As a means for realizing such a circuit, it is conceivable to use an FPGA which is a programmable logic device. However, since the FPGA is intended for versatility, it has a problem that it cannot be used in a field that requires ultra-high speed processing because the wiring load is heavy on the circuit and the calculation speed is slow. Therefore, in the field that requires ultra-high-speed processing, conventionally, a hardware circuit is designed for each necessary function and is made into an LSI.
JP 11-96030 A

In order to realize a Reed-Solomon decoding circuit, for example, using the conventional individual hardware circuit as described above, in addition to the Galois field multiplication circuit, α ^ n (^ represents a power. Hereinafter, n is an integer. ) Functions such as calculation and inverse element calculation are also required, and there is a problem that the circuit scale of the Reed-Solomon decoding circuit is increased and the design is troublesome.
An object of the present invention is to provide a Galois field α multiplication circuit and an arithmetic circuit that can solve the above-described problems of the prior art and can realize a plurality of arithmetic functions.

The Galois field α multiplication circuit having a rotation function of the present invention has a parallel input terminal of a plurality of bits, a parallel output terminal of a plurality of bits, and a control signal input terminal, and the output of the least significant bit regardless of the control signal A signal of the input terminal of the most significant bit is output to the terminal, and a logical product signal of the control signal corresponding to the bit position and the signal of the most significant bit input terminal is output to the output terminal other than the least significant bit. The main feature is that an exclusive OR signal with the signal at the input terminal at the bit position one lower than the bit position is output.
In addition, the Galois field α multiplication circuit having the rotation function is characterized in that a control signal corresponding to a desired generator polynomial is input to the control signal input terminal.

  In the Galois field α multiplication circuit having the rotation function, the bit width is 8 bits from bit 0 to bit 7, and the signal of the bit 7 input terminal is connected to the bit 0 output terminal regardless of the control signal. The bit 0 output terminal signal is output to the bit 1 output terminal, the bit 4 input terminal signal is output to the bit 5 output terminal, and the bit 5 input terminal signal is output to the bit 6 output terminal. Then, the signal of the bit 6 input terminal is output to the bit 7 output terminal, and the control signal corresponding to the bit position and the signal of the bit 7 input terminal are output to the output terminals other than bits 1, 5, 6, and 7. Is also characterized in that an exclusive logical sum signal of the logical product signal and the signal at the input terminal at the bit position one lower than the bit position is output.

  The Galois field arithmetic circuit according to the present invention receives the output signal from the preceding α multiplication circuit, performs α multiplication or left 1-bit rotation processing based on the control signal, and the control signal. And a selector circuit that selects and outputs either a signal at one bit position of the input signal or an output signal from the register circuit, and an AND gate that multiplies the output signal of the α multiplier circuit and the output signal of the selector circuit And an arithmetic circuit comprising an EOR gate for adding the output of the AND gate and the output of the EOR gate in the previous stage and a register circuit connected to one input of the selector circuit is cascaded. Features.

In the Galois field arithmetic circuit, the α multiplication circuit is also a Galois field α multiplication circuit having a rotation function.
In addition, in the Galois field arithmetic circuit, by applying a control signal to the α multiplier circuit and the selector circuit, the arithmetic circuit can be a vector multiplier circuit corresponding to an arbitrary generator polynomial or an exponential operation corresponding to an arbitrary power. Another feature is that it functions as a circuit.
The Galois field arithmetic circuit further includes a second AND gate circuit in which the output signal of the register circuit is connected to one input terminal and the output is connected to the input terminal of the register circuit in the previous stage. There is also a feature.

If the cell of the arithmetic circuit according to the present invention is designed, the design is completed simply by pasting and wiring the cells as a plurality of types of functional circuits, so that the design is facilitated and the period can be shortened.
The arithmetic circuit on the Galois field of the present invention can realize a plurality of arithmetic functions such as a vector multiplication circuit corresponding to an arbitrary generator polynomial or an exponential arithmetic circuit corresponding to an arbitrary power. Further, by dynamically switching the functions, it is possible to realize a plurality of arithmetic functions necessary for realizing, for example, a Reed-Solomon decoding circuit with the same circuit, so that the circuit scale can be reduced. .

  Embodiments of the present invention will be described below in detail with reference to the drawings.

As an embodiment, an arithmetic circuit capable of realizing the following arithmetic circuit necessary for configuring a Reed-Solomon decoding circuit will be described. In order to construct a Reed-Solomon decoding circuit, the following Galois field arithmetic circuit is required.
(1) Galois field multiplication circuit and inverse element calculation used in Berlekamp-Massey algorithm (2) Input data 16th power calculation circuit used in inverse element calculation (3) Used in syndrome calculation and chain search α ^ n (n = 0,1… 7) multiplication circuit

  The arithmetic circuit on the Galois field of the first embodiment of the present invention will be described below. FIG. 1 is a block diagram showing a configuration of an arithmetic circuit on a Galois field (GF (256)) of the present invention. The arithmetic circuit includes an α multiplication circuit 11 having a left rotation function, a selector circuit 12, an AND gate 13 for performing multiplication of modulus (modulo) 2, an EOR gate 14 for performing addition in modulus (modulo) 2, and a register. A unit circuit comprising a circuit 15 and an AND gate 16 for controlling the shift register operation is a circuit in which eight stages are cascaded as shown in the figure. Note that the α multiplier circuit 11 does not exist in the first stage (the uppermost stage in FIG. 1), and is provided in the second and subsequent stages.

  The 8-bit parallel signal a input from one signal input terminal is input to the first-stage AND gate 13 and also input to the second-stage α multiplier circuit 11 (details will be described later). In the case of GF (256), since the input signal is 8 bits, there are 8 AND gates 13. The input signal a is input to one input terminal of the eight AND gate circuits 13, and the 8-bit output signal of the selector circuit 12 is input to the other input terminal.

  When the selector control signal mat_mal_set is 1, the selector circuit 12 outputs 1 bit (for example, b0) of the 8-bit parallel signal b input from the other signal input terminal to all the bits, and the selector control signal When mat_mal_set is 0, the 8-bit output signal of the register 15 is output.

  In the case of GF (256), since the input signal is 8 bits, the EOR gate 14 is composed of 8 pieces. The input signal s is input to one input terminal of the eight EOR gate circuits in the first stage, and the 8-bit output signal of the AND gate 13 is input to the other input terminal. The output of the EOR gate 14 is input to the next-stage EOR gate. The output of the α multiplier circuit 11 is input to the AND gate 13 and also input to the α multiplier circuit 11 at the next stage.

  The register circuit 15 is an 8-bit parallel input / output register. The 8-bit parallel output signal of each register circuit is input to the preceding register circuit via an AND gate 16 that controls the shift register operation. Therefore, by setting the control signal int to 1, the plurality of register circuits 15 can function as shift registers that shift in units of 8-bit parallel signals.

  FIG. 2 is a circuit diagram showing the configuration of the Galois field α multiplication circuit 11 of the present invention. The α multiplication circuit 11 shown in FIG. 2A is provided with one buffer circuit 30, seven AND gate circuits 31, and seven EOR gate circuits that output an input signal as it is so as to correspond to a plurality of generator polynomials. 32 are connected as shown. Therefore, when the control signals ctl_n are all 0, it functions as a left 1-bit rotation circuit, and otherwise it functions as a Galois field α multiplication circuit for an arbitrary generator polynomial based on the state of the control signal ctl_n.

  The circuit of FIG. 2B is specialized only when the generator polynomial is x ^ 8 + x ^ 4 + x ^ 3 + x ^ 2 + 1. When the generator polynomial is specialized to the above equation, as shown in FIG. 2B, five buffer circuits 30, three AND gate circuits 31, and three EOR gates that output the input signal as they are The circuit 32 is connected as shown. Therefore, when the control signal ctl_n is 0, it functions as a left 1-bit rotation circuit, and when the control signal ctl_n is 1, it functions as a Galois field α multiplication circuit for the generator polynomial.

  That is, when the control signal ctl_n is 0, the outputs ao [0] = a [7], ao [1] = a [0], ao [2] = a [1], ao [3] = a [2 ], Ao [4] = a [3], ao [5] = a [4], ao [6] = a [5], ao [7] = a [6]. When the control signal ctl_n is 1, the outputs ao [0] = a [7], ao [1] = a [0], ao [2] = a [1] + a [7], ao [3] = A [2] + a [7], ao [4] = a [3] + a [7], ao [5] = a [4], ao [6] = a [5], ao [7] = a [6] This output signal is the result of α multiplication for the generator polynomial x ^ 8 + x ^ 4 + x ^ 3 + x ^ 2 + 1. Note that “+” is addition in modulus 2, that is, exclusive OR.

  Here, the α multiplication circuit will be described. Let the primitive element of the Galois field GF (256) be α and the generator polynomial F (x) be F (x) = X ^ 8 + X ^ 4 + X ^ 3 + X ^ 2 + 1 (Formula 1).

An arbitrary element a of GF (256) is expressed by the following equation.
a = a7α ^ 7 + a6α ^ 6 + a5α ^ 5 + a4α ^ 4 + a3α ^ 3 + a2α ^ 2 + a1α + a0 (Formula 2)
Multiplying equation 2 by α,
a × α ＝ a7α ^ 8 + a6α ^ 7 + a5α ^ 6 + a4α ^ 5 + a3α ^ 4 + a2α ^ 3 + a1α ^ 2 + α0α (Formula 3)
It becomes. On the other hand, since α is a primitive element, F (α) = 0, and as a result,
α ^ 8 = α ^ 4 + α ^ 3 + α ^ 2 + 1 (Formula 4)
It becomes.

Substituting Equation 4 into Equation 3,
a × α ＝ a6α ^ 7 + a5α ^ 6 + a4α ^ 5 + (a3 + a7) α ^ 4 + (a2 + a7) α ^ 3 + (a1 + a7) α ^ 2 + a0α + a7 (Formula 5)
It becomes. In the α multiplier circuit 11 shown in FIG. 2B, when the control signal ctl_n is 1, when the coefficients a0 to a7 shown in the above equation 2 are input, the coefficient of the above equation 5 is obtained as the output ao.
As for an arbitrary generator polynomial, an expression corresponding to the above expression (5) is obtained in the same manner as described above, and the coefficient of this expression is set as the control signal ctl_n [0..6]. An α multiplier circuit corresponding to the generator polynomial is obtained.

  FIG. 4 is a block diagram when a vector multiplication circuit is configured using the arithmetic circuit of the present invention. Here, the vector multiplication circuit will be described first. Let α be the primitive element of the Galois field GF (256). Further, arbitrary elements a and b of GF (256) are expressed by the following equations.

a = a7α ^ 7 + a6α ^ 6 + a5α ^ 5 + a4α ^ 4 + a3α ^ 3 + a2α ^ 2 + a1α + a0 (Formula 6)
b = b7α ^ 7 + b6α ^ 6 + b5α ^ 5 + b4α ^ 4 + b3α ^ 3 + b2α ^ 2 + b1α + b0 (Formula 7)

At this time, the product of a and b is
a × b = a × (b7α ^ 7 + b6α ^ 6 + b5α ^ 5 + b4α ^ 4 + b3α ^ 3 + b2α ^ 2 + b1α + b0)
= B7a × α ^ 7 + b6a × α ^ 6 + b5a × α ^ 5 + b4a × α ^ 4 + b3a × α ^ 3 + b2a × α ^ 2 + b1a × α + b0a (Formula 8)
It becomes.

  The circuit of FIG. 4 is a circuit for executing the calculation of the above equation 8. In the circuit of FIG. 1, the α multiplication circuit of FIG. 2B is used, the control signal ctl_n is set to 1, and the selector control signal mat_mal_set is set to A circuit in the case of 1 is shown.

  The input signal a is input to the AND gate 13 and also to the α multiplier circuit 11, and the output of the α multiplier circuit at each stage is input to the AND gate 13 at each stage and the α multiplier circuit 11 at the next stage. Therefore, a × α ^ n (n = 0,... 7) is input to one input of the AND gate 13 at each stage. Further, bn (n = 0,... 7) is input to the other input of the AND gate 13 at each stage. The outputs of the AND gates 13 are all added by the EOR gate 14, and the product of a and b is output as the output signal s_o.

  In the configuration of FIG. 4, the register circuit 15 is not used as a vector multiplying circuit because it is not necessary. Therefore, when the control signal int is set to 1, all the registers are connected in series for each bit, and can function as a shift register. Therefore, by sequentially inputting and shifting 8-bit data set in each register from the data input terminal m_i during the vector multiplication operation, desired values can be set and stored in all the registers 15. Using this function, for example, by inputting a multiplication operation result to the shift register, the multiplication operation result can be temporarily stored.

  FIG. 5 is a block diagram when an exponent multiplication circuit is configured using the arithmetic circuit of the present invention. The exponent operation circuit, in particular, the 16th power operation of input data is an operation circuit required for calculating the inverse element of GF (256).

The primitive element of GF (256) is represented by α, and an arbitrary element a of GF (256) is represented by the following expression.
a = a7α ^ 7 + a6α ^ 6 + a5α ^ 5 + a4α ^ 4 + a3α ^ 3 + a2α ^ 2 + a1α + a0 (Formula 9)
Since an is an element of GF (2), an ^ 2 = an, and 2 * aman = 0.

Therefore, a ^ 2 is
a ^ 2 ＝ a7α ^ 14 + a6α ^ 12 + a5α ^ 10 + a4α ^ 8 + a3α ^ 6 + a2α ^ 4 + a1α ^ 2 + a0 (Formula 10)
It becomes. Similarly, a ^ 16 is
a ^ 16 = a7α ^ 112 + a6α ^ 96 + a5α ^ 80 + a4α ^ 64 + a3α ^ 48 + a2α ^ 32 + a1α ^ 16 + a0 (Formula 10)
It becomes. When this is represented by a matrix, the following Expression 11 is obtained.

  The circuit of FIG. 5 is a circuit for executing the calculation of the above formula 11. In the circuit of FIG. 1, the circuit when the control signal ctl_n is 0, the selector control signal mat_mal_set is 0, and the control signal int is 0 is shown. Show. In each register 15, mask data M0 to M7 are set in advance. In order to perform the operation of Expression 11 in the circuit of FIG. 5, it is necessary to generate mask data to be set in the register 15 from a matrix corresponding to the coefficient α.

  FIG. 6 is an explanatory diagram showing a method for generating mask data. A matrix corresponding to the coefficient α in the above equation 11 is shown in FIG. The numbers on the diagonal are surrounded by dotted lines. When each row (1 to 8 rows) of this matrix is rotated left by (number of rows minus 1) bits, the matrix of FIG. 6B is obtained. In (a), the numerical values surrounded by dotted lines are aligned in a vertical column. The data of each column of this matrix is set as mask data M0 to M7. Then, as shown in FIG. 5, M0 to M7 are set in the registers 7 to 0.

  The input data a is sequentially rotated left by bit by the left rotation circuit 11 connected in series, and is input to one of the AND gates 13 (AND gate circuits). Any one of the mask data M0 to M7 is input to the other input of the AND gate 13, and a logical product is taken. That is, only data corresponding to a bit whose mask data is 1 is output. The outputs of the AND gate 13 are all added (EOR) for each bit position by the EOR gate 14, and a ^ 16 is obtained as the output s_o.

  The α ^ n (n = 0, 1... 7) multiplication used in the syndrome calculation and the chain search can also be obtained by linear conversion of the input data a. Therefore, it can be calculated by the same method as the matrix operation described above.

  FIG. 3 is a block diagram showing a configuration of an inverse element arithmetic circuit using the arithmetic circuit on the Galois field of the present invention. When the inverse element calculation is performed using the conversion table, it is necessary to prepare 255 kinds of tables that are the number of elements of GF (256). In order to reduce the number of conversion tables, the inverse element arithmetic circuit is configured as shown in FIG.

  The input data a is raised to the 16th power by the exponent operation circuit 40, and further multiplied by the input data a by the Galois field multiplication circuit 41 to generate a ^ 17. The inverse element a ^ -17 of this a ^ 17 is obtained by referring to the conversion table 42. Finally, multiplication with the previous calculation result a ^ 16 is performed to obtain a ^ -1 which is an inverse element of a.

  In the embodiment, the Reed-Solomon code generator polynomial F (x) = X ^ 8 + X ^ 4 + X ^ 3 + X ^ 2 + 1 (Equation 1), and the order is 255 = 15 * 17. Therefore, the number of elements of the input signal element a ^ n (n = 0, 1,..., 255) to the 17th power, (a ^ n) ^ 17 = a ^ 17n (mod255) is 15, and the conversion table is 15 Just type.

  While the embodiments have been disclosed above, the following modifications are also possible. In the embodiment, the embodiment corresponding to the signal having 8 bits is disclosed. However, as the α multiplier circuit 11, the set of the AND gate and the EOR gate in FIG. If unit circuits corresponding to the number of bits are cascaded as one arithmetic circuit, the present invention can cope with any number of bits.

It is a block diagram which shows the structure of the arithmetic circuit on the Galois field of this invention. It is a circuit diagram which shows the structure of the alpha multiplication circuit 11 of this invention. It is a block diagram which shows the structure of the inverse element arithmetic circuit using the arithmetic circuit on the Galois field of this invention. It is a block diagram at the time of comprising a vector multiplication circuit using the arithmetic circuit of this invention. It is a block diagram at the time of comprising an exponent multiplication circuit using the arithmetic circuit of this invention. It is explanatory drawing which shows the production | generation method of mask data.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... (alpha) multiplication circuit 12 ... Selector circuit 13 ... AND gate 14 ... EOR gate 15 ... Register circuit 16 ... AND gate

Claims (7)

A multi-bit parallel input terminal, a multi-bit parallel output terminal and a control signal input terminal;
Regardless of the control signal, the signal of the input terminal of the most significant bit is output to the output terminal of the least significant bit,
The output terminal other than the least significant bit includes a logical product signal of the control signal corresponding to the bit position and the signal of the most significant bit input terminal, and the input terminal at the bit position one lower than the bit position. A Galois field α multiplication circuit having a rotation function, wherein an exclusive OR signal is output.   2. The Galois field α multiplier circuit according to claim 1, wherein a control signal corresponding to a desired generator polynomial is input to the control signal input terminal. The bit width is 8 bits from bit 0 to bit 7,
Regardless of the control signal, the signal of the bit 7 input terminal is output to the bit 0 output terminal,
Bit 1 output terminal outputs the signal of bit 0 input terminal,
The bit 4 input terminal signal is output to the bit 5 output terminal,
The bit 5 input terminal signal is output to the bit 6 output terminal,
The signal of the bit 6 input terminal is output to the bit 7 output terminal,
The output terminals other than bits 1, 5, 6, and 7 include a logical product signal of the control signal corresponding to the bit position and the signal of the bit 7 input terminal, and a bit position one lower than the bit position. 2. The Galois field α multiplication circuit having a rotation function according to claim 1, wherein an exclusive OR signal with the signal of the input terminal is output. An output signal from the α multiplier circuit in the previous stage, and a Galois α multiplier circuit that performs α multiplication or left 1-bit rotation processing based on the control signal;
A selector circuit that selects and outputs either a signal at one bit position of the input signal or an output signal from the register circuit based on the control signal;
An AND gate for multiplying the output signal of the α multiplier circuit and the output signal of the selector circuit;
An EOR gate for adding the output of the AND gate and the output of the preceding EOR gate;
A Galois field arithmetic circuit comprising a plurality of arithmetic circuits connected in cascade to a register circuit connected to one input of the selector circuit.   5. The Galois field arithmetic circuit according to claim 4, wherein the α multiplication circuit is the α multiplication circuit according to claim 1.   The control circuit is applied to the α multiplication circuit and the selector circuit, thereby causing the arithmetic circuit to function as a vector multiplication circuit corresponding to an arbitrary generator polynomial or an exponential arithmetic circuit corresponding to an arbitrary power. 5. A Galois field arithmetic circuit according to 4. 5. The circuit according to claim 4, further comprising a second AND gate circuit in which an output signal of the register circuit is connected to one input terminal, and an output is connected to an input terminal of the register circuit in the preceding stage. Arithmetic circuit of Galois field.

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