WO2017166026A1

WO2017166026A1 - Multiplier-accumulator, multiplier-accumulator array and digital filter

Info

Publication number: WO2017166026A1
Application number: PCT/CN2016/077530
Authority: WO
Inventors: 张科峰
Original assignee: 武汉芯泰科技有限公司
Priority date: 2016-03-28
Filing date: 2016-03-28
Publication date: 2017-10-05

Abstract

Disclosed are a multiplier-accumulator, a multiplier-accumulator array and a digital filter. The multiplier-accumulator comprises a multiplier converter for converting a multiplier to obtain a converted multiplier, wherein when the converted multiplier is expressed in binary, only one bit is 1 and the remaining bits are 0; a multiplier for multiplying the converted multiplier by a multiplicand to obtain a product; and an accumulator for adding the product to output an accumulation result of the product. By converting a multiplier of a multiplier-accumulator, when the multiplier-accumulator carries out multiplication, the multiplier needs only one bit of space, regardless of the number of bits of the multiplier and the multiplicand, and the multiplication can be completed in one clock cycle. The power consumption and area of a multiplier-accumulator are greatly reduced, while the speed is greatly increased.

Description

Title of Invention: A Multiplier Adder, Multiplier Adder Array, and Digital Filter

Technical field

[0001] The present invention relates to the field of digital filtering technologies, and in particular, to a multiplier, a multiplier array, and a digital filter.

Background technique

[0002] In the digital baseband technology of the existing mobile communication technology, digital filtering technology is an important technology. As is well known, the digital filtering process is mainly realized by the multiplication operation of the filter coefficient and the sampled data, and the accumulation operation. Therefore, the multiplier is a very core module of the digital filter, which often determines the speed and resource consumption of the digital filter (such as area, power consumption, etc.).

[0003] However, in the existing digital filter, the multiplier is operated based on the principle of precise calculation, and the filter coefficient is usually a very accurate number which changes with the change of the sampled data. However, the effect of the filter coefficients on the final filtering accuracy of the digital filter is a relative relationship and is not an absolute relationship. In this way, the use of accurate filter coefficient calculations will make the calculation of multiplication and addition, especially the multiplication calculation, very large, which leads to the defects of digital filter, such as slow speed, large power consumption and large area. Therefore, it is necessary to design a multiplier that can ensure the effective accuracy of the digital filter and simplify the multiplication calculation.

technical problem

[0004] In view of the defects in the prior art that the multiplier is computationally intensive and occupies a large amount of resources, the present invention provides a multiplier, a multiplier array and a multiplier that can greatly simplify multiplication calculation, reduce the area of the multiplier and power consumption, and Digital filter. Problem solution

Technical solution

[0005] The technical solution proposed by the present invention with respect to the above technical problems is as follows:

[0006] In one aspect, a multiplier is provided, including: a multiplier converter for converting a multiplier to obtain a converted multiplier, the converted multiplier being represented by a binary, only one The bit is 1 and the remaining bits are 0; a multiplier for multiplying the converted multiplier by the multiplicand to obtain a product; an accumulator for accumulating the product The cumulative result of the product. [0007] Preferably, the multiplier converter converts the multiplier, retains 1 of the binary highest bit of the multiplier, and sets the remaining bits to 0.

[0008] Preferably, the multiplier converter converts the multiplier, and the multiplier converter performs the following operations:

Obtaining two numbers 2^ and 2 closest to the multiplier according to the value of the multiplier, wherein the multiplier is in the range of 2 η~2 "+ι, n is an integer;

[0010] determining which of the 2 n and 2 ^ is closer to the multiplier, if it is closer to 2 ", the multiplier is converted to 2 ", otherwise the multiplier is converted to 2 ^.

[0011] In another aspect, there is also provided a multiplier array comprising at least two of the above multipliers.

[0012] Preferably, in the multiplier array, the multipliers are connected in series.

[0013] Preferably, in the multiplier array, the multipliers are connected in parallel.

In still another aspect, a digital filter is provided, including the above-described multiplier. .

Advantageous effects of the invention

Beneficial effect

[0015] Embodiments of the present invention have the following beneficial effects: By converting the multiplier of the multiplier, only one bit of the binary bit of the converted multiplier is 1, and the other bits are all 0. Thus, the multiplier is doing the multiplication operation. Regardless of the number of bits of the multiplier and the multiplicand, the multiplier only needs one bit of space, and one multiplication operation can be completed in one chirp cycle. The power consumption and area of the multiplier are greatly reduced, but the speed is greatly increased.

Brief description of the drawing

DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings to be used in the embodiments or the prior art description will be briefly described below, and obviously, in the following description The drawings are only some of the embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative work.

1 is a block diagram showing the structure of a multiplier of a first embodiment provided by the present invention;

2 is a schematic diagram of a multiplier conversion structure of a first embodiment provided by the present invention;

3 is a schematic diagram of a multiplier conversion structure of a first embodiment provided by the present invention; 4 is a schematic structural diagram of a multiplier array of a second embodiment provided by the present invention;

[0021] FIG. 5 is a schematic structural diagram of a multiplier array of a second embodiment provided by the present invention;

6 is a schematic structural diagram of a digital filter according to a third embodiment of the present invention;

7 is a flow chart of a multiplication and addition calculation method according to a fourth embodiment of the present invention.

Embodiments of the invention

[0024] The technical solutions in the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. example. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

[0025] Embodiment 1: Multiplier

The present embodiment provides a multiplier and adder. Referring to FIGS. 1 to 3, the multiplier 100 includes: a multiplier converter 11, a multiplier 12, and an accumulator 13.

The multiplier converter 11 is used to convert the multiplier A to obtain the converted multiplier A'. The converted multiplier A' is expressed in binary 吋, with only one bit being 1, and the remaining bits being 0.

[0028] The multiplier 12 is for multiplying the converted multiplier A' by the multiplicand X to obtain a product.

[0029] The accumulator 13 is for accumulating the product to output an accumulated result ¥.

[0030] In this embodiment, the multiplier A may include L (L is a natural number) number _ai , a ₂ ... a _L , and the multiplicand X may also include N numbers _{X l} , x ₂ ... x _N . The accumulator 13 needs to accumulate the L products, and the calculation formula is as follows

[0031]

Fiber: - ” 3⁄4 arrow :

[0032] Specifically, as shown in FIGS. 2 and 3, the manner in which the multiplier converter 11 converts the multiplier A includes the following two modes:

[0033] In the first mode, the binary highest bit of the multiplier A is reserved for 1, and the remaining bits are all set to zero. For example, as shown in Figure 2, fake Let the multiplier A be an 8-bit (bo~b ₇ ) number, and the value of A be 26, then represent A吋 in binary, it! ^, b ^nb ₅ bits are 1, and the remaining bits are 0. After conversion, 1^ ₅ bits of 1 are directly reserved, and the remaining bits are set to 0. That is to say, the value of the converted multiplier A' is 16.

[0034] Method 2: First, the two numbers 2 closest to the multiplier A are obtained according to the value of the multiplier A. And 2 ^, wherein the multiplier is in the range of 2 "~2"+1, n is an integer; then it is determined that the multiplier A is closer to which of 2 n and 2, if it is closer to 2", then Multiplier is converted to 2", otherwise the multiplier is converted to 2^

. For example, as shown in Figure 3, also assume that the multiplier A is a number of 8 bits (bo~b ₇ ), and the value of A is 26, then the two nearest neighbors to the multiplier A are 2 ⁵ =32 and 2 ⁴

= 16. Since 26 is closer to 32, the value of A' is 32.

[0035] When the multiplier A is converted in the above manner, the multiplication between the multiplier A and the multiplicand X becomes very simple, and it is only necessary to shift the X according to the position of 1 in A'. Just right. If A is a number greater than 1, then X is shifted to the left; if A is less than 1, then X is shifted to the right. That is to say, the multiplier 12 does not only implement the multiplication calculation, but actually implements the division calculation. Since the converted multiplier A' is always longer than the converted multiplier A' (8bit, 9bit, lObit...), the converted multiplier A' always has only one bit with a value of 1, so the multiplier 12 only needs to occupy lbit. Resources. That is, the multiplier 12 can be simplified into a lbit shift register. Therefore,

[0036] In the prior art, if an 8-bit multiplier A is used for multiplication, it is necessary to multiply each bit of the multiplier A, even if this bit is 0. Then, to complete an 8-bit multiplier multiplication operation, it takes at least 8 clock cycles. With the multiplier A' after the conversion of the present application, it is only necessary to perform a shift operation to complete the multiplication operation. That is to say, regardless of how long the multiplier A is, this application requires only one clock cycle to complete a multiplication operation. This greatly increases the computational speed and significantly reduces power consumption.

[0037] It should be understood that in the present application, the input and output of data may be either a serial mode or a parallel mode, or a combination of serial and parallel. This belongs to the prior art in the art, and those skilled in the art can carry out corresponding design on the basis of the present application according to actual needs, which does not require creative labor.

Embodiment 2: Multiplier array

[0039] This embodiment provides a multiplier array, as shown in FIGS. 4 and 5, the multiplier array may include at least two The multiplier adder 100 in the first embodiment.

[0040] Specifically, as shown in FIG. 4, the multiplier array 200 includes seven parallel multipliers 100. The inputs X1~X7 of the seven multipliers 100 can be identical, partially identical or completely different. If the input X1 X7 of the multiplier 100 is the same, a different multiplier A can be multiplied by the multiplicand X to achieve different filtering effects. If the inputs X1~X7 of the multiplier 100 are different, then different attribute items of the same thing can be filtered. For example, X1~X7 can represent frequency, spatial position (X-axis, y-axis, and z-axis), current, voltage, rate, and so on. By implementing the multiplier array of the present embodiment, a very complicated matter can be described with few resources.

Specifically, as shown in FIG. 5, the multiplier array 300 includes four serial multipliers 100. The multipliers A1~A4 of the four multipliers 100 can be identical, partially identical or completely different. By constructing the multiplier array 300 in series, a multi-stage filtering of the multiplicand XI can be achieved.

[0042] In other preferred embodiments provided by the present invention, the multiplier array may also include a plurality of multipliers 100 connected in parallel and in series.

[0043] It should be understood that the specific number of the multipliers 100 given in this embodiment is for illustrative purposes only and is not intended to limit the present invention. Those skilled in the art, under the teachings of the present application, can select the number of multipliers 100 according to actual needs, which does not require creative labor.

Embodiment 3: Digital Filter

[0045] This embodiment provides a digital filter. Referring to FIG. 6, the digital filter 400 includes the multiplier adder 100 described in the first embodiment.

[0046] The multiplier is a core module of the digital filter. In the prior art, the multiplication and addition operations of the filter coefficient A of the digital filter and the sampled data X are accurately calculated. However, in this application, the applicant has made a lot of exploration and research and found that the accuracy of the filter coefficient A has little effect on the final filtering accuracy of the digital filter. Therefore, the present application explores and designs a digital filter based on fuzzy calculation, which can obtain good filtering precision, can greatly reduce the amount of calculation, increase the calculation speed and save resources.

Embodiment 4: Multiply and add calculation method

[0048] This embodiment provides a multiplication and addition calculation method. Referring to FIG. 7, the multiplication and addition calculation method includes the following steps. [0049] Step S1, the multiplier is converted to obtain the converted multiplier, and the converted multiplier is expressed in binary, 只有, only one bit is 1, and the remaining bits are 0;

[0050] Further, the remaining highest digit of the multiplier is reserved, and the remaining bits are set to 0 to implement the above multiplier conversion.

[0051] Further, the multiplier conversion can also be realized by the following steps:

[0052] Step S1 l, obtaining two numbers 2 n and 2 η+ι closest to the multiplier according to the value of the multiplier, wherein the multiplier is in the range of 2 "~2"", n is an integer;

[0053] Step S12: Determine which of the 2 n and 2 ^ι multipliers is closer to, and if it is closer to 2 ", convert the multiplier to 2 ", otherwise convert the multiplier to 2 ^.

[0054] By the multiplication and addition calculation method prepared in the embodiment, the multiplication calculation can be completed quickly, the calculation speed is improved, and the power consumption of the multiplication and addition operation is reduced.

The above disclosure is only a preferred embodiment of the present invention, and of course, the scope of the present invention is not limited thereto, and those skilled in the art can understand all or part of the process of implementing the above embodiments, and Equivalent variations of the claims of the invention are still within the scope of the invention.

Claims

Claim

[Claim 1] A multiplier, comprising:

a multiplier converter for converting the multiplier to obtain a converted multiplier, the converted multiplier being represented by a binary representation, only one bit is 1 and the remaining bits are 0; a multiplier, And a multiplier for multiplying the converted multiplier by a multiplicand to obtain a product; an accumulator for accumulating the product to output an accumulated result of the product.

[Claim 2] The multiplier and adder according to claim 1, wherein the multiplier converter converts the multiplier, and retains 1 of the binary highest bit of the multiplier, and the remaining bits are Set to 0.

[Claim 3] The multiplier and adder according to claim 1, wherein the multiplier converter converts the multiplier, the multiplier converter performs the following operations: according to the multiplier a value that obtains two numbers 2 n and 2 -' that are closest to the multiplier, wherein the multiplier is in the range 2^2^, n is an integer;

It is judged which of the 2 n and 2 ^ is closer to the multiplier, and if it is closer to 2 ", the multiplier is converted to 2 n , otherwise the multiplier is converted to 2 ^.

[Attachment 4] A multiplier array comprising at least two multipliers according to any one of claims 1 to 3.

[Claim 5] The multiplier adder array according to claim 4, wherein the multipliers are connected in series.

[Claim 6] The multiplier adder array according to claim 4, wherein the multipliers are connected in parallel.

[Claim 7] A digital filter comprising the multiplier according to any one of claims 1 to 3.