RU117747U1 - DEVICE FOR CONTROL OF A THREE-PHASE AUTONOMOUS INVERTER USING A VECTOR PWM - Google Patents

Abstract

A device for controlling a three-phase autonomous inverter using a vector PWM relates to a converter technique and can be used to control autonomous voltage inverters by means of a "vector" PWM, which is implemented using digital technologies.

The objective of the utility model is to create a digital control device using a vector PWM that does not use a microprocessor or digital signal processor with software instructions, and as a result, increase the productivity, flexibility and reliability of the device while reducing size and cost.

The inventive device for digital control of a three-phase autonomous inverter using a vector PWM, in which modulation coefficients are generated, as well as digital PWM phase sweep coefficients at the on-state intervals of the upper passive phase keys and the PWM phase sweep coefficients at the on-state intervals of the lower passive phase keys, contains an analog-to-digital Converter 8, configured to convert the error voltage into an m-bit digital control code output by the inverter linear voltages (modulation coefficient code), a device for supplying control signals to the inverter keys, a digital sawtooth sweep generator (TsGPR) 13, a comparator and programmable logic circuits generating control signals implemented by programmable logic devices. The comparator is made in the form of 2n digital comparison circuits (DSS) 11 ₁ -11n, and 12 ₁ -12n settings for which are codes 2n of the PWM sweep coefficients of the active phases formed by two groups of logical matrices, of which the first group of n logical matrices (by the number of PWM intervals fundamental frequency) 9 ₁ -9n contains the pre-calculated values of the coefficients А _{B of the} phase scans of the active PWM phases at intervals - the output frequency of the on state of the upper keys of the passive phases of the inverter, corresponding to each value of the m-bit ADC code, and the second group of n logical matrices 10 ₁ -10n contains pre-calculated values of the coefficients A _{N of the} phase sweeps of the PWM active phases at intervals (output frequency) of the on state of the lower keys of the passive phases of the inverter, corresponding to each value of the m-bit ADC code. At the same time, shift registers, a pulse distributor 18 and two logic devices 15 and 16, commuting the resulting pulses of these DSSs to the corresponding inputs of the pulse distributor by the command of the RF shift register, are autonomously set in series-connected high-frequency (HF) 17 and low-frequency (LF) 19 a generator 14 and an external synchronization device 20 connected to the DCH, as well as to the high and low frequency shift registers. The outputs of these two groups of logical matrices are connected to the first inputs of the DSS, the second inputs of which receive signals from the DCHC, and the outputs of the DSS are connected to the first inputs of two logical devices, the second inputs of which receive a sequence of pulses from the RF shift register, the outputs of these two logical devices are connected with the corresponding inputs of the pulse distributor, the other inputs of which are connected to the outputs of the low-frequency shift register, and through a group of 21 AND-NOT circuits, with the keys of a three-phase inverter 1a, and the output of an autonomous master the nerator is connected to the DCHP, the output of which is connected to the RF shift register.

The technical result of this solution is the ability to implement the functions of all these devices, with the exception of an external synchronization device and an autonomous master oscillator, in one programmable logic integrated circuit; moreover, the formation of PWM phase scan coefficients for conversion is not performed as a function of the modulation coefficient, but using pre-programmed logic matrices, resulting in increased performance under conditions in sokochastotnogo PWM conversion, and hence an adequate and quick reaction to closed systems disturbance, reduced distortion autonomous inverter output voltage.

Description

The utility model relates to a conversion technique and can be used to control stand-alone voltage inverters by means of a “vector” PWM, which is implemented using digital technologies.

Vector PWM is the most common in modern systems with inverters due to the widespread use of digital microprocessor control systems. The essence of the vector PWM method is the rejection of simultaneous switching with the inverter keys and the transition to switching between several pre-selected inverter states, each of which corresponds to a specific spatial position of the base voltage vector. Changing the state of the keys leads to an abrupt transition from one base vector to another. In this case, the vector of the phase voltage of the load specified by the module U _m and the angle of rotation of the vector θ relative to the fixed coordinate axes is used as a control signal. The real phase voltage vector is a linear combination of two fixed adjacent non-zero base vectors and one or two zero base vectors, the relative duration of which γ _k on the period T of the carrier sawtooth signal are defined as sinusoidal functions of the angle θ and the module U _m .

When this type of PWM is implemented twice during the output frequency period, each phase of the inverter becomes passive, i.e. switching of power keys does not occur in it [Izosimov DB, Ryvkin S.E., Shevtsov SV Simplex control algorithms for a three-phase autonomous voltage inverter with PWM // Electrical Engineering, No. 12, 1993.]. In addition, the control signals of the phases are premodulated by an additional signal of the zero sequence containing only odd harmonics that are multiples of three.

When implementing a "vector" PWM, each of the phases is passive during 1/3 of the output frequency period when switching in the passive phase is not carried out. Therefore, the average switching frequency of each of the power switches with a “vector” PWM turns out to be 1.5 times lower than in other types of PWM with the same number of pulses in the output frequency period (E. E. Chaplygin “Spectral modeling of converters with pulse-width modulation "Textbook for the course" Modeling of electronic devices and systems "for students of the specialty" Industrial Electronics ", M, 2009).

A known block diagram of a three-phase AIN with a vector PWM algorithm for this method is shown in Fig. 3 in the work (K. Chubukov “Research and development of PWM options in three-phase autonomous voltage inverters with motor load”. Abstract of dissertation for the degree of candidate of technical sciences, Cheboksary, 2010). In this scheme, the conversion unit includes a number of arithmetic and logical operations for generating the required phase voltage tasks, the implementation of which requires significant time and includes expensive processor equipment.

A device for controlling an autonomous inverter that implements vector PWM (Goryachev OV, Eroshkin EA, Vector control of asynchronous three-phase motors. - Electronics: NTB, 1999, No. 4, p.32), which contains a programmable clock timer, digital triangle generator, containing three counters and read-only memory, control register, block of PWM registers and digital comparators according to the number of phases, block of commutators of the PWM signal according to the number of phases. The disadvantage of this device is the presence of a control register, as well as the presence of a circuit implementation of phase control, which increases the bulkiness of the device, complicates the control circuit, reducing overall performance.

Also known from foreign sources of information are inverter control devices based on the use of vector PWM using digital processors, microcontrollers and discrete elements (see, for example, US patents No. 5182701, No. 5428283, No. 6069808). The implementation of such methods using software and a digital processor requires a large number of instructions. The bit depth of the code, and especially the execution time of program instructions, does not satisfy the requirements and limitations of high-performance control systems for most applications. Modern control systems use frequencies from 25 kHz and higher to generate a PWM signal. The use of vector PWM requires multiple switching of powerful transistors in each PWM period, which, for example, for a frequency of 25 kHz is 40 μs. In addition, switching is usually controlled by interrupt signals. Microprocessors, microcontrollers, and digital signal processors have a certain delay for the processor to recognize the occurrence of an interrupt signal and run a program to start executing the instruction corresponding to this signal. Processing interrupts and executing many program codes in each PWM period of less than 40 μs makes this task difficult and sometimes impossible for microprocessors and even for high-performance digital signal processors. In addition, to implement digital control methods using vector PWM, it is desirable to provide programming flexibility so that the user can optimize the generation of control signals in accordance with the selected characteristics of the inverter with minimal losses due to noise and switching. Therefore, there is a need to eliminate these difficulties, provide a reduced cost, and, at the same time, increase the reliability and performance of such control systems without expensive processor technology, through the use of programmable logic circuits.

Closest to the claimed device is a "Symmetric vector PWM controller for controlling the inverter" described in US patent No. 6069808, which although the processor is used, but also uses many registers to store the values of the transition counts corresponding to the transition moments between the activations of the first transistors in accordance with predefined vectors. The device of this invention includes an inverter having three pairs of transistors. Each such pair of transistors is connected in series between the terminals of the voltage source. The activation of the first transistor in each pair is performed by applying to it the first activating voltage, the second and third activating voltages, respectively. The choice and duration of the effect (activation) of transistors during each of the successive equal periods T _{p are} symmetric with respect to the midpoint of each of the periods, and is represented by six non-zero vectors and two zero vectors. The control device includes a processor and a bus connected to the processor for transmitting data between the processor and other elements of the control device. The control device also includes a counter connected to the bus to ensure counting from zero to half the period T _p , and then counting back to zero, for each of the equal periods T _p . The comparison unit is connected to the bus and has many registers for storing the values of the transition counts corresponding to the transition moments between the activations of the first transistors in accordance with predefined vectors, and is designed to compare the values in the counter with the value of the transition counts and provide the corresponding transition signals when the counter value is the same as the calculated value. The device contains output logic circuits forming output control signals. Finally, a state machine connected to the bus and to the comparison unit is introduced into the device to generate the first activating voltage, the second activating voltage and the third activating voltage, and supplying them to the inverter keys in response to the corresponding transition signals.

The device has the above disadvantages associated with the use of a processor that executes program instructions for calculating the reference phase sweep coefficients, establishing one of the six sectors of the vector diagram and the corresponding main vectors using vector PWM equations and phase variables, as well as calculating switching times. The normalized values of these moments are then loaded into two comparison registers.

The objective of the utility model is to create a digital control device using a vector PWM that does not use a microprocessor or digital signal processor with software instructions, and as a result, increase the productivity, flexibility and reliability of the device while reducing size and cost.

The inventive device for digital control of a three-phase autonomous inverter using a vector PWM, in which modulation coefficients are generated, as well as digital PWM phase sweep coefficients at the on-state intervals of the upper passive phase keys and the PWM phase sweep coefficients at the on-state intervals of the lower passive phase keys, as well as a prototype, it contains an analog-to-digital converter, a device for supplying control signals to the inverter keys, a digital generator iloobraznoy sweep (TSGPR), a comparator, and programmable logic circuits forming the control signals, implemented by programmable logic devices. Unlike the prototype, the analog-to-digital converter is capable of converting the error voltage into an m-bit digital code for controlling the inverter output voltage (modulation coefficient code), the comparator is made in the form of 2 _n digital comparison circuits (DSS), the settings for which are codes 2 _n defining PWM sweep coefficients of the active phases formed by two groups of logical matrices, of which the first group of n logical matrices (according to the number of PWM intervals of the interval partition fundamental frequency) contains pre-calculated values of the coefficients A _{B of the} phase scans of the active PWM phases at intervals the output frequency of the on state of the upper keys of the passive phases of the inverter, corresponding to each value of the m-bit ADC code, and the second group of n logical matrices contains pre-calculated values of the coefficients A _{H of the} PWM phase sweeps of the active phases at intervals (output frequency) of the on state of the lower keys of the passive phases of the inverter, corresponding to each value of the m-bit ADC code. At the same time, a high-frequency (HF) and low-frequency (LF) shift registers, a pulse distributor, and two logic devices switching the resulting pulses of the indicated DSS to the corresponding inputs of the pulse distributor by the command of the RF shift register, an autonomous driving generator, and an external synchronization device are introduced into the device connected to the DCH, as well as to the high and low shift registers. The outputs of these two groups of logical matrices are connected to the first inputs of the DSS, the second inputs of which receive signals from the DCHC, and the outputs of the DSS are connected to the first inputs of two logical devices, the second inputs of which receive a sequence of pulses from the RF shift register, the outputs of these two logical devices are connected with the corresponding inputs of the pulse distributor, the other inputs of which are connected with the outputs of the low-frequency shift register, and through the group of AND-NOT circuits with the keys of a three-phase inverter, and the output of the autonomous master gene Ator TSGPR connected to the output of which is connected to the RF shift register.

The technical result of this solution is the ability to implement the functions of all these devices, with the exception of an external synchronization device and an autonomous master oscillator, in one programmable logic integrated circuit; moreover, the formation of PWM phase scan coefficients for conversion is not performed as a function of the modulation coefficient, but using pre-programmed logic matrices, resulting in increased performance under conditions in sokochastotnogo PWM conversion, and hence an adequate and quick reaction to closed systems disturbance, reduced distortion autonomous inverter output voltage.

The essence of the claimed utility model is illustrated by drawings. Figure 1 shows the control circuit of an autonomous inverter, figure 2 - schematically shows the operation at intervals π / 3 of the main frequency of the inverter, explaining the principle of vector PWM, figure 3 is a diagram of the control of the inverter.

The control device for a 3-phase bridge inverter 1, with keys 2-7 through a vector PWM, contains an analog-to-digital converter 8, the output of which is connected to two groups of logical matrices, of which the first group of n logical matrices 9 ₁ -9 _n contains pre-calculated values phase sweep coefficients of active PWM phases at intervals the output frequency of the on state of the upper keys of the 2.4 and 6 passive phases of the inverter 1, corresponding to each value of the m-bit ADC code 8, and the second group of n logical matrices 10 ₁ -10 _n contains pre-calculated values of the PWM phase scan coefficients of the active phases at intervals (output frequency) of the on state of the lower keys 3, 5 and 7 of the passive phases of inverter 1, corresponding to each value of the m-bit ADC code 8. Here n is the number of PWM intervals of the interval partition fundamental frequency. The outputs of these two groups of logical matrices 9 ₁ -9 _n and 10 ₁ -10 _n are connected to the first inputs of the digital comparison circuits ll ₁ -11 _n and 12 ₁ -12 _n , the second inputs of which are connected to a digital sawtooth generator 13, controlled by an autonomous master the generator 14 and the external synchronization device 20. The outputs of the digital comparison circuits are connected to the first inputs of the logic devices 15 and 16, the other inputs of which are connected to the program shift register HF 17. The outputs of these logical devices 15 and 16 are connected to the inputs of the pulse distributor 18, the other input which are associated with the low-frequency shift register 19. The high-frequency shift register 17 and the low-frequency shift register 19 are connected in series, and are connected to the external synchronization device 20 and to a digital sawtooth sweep generator 13. The pulse distributor 18 generates control pulses of the inverter 1 keys through the I-HE21 circuit group .

The device operates as follows:

The error voltage is converted by an analog-to-digital converter 8 into a binary control code for the inverter output linear voltages (modulation coefficient) Km in amplitude.

Figure 2 shows that the period 2π of operation of each phase, for example phase A (rack, consisting of keys 2 and 3 (see figure 2) is divided into 6 intervals (π / 3) of 60 el. Degrees. each π / 3 interval is divided, for example, into 8 PWM intervals of 7.5 electrical degrees (n = 8) .Thus, the modulation number of the PWM conversion is M = 48. If the frequency fout of the output voltage of the AIN is selected, as in our case, 1 kHz, then the switching frequency is fc = M × fout = 48 kHz, hence the period Tshim = 1 ms / 48 = 20.833 μs.

The simplest code for a two-sided digital saw is to form a reverse counter, for example, with a maximum filling of N = 500. The conditional phase voltage sweep will be equal to N.

In the first interval, the passive state of the open top switch 2 must correspond to a phase-to-phase voltage Unc equal to N, i.e. when ti = Tshim.

PWM is generated by comparing the scan signal with the control signal. In this case, as a bi-directional PWM scan at an interval of 7.5 el. column accept a "triangular" digital scan:

- in the range from 0 to 3.75 e. column - from 500 to 0 (decimal)

- in the range from 3.75 to 7.5 e. column - from 0 to 500. (See FIG. 3) That is, N = 500 - full filling of the digital sawtooth generator 13. Hence, the period of the autonomous master oscillator 14 is TTI = Tshim / 2N = 20.833 ns, and the frequency is 48 MHz.

With a “vector” PWM, twice during the period of the output frequency with a shift π during the π / 3 intervals, the control of each phase of the inverter is made passive, i.e. switching power keys with a PWM frequency does not occur in it. In this case, either the upper or lower phase switch is open in accordance with the control algorithm (see Fig. 3). The other two phases using PWM are controlled by a reversal of the duration of 48 kHz pulses according to a sinusoidal law. Thus, the average switching frequency of each power switch is 1.5 times lower compared to the classical PWM, which accordingly reduces dynamic losses.

If the phase PWM tasks correspond to the fundamental harmonic of the phase output voltage of the AIN, then in the "uncontrolled network rectifier - AIN" system, the output voltage does not exceed 0.827 of the network voltage. Actually, due to losses and time delays of keys - even lower. The task of increasing the ratio of the fundamental harmonic of the output voltage to the supply voltage can be solved in only one way - by using the non-sinusoidal law of changing phase tasks, for example, rectangular or trapezoidal, but this leads to a deterioration in the harmonic composition of the phase and linear output voltages of the AIN, primarily due to 5th, 7th, 11th and 13th harmonics. Harmonics that are multiples of three are zero-sequence harmonics, and with a symmetrical load, they are not contained in phase and linear load voltages. In our case, bridge three-phase rectifiers are used, i.e. symmetrical load.

Therefore, premodulation is implemented by applying the non-sinusoidal trapezoidal law to modulate the pulse durations of the phase potentials φ _A , φ _B and φ _C , which provides an increase in the amplitude of the fundamental harmonic, but the spectrum of PWM sequences φ _A , φ _B and φ _C contains only the fundamental harmonic harmonics of the zero sequence, i.e. harmonics that are multiples of three. This ensures the absence in the low-frequency part of the spectrum of phase and linear voltages of the inverter of distortion harmonics.

The error voltage is converted by an analog-to-digital converter (ADC) 8 into a binary control code (output voltage of the inverter 1), which we will call the modulation factor Km by the amplitude of the autonomous voltage inverter. The code range Km is actually selected to be 0-N, and in relative units Km = 0 …one. Km is the modulation coefficient, from 0 to 1, or the relative output error voltage converted to a digital code (the ratio of the current ADC code to the ADC code corresponding to the maximum output error voltage). With Km = 1

Um1 / Upit = 1 / cos (π / 6) = 1.1547,

where Upit is the input voltage of the inverter, Um1 is the amplitude of the first harmonic of the output voltage.

In general, the reference voltage Uop of the phase sweep controlled by PWM is

Uop = Uet + Upm,

where Uet is the reference sinusoidal voltage of the phase sweep with PWM modulation corresponding to the segment of this phase in the considered 60-degree interval, and Um is the third-harmonic premodulation voltage corresponding to the segment of this phase in the considered 60-degree interval.

In its turn

Upm = Ups - Uet.ps,

where Ups is the scan voltage of the passive phase in the considered interval, and Uet.ps is the reference sinusoidal scan voltage of the passive phase.

Upm - on the interval 2π of the main harmonic of the output voltage, it will take the form of the third harmonic.

Consider the first (conditionally) 60-degree sweep interval (see FIGS. 2 and 3). At this time, the upper key 2 is open, and the key 3 is locked. Thus, the control of phase A is passive.

In the first interval, the passive state of the open upper 2 key must correspond to a phase-voltage Ups equal to N, i.e. when ti = Tshim.

In the future, it is assumed that under the control of the phases refers to the management of the upper power keys of the AIN bridge. The management of the lower phase keys is automatically inverted with respect to the corresponding upper key. Taking N / 2 as the level of the conditional zero line of the phase scans, unified (for the period of the main frequency) digital setting coefficients of the phase scans Av1 and Av2 are calculated on the intervals of the on state of the upper keys of the passive phases, as well as An1 and An2 on the intervals of the on state of the lower keys passive phases for each 60 degree interval.

The implementation of PWM phase scans is based on the condition that the average value of the PWM pulse is equal to the average value of the reference scan voltage in the Tshim period interval. Taking a segment of the reference voltage in the range of 7.5 el. column linear, we get the threshold point in the middle of the PWM interval. The setting factors for Km = 1 are the current settings for digital comparison circuits 11 ₁ -11 _n , 12 ₁ -12 _n .

With a 9-bit ADC code at the output, for each Km value in the range from 0 to 1, with a resolution of 1: 500 = 0.002, we must have 16 coefficient tables Av1.1 (Km) ... Av1.8 (Km), An2.1 ( Km) ... An2.8 (Km).

The order of alternating switching keys on the period of the fundamental frequency of the AIN is shown in table 1.

Table 1 Control interval π / 3 number for the period one 2 3 four 5 6 Passive phase BUT FROM AT BUT FROM AT Passive Key Status On 2 7 four 3 6 5 Off 3 6 5 2 7 four PWM Phase Scan Factor Av1 Phase AT FROM BUT Key four 6 2 Av2 Phase FROM BUT AT Key 6 2 four An1 Phase BUT AT FROM Key 2 four 6 An2 Phase AT FROM BUT Key four 6 2

Thus, in the indicated device, 8 logical matrices are generated programmatically according to the above tables, where each value of the 9-bit ADC code corresponds to the value of 8 phase scan coefficients Av (matrices 9 ₁ -9n as well as 8 logical matrices, where each value 8 the ADC bit code corresponds to the value of 8 coefficients an (10 ₁ -10n). These phase scan coefficients as settings in the form of codes are fed to the inputs of digital comparison circuits 11 ₁ -11n and 12 ₁ -12n. At the same time, the digital sawtooth generator 13 six arrive of sequences of synchronization pulses from the generator 14, shifted relative to each other by 60 electrical degrees, with a frequency of 1 kHz and a duration of 166.6 μs, each sequence is a sign of the interval number π / 3 of the key control of inverter 1 on the period of the fundamental frequency. this 60-degree interval corresponds to a rectangular pulse of the same duration (7.5 el. degrees) of one of 8 sequences of pulses with a frequency of 6 kHz, formed by a high-frequency shift register 17. These pulses into logic devices 15 and 16 are allowed to "gate" for comparison of resulting pulses digital comparison circuits -11n January ₁₁ and January ₁₂ -12n, the incoming pulses to respective inputs of the distributor 18. The pulses received from the shift register to the other input pulse distributor low frequency 19, corresponding to 60-degree intervals, according to which, the pulse distributor 18 generates control pulses of power keys 2-7 of the inverter 1, which are supplied to them through a group of AND-NOT 21 circuits.

Such digital processing of the control signals of the inverter allows you to implement this device in one programmable digital microcircuit with an increase in speed, increased reliability and reduced size. In this case, the formation of PWM phase-conversion coefficients for the PWM conversion is performed not by calculating a function of the specifying modulation coefficient, but by using preprogrammed logic matrices, and therefore, an adequate and quick response of closed systems to the disturbing effect, and reduction of distortion of the output voltage of the autonomous inverter, is achieved.

Claims (1)

A device for digitally controlling a three-phase autonomous inverter using a vector PWM, at which modulation coefficients are generated, as well as digital PWM phase-sweep coefficients at the upper pass-phase switched-on intervals and the PWM phase-sweep coefficients at the low-pass-phase switched-on intervals, containing analog-to-digital converter (ADC), a circuit providing control signals for the keys of a three-phase inverter, a digital sawtooth generator sweep (TsGPR), a comparator and logic circuits that generate control signals, as well as a control unit, characterized in that the analog-to-digital converter is configured to convert the error voltage into an m-bit digital code for controlling the inverter output voltage line (modulation coefficient code), the comparator is made in the form of 2n digital comparison circuits, the settings for which are codes of 2n PWM sweep coefficients of the active phases formed by two groups of logical matrices, of which the first a group of n logic arrays contain precalculated values of coefficients of the phase sweeps active phase PWM intervals

the output frequency of the on state of the upper keys of the passive phases of the inverter, corresponding to each value of the m-bit ADC code, and the second group of n logical matrices contains pre-calculated values of the PWM phase scan coefficients of the active phases at intervals

the output frequency of the on state of the lower keys of the passive phases of the inverter, corresponding to each value of the m-bit ADC code, while the device is connected to a series of high-frequency (HF) and low-frequency (LF) shift registers, a pulse distributor, and two logical devices that switch the resulting pulses of the indicated DSS to the corresponding inputs of the pulse distributor at the command of the high-frequency shift register, an autonomous master oscillator and an external synchronization device connected to the DCH, as well as to the high-frequency LF shift registers, while the outputs of these two groups of logical matrices are connected to the first inputs of the DSS, the second inputs of which receive signals from a digital sawtooth generator, and the outputs of the DSS are connected to the first inputs of two logical devices, the second inputs of which receive a sequence of pulses from the RF the shift register, the outputs of two logical devices are connected to the corresponding inputs of the pulse distributor, the other inputs of which are connected to the outputs of the low-frequency shift register, and through the AND-NOT circuits with the keys tr hfaznogo inverter and auxiliary oscillator output is connected to TSGPR whose output is connected to the RF shift register.