JP3259308B2 - Inverter device and uninterruptible power supply using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter device and an uninterruptible power supply device, and more particularly to an inverter device suitable for stably operating inverters operating in parallel by suppressing inverter output overcurrent during transients. It relates to an uninterruptible power supply.

[0002]

2. Description of the Related Art When driving a large-capacity load with a small-capacity power supply device, or when configuring a highly reliable power supply system by parallel multiplexing, the output terminals of a plurality of power supply devices are connected in parallel. The driving method is adopted. A conventional inverter parallel operation method will be described by taking an uninterruptible power supply for a computer as an example. An uninterruptible power supply device is a power supply device that normally receives power supply from a commercial AC system, and supplies AC power of a predetermined voltage and a predetermined frequency to a load by using the power of a storage battery during a power failure. converter),
An uninterruptible power supply unit comprising an inverter and a storage battery;
And a control circuit for controlling the uninterruptible power supply unit. The rectifier converts AC power from the commercial AC system into DC power, charges the storage battery, and is supplied as an input to the inverter. The storage battery supplies DC power to the inverter in place of the rectifier during a power failure. The inverter receives a supply of DC power from a rectifier or a storage battery and outputs stable AC power at a predetermined voltage and frequency. When a plurality of such uninterruptible power supplies are connected in parallel and operated, the voltage difference and the phase difference of the inverter output voltage of each uninterruptible power supply are suppressed, and the current flowing between the uninterruptible power supplies, Must be minimized to protect the power supply from overcurrent. In order to suppress this cross current, a phase difference and a voltage difference between output voltages of the inverters are detected as described in JP-A-1-255475, and each inverter output is controlled so as to suppress the phase difference. There is known a method of correcting the frequency of the voltage and the magnitude of each inverter output voltage so as to suppress the voltage difference. There are various methods for detecting the phase difference and the voltage difference. In the above-mentioned patent publication, the phase difference is indirectly detected by the difference in the active power output from each inverter, and the voltage difference is indirectly detected by the difference in the reactive power.

[0003]

When the above-described phase difference and voltage difference detection method is adopted, it is necessary to detect the phase difference and the voltage difference as DC components, so that a filter having a time constant of several tens of ms is used in the detection circuit. I have. Therefore, the cross current when the inverters are turned on in parallel is suppressed by the main circuit impedance on the inverter output side for several tens of ms. However, recently, with the improvement of the performance of the power semiconductor element, a high frequency inverter has been used in which the switching frequency of the inverter is increased to reduce the size of a filter for reducing the output ripple of the inverter. In such a high-frequency inverter, since the main circuit impedance on the inverter output side is small, it is difficult to suppress the overcurrent on the inverter output side using only the main circuit impedance. In addition, if the instantaneous voltage control method that instantaneously adjusts the voltage of the output filter to the command value to fully utilize the high-speed response characteristics of the high-frequency inverter is adopted, the output voltage drop due to overcurrent on the output side is instantaneously corrected. Overcurrent suppression due to the impedance of the output filter cannot be expected.

An object of the present invention is to provide an inverter device and an uninterruptible power supply which solve the above-mentioned problems.

It is another object of the present invention to provide an improved inverter device and an uninterruptible power supply device capable of suppressing an overcurrent on the output side when a high-frequency inverter is operated in parallel.

Further objects of the present invention will become clear from the description hereinafter.

[0007]

The inverter device according to the present invention which solves the above-mentioned problems is characterized by a plurality of inverters whose input side is connected to a DC power supply and whose output side is connected to the same load, and a plurality of inverters which control each inverter. Each control circuit comprises: (1) voltage detection means for detecting the output voltage of the inverter, (2) current detection means for detecting the output current of the inverter, and (3) output voltage of a plurality of inverters. (4) a sinusoidal waveform corresponding to the frequency and amplitude of the voltage to be output by the inverter based on the output signal of the voltage detection means and the output signal of the first deviation detection means. (5) a second deviation detecting means for converting the output signal of the current detecting means into a voltage signal and detecting a deviation between the voltage signal and the output signal of the parallel operating control circuit; (6) Third deviation detecting means for detecting a deviation between the output signal of the second deviation detecting means and the output signal of the voltage detecting means, (7) deviation between the output signal of the second deviation detecting means and the output signal of the voltage detecting means And control means for controlling the duty of the inverter so as to reduce the duty.

The uninterruptible power supply of the present invention which solves the above-mentioned problems is characterized by a rectifier for converting AC power from a commercial AC system into DC power, an inverter connected to an output side of the rectifier for converting DC power into AC power, A plurality of uninterruptible power supply units, each of which has a storage battery that supplies DC power to the inverter when the commercial AC system is out of power, and the output side of the inverter is connected to the same load, and a plurality of control circuits that control each uninterruptible power supply unit Each control circuit comprises: (1) voltage detection means for detecting the output voltage of the uninterruptible power supply unit,
(2) current detecting means for detecting the output current of the uninterruptible power supply unit; (3) first deviation detecting means for detecting a deviation of the output voltages of the plurality of uninterruptible power supply units; (4) output of the voltage detecting means A parallel operation control circuit for generating a sinusoidal voltage waveform command signal corresponding to the frequency and amplitude of the voltage to be output by the uninterruptible power supply unit based on the signal and the output signal of the first deviation detecting means; A second deviation detecting means for converting an output signal of the detecting means into a voltage signal and detecting a deviation between the voltage signal and an output signal of the parallel operation control circuit; (6) an output signal of the second deviation detecting means and a voltage signal of the voltage detecting means; Third deviation detecting means for detecting a deviation from the output signal, and (7) control means for controlling the duty of the inverter so as to reduce the deviation between the output signal of the second deviation detecting means and the output signal of the voltage detecting means. , Is provided.

[0009]

According to this configuration, a voltage waveform command signal having a sine waveform corresponding to the frequency and amplitude of the voltage to be output by the inverter is generated based on the output signal of the voltage detection means and the output signal of the first deviation detection means. The frequency and amplitude of the voltage to be output by each inverter is determined by the generated parallel operation control circuit. At this time, the output signal of the current detection means is converted to a voltage signal, and the deviation between the output signal and the output signal of the parallel operation control circuit is detected. The second deviation detecting means corrects the frequency and amplitude of the voltage to be output from each inverter, thereby suppressing overcurrent when the inverters are turned on in parallel.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of an inverter device according to the present invention. FIG. 1 is a schematic circuit configuration diagram showing an uninterruptible power supply to which the inverter device of the present invention is applied. The uninterruptible power supply includes an uninterruptible power supply unit and a control circuit. In the figure, 1 is a commercial AC system,
Reference numerals 2 and 3 denote an uninterruptible power supply unit whose input side is connected to the commercial AC power system 1, respectively, and 4 denotes a series connection of resistors 5 and 6, reactors 7 and 8, and switches 9 and 10 on the output side of the uninterruptible power supply units 2 and 3, respectively. This is a load connected via a circuit. Here, the resistors 5 and 6, the reactor 7
And 8 show the impedance of the wiring. The uninterruptible power supply units 2 and 3 are respectively connected to the commercial AC system 1 and rectifiers 2a and 3a, inverters 2c and 3c connected to the output sides of the rectifiers 2a and 3a, and the rectifier 2a.
And 3a, storage batteries 2b and 3b connected to the connection point between inverters 2c and 3c, transformers 2d and 3d connected between inverters 2c and 3c and resistors 5 and 6, transformers 2d and 3d and resistor 5 And 6 are connected to the connection point between the inverter 2c and the inverter 2c.
And 3c are usually rectifiers 2a and 3a
And supplies DC power from the storage batteries 2b and 3b at the time of a power failure, converts the DC power into AC power, and supplies stable AC power to the load 4. Here, the transformers 2d and 3d are used to insulate the commercial AC system 1 from the load 4, and the inverters 2c and 3e have respective leakage reactances and capacitors 2e and 3e.
And 3c. The control circuit of the uninterruptible power supply units 2 and 3 includes inverters 2c and 3c
Current detectors 11 and 12 for detecting the output currents of the current detectors, and a current control circuit 1 for outputting voltage signals ΔV ₁ and ΔV ₂ proportional to the detection signals kI ₁ and kI ₂ of the current detectors 11 and 12
3 and 14, a parallel operation control circuit 15 for generating voltage waveform command signals _VR10 and _VR20 having a sine waveform corresponding to the frequency and amplitude of the voltage to be output by the uninterruptible power supply units 2 and 3.
And 16, a voltage signal △ V ₁ and △ V ₂ and the voltage waveform command signal V _R10 and the output signal △ V ₁ and △ V of the current control circuit 13 and 14 for detecting the deviation V _R1 and V _R2 and V _{R20 2} is replaced by the parallel operation control circuits 15 and 1
6 and the output voltages V ₁ and V _{2 of the} inverters 2c and 3c, which are added to the output signals V _R10 and V _R20 of FIG.
Voltage detector 19 and 20 for detecting the output signal kV ₁ output signals kV ₁ and kV ₂ the voltage detector 19 and 20 for detecting the deviation V _R1 and V _R2 of the output signal V _R1 and V _R2 and Adders 21 and 22 that add kV ₂ to the output signals V _R1 and V _R2 of the adders 17 and 18 with their polarities changed, and signals D ₁ and D ₁ that control the inverters 2 c and 3 c based on the output signals of the adders 21 and 22. It comprises voltage waveform control circuits 23 and 24 for generating D ₂ , and adders 25 and 26 for applying deviation signals ε ₁ and ε ₂ of the output signals of the voltage detectors 19 and 20 to the parallel operation control circuits 15 and 16. I have. The parallel operation control circuits 15 and 16 output signals kV _{1 and} / or kV of the voltage detector 19 or 20 for detecting the output voltage of the uninterruptible power supply unit 2c or 3c on the controlling side in addition to the deviation signals ε ₁ and ε ₂ , respectively. ₂ is the input signal.

The current control circuit 13 (and 14) has, for example, the configuration shown in FIG. DC voltage Vcc to variable resistor 1
Current signals G ₁ that is proportional to the voltage divided by 3a detector 1
The detection signal kI ₁ is multiplied by ₁ to output an output signal ΔV ₁ . The signal G ₁ is the sensitivity of the current control circuit 13 to the detection signal kI ₁ , and can be set to a value at which the uninterruptible power supply unit 2 can operate stably by operating the variable resistor 13a. Here, 13b and 13c are operational amplifiers,
13d, 13e, 13f, 13g, 13h and 13i are resistors, and 13j is a multiplier.

The parallel operation control circuit 15 (and 16)
Has the configuration of FIG. 3, for example. This circuit, as shown in FIG. 4, to create a signal CP ₁ from the output signal kV ₁ of the voltage detector 19 through the comparator 15c, whereas signal CP ₁ signals kV ₁ via the differentiating circuit 15a and a comparator 15b create a signal CP ₂ advanced by the phase more 90 electrical degrees, the signal smoothing filter 15 multiplied by the signal CP ₁ only voltage deviation epsilon ₁ while the switch 15d is closed
h, a voltage correction value ΔE is generated as a DC signal, and a signal obtained by multiplying the voltage deviation ε ₁ by the signal CP ₂ is converted to a smoothing filter 1.
5g, a frequency correction value Δf is generated as a DC signal, a frequency command f (f = f ₀ + Δf) is generated from the reference frequency command f ₀ and the frequency correction value Δf by an adder 15i, and a reference is generated by an adder 15j. A voltage command E is created from the voltage command E ₀ and the voltage correction value ΔE, and the sine wave generation circuit 15 k
Thus, a voltage waveform command _VR10 having a sine waveform corresponding to the frequency command f and the voltage command E is created.

The operation of the uninterruptible power supply provided with the control circuit having such a configuration will be described. As understood from the block diagram of FIG. 3, the parallel operation control circuit 15 includes a signal kV ₁ proportional to the output voltage V ₁ of the uninterruptible power supply unit 2 and a signal kV ₁ proportional to the output voltage V ₂ of the uninterruptible power supply unit 3. uninterruptible power supply unit 2 with voltage deviation signal ε ₁ from kV ₂ as input
Determines the frequency and amplitude of the voltage to be output, and creates a sinusoidal voltage waveform command signal _VR10 . Current control circuit 1
5 outputs a signal ΔV ₁ proportional to the output current I ₁ , as understood from the block diagram of FIG. From these signals, the voltage waveform control signal V _R1 (= V
_R10 - [Delta] V ₁₎ is Motomari, the voltage waveform control circuit 23 is an inverter 2 so as to reduce the deviation between V _R1 the output voltages V ₁
controlling the duty command signal D ₁ of the c. This operation is the same for the uninterruptible power supply unit 3.

In the circuit configuration of FIG. 1 described above, only the switch 10 is closed and the load 4 is driven only by the second uninterruptible power supply having the uninterruptible power supply unit 3. Consider the case where the first uninterruptible power supply devices each having the following configuration are connected in parallel. In this case, first, the switch 15d shown in FIG. 3 is closed to operate the parallel operation control circuits 15 and 16, and then the switch 9 is turned on to perform the parallel operation of the first and second uninterruptible power supply devices. Accordingly, there is a deviation between the output voltages V ₁ and V ₂ of the _first and _second uninterruptible power supply units due to a response delay of the filters 15 g and 13 h and a difference in response characteristics of the voltage waveform control circuits 23 and 24 shown in FIG. When there is, a cross current flows between both uninterruptible power supplies.
In particular, the impedance contributing to current suppression is the resistance of the wiring 5
Considering that only the current control circuits 13 and 14 and the reactors 7 and 8 are provided, there is a risk that each of the inverters will be in an overcurrent state without the current control circuits 13 and 14. However, in FIG. 1, since the voltage waveform command signals V _R1 and ΔV _R2 are corrected by the output signals ΔV ₁ and ΔV _{2 of the} current control circuits 13 and 14, overcurrent is effectively suppressed. The operation waveform at this time is shown in FIG. FIG. 5 shows the voltage detectors 19 and 2 when the output voltage V ₁ of the _first uninterruptible power supply is higher than the output voltage V _{2 of} the second uninterruptible power supply.
The amplitudes of the responses of the output signals kV ₁ and kV _{2 of} 0 and the output signals kI ₁ and kI ₂ of the current detectors 11 and 12 are shown. The waveform indicated by the solid line indicates the response when the current control circuits 13 and 14 are not provided, and the waveform indicated by the broken line indicates the response when the current control circuits 13 and 14 are provided, respectively. First, when turning on the switch 9 at the time of t _1,
If there is no current control circuit 13 and 14 cross flow current flows between both the uninterruptible power supply by the difference between V ₁ and V ₂ as shown by the solid line, the current I ₁ is greater than the steady value I _10. The current I ₂ is smaller than the steady value I _20. After that, the output voltage difference between the two uninterruptible power supplies is suppressed by the operation of the parallel operation control circuits 15 and 16, and the currents I ₁ and I ₂ also settle to steady values. In contrast, the current control circuit 1
When there are 3 and 14, the magnitudes of the output voltages of both uninterruptible power supplies are suppressed according to the magnitudes of the currents I ₁ and I ₂ as indicated by broken lines, and the voltage difference between the uninterruptible power supplies is reduced. Since it becomes smaller, the difference between the currents I ₁ and I ₂ is also suppressed. Therefore, according to the present embodiment, it is possible to effectively suppress the cross current flowing between the uninterruptible power supplies when a plurality of uninterruptible power supplies are operated in parallel.

Although this embodiment has been described by taking as an example a case where a plurality of uninterruptible power supply units are operated in parallel, the present invention is not limited to this case. Can be applied as is.

FIG. 6 is a schematic circuit diagram showing another embodiment of the present invention, and FIG. 7 is an operation waveform diagram thereof. This embodiment is shown in FIG.
The difference from the embodiment of FIG.
Deviations ΔkI ₁ (= kI ₁ −kI ₂ ) and ΔkI ₂
The point is that adders 27 and 28 are provided so that (= kI ₂ −kI ₁ ) becomes an input signal of the current control circuits 13 and 14.
With such a configuration, the output voltage V ₂ of the operation by the contrast output voltage V ₁ of the uninterruptible power supply unit 2 is lowered, the uninterruptible power supply unit 3 of the current control circuit 13 as indicated by the broken line in FIG. 7 is a current It rises by the operation of the control circuit 14.
Therefore, in this embodiment, as can be seen by comparing FIGS. 5 and 7, there is an advantage that the effect of suppressing the voltage difference between the uninterruptible power supplies is further increased as compared with the embodiment of FIG. In a steady state, the operation of the current control circuits 13 and 14 has an effect of suppressing a decrease in output voltage. Therefore, according to the present embodiment, it is possible to provide an ideal uninterruptible power supply in which the fluctuation of the output voltage due to the size of the load is small.

8 and 9 are schematic circuit diagrams showing another embodiment of the present invention, and FIG. 10 is an operation waveform diagram thereof. This embodiment differs from the embodiment of FIG. 1 in that a sequence control circuit 29 for managing the entire parallel operation system is provided, whereby signals kI ₁ and kI of the current control circuits 13 and 14 are provided.
In point so as to manipulate the sensitivity to I _2. The sequence control circuit 29, the current control circuit 13 and the sequence signal generator 29a for generating a sequence signal S ₁ and S ₂ operate the sensitivity of 14, the switch driving signal SD ₁ of the sequence signal S ₁ and S ₂ by delaying a predetermined time And S
In the D ₂ delay circuit 29 to be applied to the switches 9 and 10
b and 29c. The sensitivity of the current control circuits 13 and 14 is increased when the uninterruptible power supply units requiring overcurrent suppression are turned on in parallel, and lowered when the stable parallel operation is performed and when the operation is performed with one uninterruptible power supply unit. Ideally, the fluctuation of the output voltage with respect to the change of the output current is reduced. In this embodiment, the signal k of each of the current control circuits 14 and 14 is controlled by the sequence control circuit 29.
Because you have to manipulate the sensitivity to I ₁ and kI _2, if the sequence signal generating circuit 29a in parallel put uninterruptible power supply unit 2 generates a sequence signals S ₁ of a parallel closing command shown in FIG. 10, the current Control circuit 14
In Figure 10 the sensitivity G ₁ in accordance with the cans signal S ₁ - This sheet
The above is achieved by changing as shown in (4). That is, the sensitivity G ₁ when the parallel is turned on high, will lower with time, becomes almost zero in the steady operating state. The current control circuit 14 having such characteristics can be easily realized by the configuration shown in FIG. In FIG. 9, operational amplifiers 32a to 32
c, capacitors 32d, resistor 32e~32m and has operated the sensitivity G ₁ in the current sensitivity operation circuit 32 composed of variable resistor 32n, the output ST ₁ the operational amplifier 32a a sequence signals S ₁ shown in FIG. 10 are input Changes as shown in FIG. At this time, the value of sensitivity G ₁ is found as the (4) in FIG. 10 by addition of 10 (1) of FIG. 10 (3). Switch 9 of FIG. 8 must be operated after the sensitivity G ₁ of the current control circuit 13 is established, operating the sequence signals S ₁ by the switch driving signal SD ₁ which is delayed by the delay circuit 29b. Also, adjustment of the peak value of the sensitivity G ₁ is performed by operating the variable resistor 32n.

FIG. 11 shows another embodiment of the current control circuit 13 (and 14), which provides a current control circuit which enables parallel operation between uninterruptible power supplies having different device capacities. This current control circuit includes a sequence signal generation circuit 29
a, a current sensitivity operation circuit 32 (shown in FIG. 9) and a delay circuit 33 connected to the output side of the current detector 11, an effective value detection circuit 36 connected to the output side of the current detector 11, and a reference current value Ie from Vcc.
Variable resistor 35 for setting _10, an adder 37 for comparing the output signal Ie ₁ and the reference current value Ie ₁₀ of the effective value detection circuit 36,
The current control function 38 connected to the output side of the adder 37, the switch 34 for switching the output signal of the current sensitivity operation circuit 32 and the output signal of the current control function 38 to the output signal of the delay circuit 33, and the output side of the switch 34 Connected adder 13j
Consists of In such a current control circuit, the delay circuit 3
In 3 of the output signal SD ₃ by operating the switch 34, it operates as G ₃ = G ₁ when SD ₃ is Low leveling Le, also SD ₃ becomes G ₃ = G ₂ when the High leveling Le I do. Where G
₂ is a signal current control function 38 outputs so as to approach the set value Ie ₁₀ to the effective value Ie ₁ of the current kI ₁ obtained through the effective value detection circuit 36 is set by the variable resistor 35. Therefore, since the output signal SD ₃ of the delay circuit 33 when the High level is the effective value Ie ₁ of the current I ₁ is controlled in accordance with the setting value Ie _10, the set value of the output current effective value for each uninterruptible power supply By changing Ie ₁₀ , the current sharing between the devices can be manipulated. Figure 12 is an operation waveform diagram of FIG. 11, the output signal SD ₃ of the delay circuit 33, the time determined by the delay circuit 33 to sequence signals S ₁ of the sequence signal generator circuit 29a in FIG. 8 as shown in FIG. 12 T
The waveform is delayed by D. At this time, the current control circuit 15
Is the time t ₃ before the simple current suppressing operation, the time t ₃ after the current sharing control operation. Therefore, according to the present embodiment, the current suppression operation is performed by adjusting the delay time TD while the transient response when the uninterruptible power supplies are turned on in parallel continues, and the current sharing operation is performed after reaching the steady state. It is possible to operate.

FIGS. 13 and 14 show still another embodiment of the present invention, which shows a configuration in which a large number of uninterruptible power supplies are operated in parallel. In FIG. 13, three uninterruptible power supplies 39, 40, and 41 are configured so that they can be turned on in parallel by switches 9, 10, and 45, respectively, and the parallel operation control circuit 15 (the components in 40 and 41 are omitted). and using a signal kV _L proportional to the load voltage V _L obtained through the average value voltage, that the voltage detector 42 of each inverter as a reference waveform for determining the voltage difference and the phase difference between the output voltage. Therefore, the adder 25 outputs the signal k from the voltage detector 19.
It serves to detect the deviation between the signals kV _L from V ₁ and the voltage detector 42. In this way, multiple units can be operated in parallel. Further, FIG. 14 shows a modification of FIG. 8 in which the uninterruptible power supplies 39, 40 and 41
And changes the sensitivity of the current control circuit and drives the switch with a delay of a predetermined time from the sequence signal. 43 is a resistor, and 44 is a reactor.

[0020]

According to the present invention, the cross flow between the inverters when the inverters are operated in parallel can be effectively suppressed, and each inverter can be operated stably. In addition, since the shared current can be set for each device, parallel operation between inverters having different capacities is also possible.

[Brief description of the drawings]

FIG. 1 is a schematic circuit configuration diagram showing an embodiment of an uninterruptible power supply to which the present invention is applied.

FIG. 2 is a detailed diagram of a current control circuit used in the uninterruptible power supply of FIG.

FIG. 3 is a detailed diagram of a parallel operation control circuit used in the uninterruptible power supply of FIG. 1;

FIG. 4 is a waveform chart for explaining an operation of the parallel operation control circuit of FIG. 3;

FIG. 5 is a waveform chart for explaining the operation of the uninterruptible power supply of FIG. 1;

FIG. 6 is a schematic circuit diagram showing another embodiment of the uninterruptible power supply to which the present invention is applied.

FIG. 7 is a waveform chart for explaining the operation of the uninterruptible power supply of FIG. 6;

FIG. 8 is a schematic circuit diagram showing another embodiment of the uninterruptible power supply to which the present invention is applied.

FIG. 9 is a detailed diagram of a parallel operation control circuit used in the uninterruptible power supply of FIG. 8;

FIG. 10 is a waveform diagram for explaining an operation when the parallel operation control circuit of FIG. 9 is applied to the uninterruptible power supply of FIG. 8;

FIG. 11 is a detailed diagram showing another embodiment of the parallel operation control circuit used in the uninterruptible power supply of FIG.

FIG. 12 is a waveform diagram for explaining an operation when the parallel operation control circuit of FIG. 11 is applied to the uninterruptible power supply of FIG. 8;

FIG. 13 is a schematic circuit diagram showing still another embodiment of the uninterruptible power supply to which the present invention is applied.

FIG. 14 is a schematic circuit diagram showing still another embodiment of the uninterruptible power supply to which the present invention is applied.

[Explanation of symbols]

1: Commercial AC system, 2, 3: Uninterruptible power supply unit, 2
a, 3a rectifier, 2b, 3b storage battery, 2c, 3c
Inverter, 4 ... Load, 9,10 ... Switch, 11,1
2: Current detector, 13, 14: Current control circuit, 15, 1
6. Parallel operation control circuit, 17, 18, 21, 22, 2
5, 26, 27, 28 adder, 29 sequence control circuit, 39, 40, 41 uninterruptible power supply.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Keizo Shimada 3-1-1, Sakaimachi, Hitachi, Ibaraki Pref. Hitachi, Ltd. Hitachi Plant (72) Inventor Kiichi Tokunaga 4026 Kujicho, Hitachi, Ibaraki Stock (72) Inventor Yoshimi Sakurai 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd.Hitachi Laboratory Co., Ltd. (72) Inventor Ikuo Yamato 4026, Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. (56) References JP-A-2-303327 (JP, A) JP-A-62-268323 (JP, A) JP-A-1-99477 (JP, A) JP-A-3-128626 (JP, A) ( 58) Surveyed field (Int.Cl. ⁷ , DB name) H02M 7/48

Claims (2)

(57) [Claims] With a 1. A plurality of input side is connected to the DC power supply output side connected to the same load inverter, and a plurality of control circuit for controlling several Lee <br/> inverter each plurality, the each control circuit, voltage detecting means for detecting (1) the output voltage of the inverter
When current detecting means for detecting an output current of (2) the inverter
When the second difference detecting means for detecting (3) and the first deviation detecting means for detecting a deviation of the output voltage of said plurality of inverters, (4) the deviation of the output current of the plurality of inverters, (5) parallel operation the inverter generates a voltage waveform instruction signal of a sine waveform corresponding to the frequency and amplitude of the voltage to be outputted based output signal and the output signal of said first difference detecting means of said voltage detecting means a control circuit, and a third difference detecting means for detecting (6) changing the output signal of the second deviation detecting means into a voltage signal, the deviation between the output signal of the parallel operation control circuit and the voltage signal, (7 ) and fourth deviation detecting means for detecting a deviation between output signals of the voltage detecting means of the third difference detecting means (8) of the output signal and the voltage detecting means of the third difference detecting means Set the duty of the inverter so that the deviation from the output signal is small. Inverter apparatus characterized by comprising control means for controlling, the. Wherein the AC power from the commercial AC line and the rectifier for converting the DC power, an inverter for converting DC power is connected to the output side of the rectifier into AC power, the inverter in the event of a power failure of the commercial AC system and uninterruptible power supply unit and a storage battery for supplying DC power, a plurality of wireless power failure
The output side of the inverter of the power supply unit is connected to the same load, and a plurality of control circuits for controlling the respective several UPS units plurality, each said control circuit, (1) the uninterruptible power supply detecting a voltage detecting means for detecting an output voltage of the unit, a current detecting means for detecting an output current of (2) the uninterruptible power supply unit, the deviation of (3) the output voltage of the plurality of uninterruptible power supply units a first deviation detecting means, (4) and the second deviation detecting means for detecting a deviation of the output current of the plurality of uninterruptible power supply unit, (5) the output signal and the first difference of said voltage detecting means a parallel operation control circuit for generating a voltage waveform instruction signal of a sinusoidal waveform based on the output signal uninterruptible power supply unit corresponding to the frequency and amplitude of the voltage to be output of the detecting means, (6) the second difference detecting Means output signal to voltage signal Deviation of recombinant, a third difference detecting means for detecting a deviation between the output signal of the parallel operation control circuit and the voltage signal, and (7) the output signal of the output signal and the voltage detecting means of the third difference detecting means a fourth difference detecting means for detecting, control means for controlling the duty cycle of the inverter so as to reduce the deviation between the (8) output signals of the voltage detecting means of the third difference detecting means, An uninterruptible power supply comprising: