CN110048627B - Modulation method of multi-level inverter without common-mode voltage - Google Patents
Modulation method of multi-level inverter without common-mode voltage Download PDFInfo
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- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
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Abstract
The invention provides a modulation method of a multi-level inverter without common-mode voltage, which belongs to the technical field of modulation of multi-level inverters and comprises the steps of decomposing modulation waves, and subtracting every two of the decomposed modulation waves to be equal to the original modulation waves; carrying out one-dimensional space vector modulation on the decomposed modulation wave to obtain an action vector for synthesizing the modulation wave and corresponding vector action time; combining the sawtooth carrier to output the vector with small module value in one carrier period of the positive half period first and output the vector with large module value in the negative half period first to obtain a middle PWM signal; subtracting the middle PWM signals two by two to obtain three-phase PWM signals; and selecting the redundant vectors according to actual requirements of different topologies. The invention eliminates common-mode voltage, eliminates the influence of leakage current on grid-connected current, and improves waveform quality; compared with the traditional SVPWM (space vector pulse width modulation) strategy, the method has the advantages that the two-dimensional simplification is changed into one-dimensional simplification, the sector judgment and the vector action time are both simplified, the trigonometric function operation is not contained, and the calculation amount is small; the versatility for different inverter topologies is strong.
Description
Technical Field
The invention relates to the technical field of modulation of multi-level inverters, in particular to a modulation method of a multi-level inverter without common-mode voltage.
Background
In recent years, photovoltaic power generation is widely concerned by countries in the world due to its cleanness, reproducibility, abundant resources and great development potential. Compared with the traditional photovoltaic grid-connected inverter with the isolation transformer, the non-isolation type photovoltaic grid-connected inverter has the advantages that the size is greatly reduced, the cost is reduced, and the efficiency is improved. However, the photovoltaic cell panel of the non-isolated photovoltaic grid-connected inverter is directly connected with the power grid, so that leakage current is generated, the leakage current can cause the problems of electromagnetic interference, grid-connected current distortion, power loss increase and the like, and even the equipment and personnel safety can be damaged. The multi-level inverter can reduce common-mode voltage dv/dt, reduce output voltage harmonic waves and improve inverter efficiency. If better harmonic performance is desired, the inverter is required to have a greater number of output levels.
The existing multilevel inverter modulation technology is mainly divided into two types, namely space vector modulation (SVPWM) and Sinusoidal Pulse Width Modulation (SPWM), wherein the SVPWM is mature in application to two levels and three levels, when the number of the levels is increased to five levels or above, the number of voltage vectors is greatly increased, the calculation is extremely complicated, and the amplitude of common-mode voltage is increased along with the increase of the number of the levels by the SVPWM. The SPWM is mature in application in a traditional topology with a specific corresponding relation between a carrier and a switching tube, and has low universality aiming at a non-traditional topology, the common-mode voltage of the SPWM is reduced relative to SVPWM, but the voltage on a parasitic capacitor is changed at high frequency due to high output frequency, and a common-mode filtering link is still required to be additionally arranged at a later stage to suppress leakage current.
Therefore, it is necessary to start with a modulation strategy and suppress the common-mode voltage generation source, and a modulation technique of a multi-level inverter without the common-mode voltage is designed, which has strong universality, simple calculation and easy digital realization for different multi-level inverters.
Disclosure of Invention
The invention aims to provide a modulation method of a multi-level inverter without common-mode voltage, which has strong universality, simple calculation and easy digital realization, so as to solve the technical problems in the background technology.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a modulation method of a multi-level inverter without common-mode voltage, which comprises the following steps:
step S110: decomposing the modulated waves, and subtracting two of the decomposed modulated waves from each other to be equal to the original modulated waves;
step S120: carrying out one-dimensional space vector modulation on the decomposed modulation wave to obtain an action vector for synthesizing the modulation wave;
step S130: combining the sawtooth carrier waves to obtain a three-phase PWM signal according to the action vector and the corresponding vector action time;
step S140: and selecting a redundant vector according to the three-phase PWM signal to obtain a driving signal of each power switch tube, thereby realizing output phase modulation of the multi-level inverter.
Preferably, the step S110 specifically includes:
for n-level inverter, three-phase modulated wave uA、uBAnd uCDecomposition into u by transformation matrix1、u2And u3The transformation formula is as follows:
wherein u isAAnd u1-u2Same phase, constant amplitude, uBAnd u2-u3Same phase, constant amplitude, uCAnd u3-u1In phase, equal amplitude.
Preferably, in step S120, the performing one-dimensional space vector modulation on the decomposed modulated wave to obtain an action vector for synthesizing the modulated wave specifically includes:
will u1、u2And u3Carry out n0One-dimensional space vector modulation of electrical levels, n0A voltage vector divides a one-dimensional space into n0-1 modulation sector, u1、u2And u3Are converted to respectively obtain u'1、u′2And u'3Prepared of u'1、u′2And u'3All fall within the first modulation sector, the transformation rule is as follows:
wherein E represents a level step of the multilevel inverter, x is an integer part of an x rounding-down function, and x' is an integer part of an x rounding-up function.
Preferably, the step S130 specifically includes:
judging the modulation sector and selecting a vector participating in synthesizing voltage;
u's'1、u′2And u'3Comparing with sawtooth carrier to obtain action time of each voltage vector and obtain the corresponding u1、u2And u3Intermediate signal PWM of1、PWM2And PWM3；
Intermediate signal PWM1And PWM2Subtracting to obtain PWM signal PWM of A phaseA，PWM2And PWM3Subtracting to obtain the PWM signal PWM of B phaseB，PWM3And PWM1Subtracting to obtain PWM signal PWM of C phaseC。
Preferably, said n0Is the smallest odd number larger than n/2.
Preferably, said n0The-1 modulation sectors are respectively 0 to E, 0 to-E, E to 2E,
Preferably, the judging the modulation sector and the selecting the vector participating in the synthesis of the voltage specifically includes:
selecting a large level vector and a small level vector of the modulation sector needing to be judged as action vectors, and if u is the action vector1Within 0-E, the large level vector is E, and the small level vector is 0; if u1Within 0-E, the large level vector is-E and the small level vector is 0.
Preferably, the sawtooth carrier wave has a frequency fcSaw tooth carriers with uniformly increasing amplitudes from 0 to E.
Preferably, the intermediate signal PWM1、PWM2And PWM3The obtaining specifically comprises:
if u1Greater than 0, using T1 0When compared to a sawtooth carrier, T1 0When greater than the carrier, output u1Small level vector of modulation sector as intermediate signal PWM1(ii) a When T is1 0When it is smaller than the carrier, then output u1Large level vector of modulation sector as intermediate signal PWM1(ii) a If u1Less than 0, using T1 1When compared to a sawtooth carrier, T1 1When greater than the carrier, output u1Large level vector of modulation sector as intermediate signal PWM1(ii) a When T is1 1When it is smaller than the carrier, then output u1Small level vector of modulation sector as intermediate signal PWM1；
Wherein the content of the first and second substances,
if u2Greater than 0, using T2 0When compared to a sawtooth carrier, T2 0When greater than the carrier, output u2Small level vector of modulation sector as intermediate signal PWM2(ii) a When T is2 0When it is smaller than the carrier, then output u2Large level vector of modulation sector as intermediate signal PWM2(ii) a If u2Less than 0, using T2 1When compared to a sawtooth carrier, T2 1When greater than the carrier, output u2Large level vector of modulation sector as intermediate signal PWM2(ii) a When T is2 1When it is smaller than the carrier, then output u2Small level vector of modulation sector as intermediate signal PWM2；
Wherein the content of the first and second substances,
if u3Greater than 0, using T3 0When compared to a sawtooth carrier, T3 0When the carrier wave is larger than the carrier wave,output u3Small level vector of modulation sector as intermediate signal PWM3(ii) a When T is3 0When it is smaller than the carrier, then output u3Large level vector of modulation sector as intermediate signal PWM3(ii) a If u3Less than 0, using T3 1When compared to a sawtooth carrier, T3 1When greater than the carrier, output u3Large level vector of modulation sector as intermediate signal PWM3(ii) a When T is3 1When it is smaller than the carrier, then output u3Small level vector of modulation sector as intermediate signal PWM3；
Wherein the content of the first and second substances,
the PWMA、PWMBAnd PWMCThe sum of the additions is 0, i.e. the common mode voltage is 0.
The invention has the beneficial effects that: the common-mode voltage is completely eliminated from the source, the leakage current problem is solved from the source, and the post-stage common-mode filtering link is omitted; the influence of leakage current on grid-connected current is eliminated, and the waveform quality is improved; compared with the traditional SVPWM (space vector pulse width modulation) strategy, the method has the advantages that the two-dimensional simplification is changed into one-dimensional simplification, the sector judgment and the vector action time are both simplified, the trigonometric function operation is not contained, and the calculated amount is greatly reduced; the versatility for different inverter topologies is strong.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a flowchart of a modulation method of a common-mode voltage-free multi-level inverter according to an embodiment of the present invention.
Fig. 2 is a topology structure diagram of a seven-level inverter based on a switched capacitor according to an embodiment of the present invention.
Fig. 3 is a one-dimensional space vector diagram of the single-phase five-level inverter according to the embodiment of the invention.
Fig. 4 is a waveform diagram of the modulation waveform and the carrier wave after being turned over according to the embodiment of the present invention.
Fig. 5 is a waveform diagram of an intermediate signal PWM simulation according to an embodiment of the present invention.
Fig. 6 is a three-phase output PWM simulation waveform diagram according to an embodiment of the present invention.
Fig. 7 is a diagram of a-phase PWM fourier analysis according to an embodiment of the present invention.
FIG. 8 is a waveform diagram illustrating voltage simulation of a clamp capacitor according to an embodiment of the present invention.
FIG. 9 is a waveform diagram of the common mode voltage simulation according to the embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or modules having the same or similar functionality throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or modules, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, modules, and/or groups thereof.
It should be noted that, unless otherwise explicitly stated or limited, the terms "connected" and "fixed" and the like in the embodiments of the present invention are to be understood in a broad sense and may be fixedly connected, detachably connected, or integrated, mechanically connected, electrically connected, directly connected, indirectly connected through an intermediate medium, connected between two elements, or in an interaction relationship between two elements, unless explicitly stated or limited. Specific meanings of the above terms in the embodiments of the present invention can be understood by those skilled in the art according to specific situations.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
For the convenience of understanding of the embodiments of the present invention, the following description will be further explained by taking specific embodiments as examples with reference to the drawings, and the embodiments are not to be construed as limiting the embodiments of the present invention.
It will be understood by those of ordinary skill in the art that the figures are merely schematic representations of one embodiment and that the elements or devices in the figures are not necessarily required to practice the present invention.
Example one
As shown in fig. 1, an embodiment of the present invention provides a modulation method for a multi-level inverter without a common-mode voltage, including the following steps:
for an n-level inverter, the level step is E, and the DC side voltage is VdcThe technical scheme adopted by the invention comprises the following steps:
step (1) of modulating a three-phase modulated wave u shown in formula (1)A、uB、uCDecomposed into u represented by formula (2)1、u2、u3After decomposition, uAAnd u1-u2Same phase, constant amplitude, uBAnd u2-u3Same phase, constant amplitude, uCAnd u3-u1In-phase, constant amplitude, transformation matrix is shown in formula (3).
uA＝Msin(ωt)
In the formula, M is the modulation wave amplitude value which can be set artificially and does not exceed half of the voltage on the direct current side.
Step (2), u1、u2、u3The following multilevel inverter modulation was performed, respectively. If the inverter is a 3-level inverter, u1、u2、u3Performing 2-level modulation; if the inverter is a 5-level inverter, u1、u2、u3Carrying out 3-level modulation; if the inverter is a 7-level inverter, u1、u2、u3Carrying out 5-level modulation; if the inverter is a 9-level inverter, u1、u2、u3Carrying out 5-level modulation; by analogy, if n level inverter, u1、u2、u3Carry out n0Level modulation, n0Is the smallest odd number larger than n/2.
Will u1、u2、u3Carry out n0One-dimensional space vector modulation of electrical levels, n0The voltage vectors divide one-dimensional space into 0-E, 0-E, E-2E, and-E-2E0-1) sectors, u1、u2、u3Is overturned and folded to obtain u'1、u′2、u′3All of them fall into 0 to E sectors to reduce the number of carriers. u. of1To u'1The rule is shown in formula (4), u2、u3Is transformed with u1And (4) transforming.
Where x is the integer part of the x floor function and x' is the integer part of the x floor function.
Judgment u1Selecting the large level vector and the small level vector of the sector as action vectors if u is in the sector1In the sectors from 0 to E, the large level vector is E, and the small level vector is 0; if u1In sectors 0 to-E, the large level vector is-E and the small level vector is 0.
Using a frequency of fcSawtooth carrier with uniformly increasing amplitude from 0 to E, frequency fcCan be set manually.
If u1Greater than 0, using T1 0When compared to a sawtooth carrier, T1 0When greater than the carrier, output u1Small level vector of modulation sector as intermediate signal PWM1(ii) a When T is1 0When it is smaller than the carrier, then output u1Large level vector of modulation sector as intermediate signal PWM1(ii) a If u1Less than 0, using T1 1When compared to a sawtooth carrier, T1 1When greater than the carrier, output u1Large level vector of modulation sector as intermediate signal PWM1(ii) a When T is1 1When it is smaller than the carrier, then output u1Small level vector of modulation sector as intermediate signal PWM1；
Wherein the content of the first and second substances,
if u2Greater than 0, using T2 0When compared to a sawtooth carrier, T2 0When greater than the carrier, output u2Small level vector of modulation sector as intermediate signal PWM2(ii) a When T is2 0When it is smaller than the carrier, then output u2Large level vector of modulation sector as intermediate signal PWM2(ii) a If u2Less than 0, using T2 1When compared to a sawtooth carrier, T2 1When greater than the carrier, output u2Large level vector of modulation sector as intermediate signal PWM2(ii) a When T is2 1When it is smaller than the carrier, then output u2Small level vector of modulation sector as intermediate signal PWM2；
Wherein the content of the first and second substances,
if u3Greater than 0, using T 30 is compared with the sawtooth carrier when T3 0When greater than the carrier, output u3Small level vector of modulation sector as intermediate signal PWM3(ii) a When T is3 0When it is smaller than the carrier, then output u3Large level vector of modulation sector as intermediate signal PWM3(ii) a If u3Less than 0, using T3 1When compared to a sawtooth carrier, T3 1When greater than the carrier, output u3Large level vector of modulation sector as intermediate signal PWM3(ii) a When T is3 1When it is smaller than the carrier, then output u3Small level vector of modulation sector as intermediate signal PWM3；
Wherein the content of the first and second substances,
step (3) of PWM (pulse-Width modulation) the intermediate signal obtained in the step (2)1And PWM2Subtracting to obtain PWM of A phaseASignal, PWM2And PWM3Subtracting to obtain B-phase PWMBSignal, PWM3And PWM1Subtracting to obtain C-phase PWMCA signal.
And (4) obtaining PWM (pulse width modulation) through the step (3)A、PWMB、PWMCAnd then selecting redundant vectors according to the actual requirements of different topologies to obtain control signals of each switching tube, because of PWMA、PWMB、PWMCThe sum is 0, i.e. the common mode voltage is 0.
Example two
In the second embodiment of the present invention, a seven-level inverter based on a switched capacitor with complicated charging and discharging conditions is used as an example topology, as shown in fig. 2, the seven-level inverter is an a-phase topology structure diagram, the B-phase and the C-phase are the same as the a-phase, A, B, C three-phase P, O, N is connected together, a level step E is equal to 62.5V, and a dc-side voltage is VdcEqual to 375V.
A. B, C three-phase modulated wave uA、uB、uCAs shown in formula (1), u is obtained by matrix transformation of formula (2)1、u2、u3。
uA＝180sin(ωt)
u1、u2、u3Five-level one-dimensional space vector modulation is required, and 5 voltage vectors divide the one-dimensional space into four sectors of 0-E, 0-E, E-2E and-E-2E, as shown in figure 3. With a period of 50s and an amplitude of 0 to E increasing uniformlyThe sawtooth carrier of (1). u. of1、u2、u3Is overturned and folded to obtain u'1、u′2、u′3All of them fall into 0 to E sectors to reduce the number of carriers. u. of1The transformation rule is shown as formula (3), the transformed waveform and carrier are shown as figure 4, u2、u3Is transformed with u1The transformation rule of (1).
Judgment u1Selecting the large level vector and the small level vector of the sector as action vectors if u is in the sector1In the sectors from 0 to E, the large level vector is E, and the small level vector is 0; if u1In the E-2E sector, the large level vector is 2E, and the small level vector is E; if u1In the sector from 0 to E, the large level vector is E, and the small level vector is 0; if u1In sectors-E to-2E, the large level vector is-2E, and the small level vector is-E.
A sawtooth carrier with a frequency of 10kHz and an amplitude of 0 to 62.5 is used, if u is uniformly increased1Greater than 0, using T1 0Comparing with carrier wave when T1 0Outputting the small level vector of the sector when the vector is larger than the carrier wave, and outputting the large level vector of the sector when the vector is smaller than the carrier wave; if u1Less than 0, using T1 1Comparing with carrier wave when T1 1And outputting the large level vector of the sector when the large level vector is larger than the carrier wave, and outputting the small level vector of the sector when the small level vector is smaller than the carrier wave. Thus obtaining u1Modulated intermediate PWM1Signal u2、u3And obtaining intermediate PWM by using same modulation method2、PWM3A signal. T is1 1And T1 0The formula (4) is shown in the following formula. Resulting intermediate PWM1、PWM2、PWM3The signals are shown in FIG. 5, where (a) denotes the intermediate signal PWM1Is shown, (b) represents the intermediate signal PWM2Waveform diagram of (c) represents the intermediate signal PWM3A waveform diagram of (a).
PWM the obtained intermediate signal1And PWM2Subtracting to obtain PWM of A phaseASignal, PWM2And PWM3Subtracting to obtain B-phase PWMBSignal, PWM3And PWM1Subtracting to obtain C-phase PWMCA signal.
The voltage of the clamping capacitors C3 and C4 in the figure (2) needs to be maintained at 62.5V due to the seven-level inverter topology based on the switched capacitor. According to the obtained PWMA、PWMB、PWMCAnd selecting a proper redundant vector for each voltage vector to maintain the voltage balance of the clamping capacitor. The switch tubes S1 and S2, S3 and S4, S5 and S6, S7 and S8, S9 and S11 and S10 are in complementary conducting relationship, and the switch tubes S1 and S3, S2 and S4 are turned on and off simultaneously. The voltage combination and the charge/discharge of the clamp capacitor are shown in table 1.
TABLE 1 switching states and capacitor charging and discharging conditions corresponding to different output levels
Hysteresis control is adopted for the voltage of the clamping capacitor, and the control period is 100 s. For example, when PWMAWhen the output level is E, if the voltage of the clamping capacitor is greater than 62.5V, the vector charged by the clamping capacitor is adopted to turn on signals of the switching tubes S1 and S5, turn off signals of the switching tubes S7 and S9, and the other switching tubes correspondingly act; when the voltage of the clamping capacitor is less than 62.5V, the vector of the discharge of the clamping capacitor is adopted to turn on signals for the switching tubes S1, S7 and S9, turn off the signals for the switching tubes S7, and the other tubes act correspondingly, so that the voltage balance of the clamping capacitor is realized. A. The B, C-phase PWM waveform is shown in FIG. 6, in which (a) represents the signal PWMAIs shown as (b) shows the signal PWMBThe waveform of (c) shows a signalPWMCA waveform diagram of (a). The A-phase PWM Fourier analysis is shown in FIG. 7, B, C is for the same A-phase, the clamp capacitor voltage is shown in FIG. 8, and the common mode voltage is shown in FIG. 9.
In conclusion, the invention can be applied to a seven-level inverter based on a switched capacitor type, meets the voltage balance of a clamping capacitor, performs corresponding redundant vector selection according to other different topological requirements in the step (4), is easy to popularize, and has good harmonic performance of output voltage and no common-mode voltage.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (5)
1. A modulation method of a multi-level inverter without common mode voltage is characterized by comprising the following flow steps:
step S110: decomposing the modulated waves, and subtracting two of the decomposed modulated waves from each other to be equal to the original modulated waves; for n-level inverter, three-phase modulated wave uA、uBAnd uCDecomposition into u by transformation matrix1、u2And u3The transformation formula is as follows:
wherein u isAAnd u1-u2Same phase, constant amplitude, uBAnd u2-u3Same phase, constant amplitude, uCAnd u3-u1Same phase and same amplitude;
step S120: carrying out one-dimensional space vector modulation on the decomposed modulation wave to obtain an action vector for synthesizing the modulation wave; will u1、u2And u3Carry out n0One-dimensional space vector modulation of electrical levels, n0Voltage vectorDividing a one-dimensional space into n0-1 modulation sector, u1、u2And u3Are converted to respectively obtain u'1、u′2And u'3Prepared of u'1、u′2And u'3All fall within the first modulation sector, the transformation rule is as follows:
wherein u is1For modulating wave, E represents level step of multi-level inverter, and x represents u1The result of dividing the magnitude of (d) by E,
the integer part of the function is rounded down for x,
is the integer part of the rounding function in the x direction, n0Is a minimum odd number greater than n/2;
step S130: combining the sawtooth carrier waves to obtain a three-phase PWM signal according to the action vector and the corresponding vector action time; judging the modulation sector and selecting a vector participating in synthesizing voltage;
u's'1、u′2And u'3Comparing with sawtooth carrier to obtain action time of each voltage vector and obtain the corresponding u1、u2And u3Intermediate signal PWM of1、PWM2And PWM3；
Intermediate signal PWM1And PWM2Subtracting to obtain PWM signal PWM of A phaseA，PWM2And PWM3Subtracting to obtain the PWM signal PWM of B phaseB，PWM3And PWM1Subtracting to obtain PWM signal PWM of C phaseC；
Step S140: and selecting a redundant vector according to the three-phase PWM signal to obtain a driving signal of each power switch tube, thereby realizing output phase modulation of the multi-level inverter.
2. The method of claim 1, wherein:
n is0The-1 modulation sectors are respectively 0 to E, 0 to-E, E to 2E,
3. The method of claim 2, wherein said determining the modulation sector and selecting the participating composite voltage vector specifically comprises:
selecting a large level vector and a small level vector of the modulation sector needing to be judged as action vectors, and if u is the action vector1Within 0-E, the large level vector is E, and the small level vector is 0; if u1Within 0-E, the large level vector is-E and the small level vector is 0.
4. The method of claim 3, wherein the sawtooth carrier is at a frequency fcSaw tooth carriers with uniformly increasing amplitudes from 0 to E.
5. Method according to claim 4, characterized in that the intermediate signal PWM1、PWM2And PWM3The obtaining specifically comprises:
if u1Greater than 0, using T1 0When compared to a sawtooth carrier, T1 0When greater than the carrier, output u1Small level vector of modulation sector as intermediate signal PWM1(ii) a When T is1 0When it is smaller than the carrier, then output u1Large level vector of modulation sector as intermediate signal PWM1(ii) a If u1Less than 0, using T1 1When compared to a sawtooth carrier, T1 1When greater than the carrier, output u1Large level vector of modulation sector as intermediate signal PWM1(ii) a When T is1 1When it is smaller than the carrier, then output u1Modulation ofSmall level vector of sector as intermediate signal PWM1；
Wherein the content of the first and second substances,
if u2Greater than 0, using T2 0When compared to a sawtooth carrier, T2 0When greater than the carrier, output u2Small level vector of modulation sector as intermediate signal PWM2(ii) a When T is2 0When it is smaller than the carrier, then output u2Large level vector of modulation sector as intermediate signal PWM2(ii) a If u2Less than 0, using T2 1When compared to a sawtooth carrier, T2 1When greater than the carrier, output u2Large level vector of modulation sector as intermediate signal PWM2(ii) a When T is2 1When it is smaller than the carrier, then output u2Small level vector of modulation sector as intermediate signal PWM2；
Wherein the content of the first and second substances,
if u3Greater than 0, using T3 0When compared to a sawtooth carrier, T3 0When greater than the carrier, output u3Small level vector of modulation sector as intermediate signal PWM3(ii) a When T is3 0When it is smaller than the carrier, then output u3Large level vector of modulation sector as intermediate signal PWM3(ii) a If u3Less than 0, using T3 1When compared to a sawtooth carrier, T3 1When greater than the carrier, output u3Large level vector of modulation sector as intermediate signal PWM3(ii) a When T is3 1When it is smaller than the carrier, then output u3Small level vector of modulation sector as intermediate signal PWM3；
Wherein the content of the first and second substances,
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