CN108683347B - Seven-level inverter topological structure based on voltage doubling circuit and seven-level inverter - Google Patents

Seven-level inverter topological structure based on voltage doubling circuit and seven-level inverter Download PDF

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CN108683347B
CN108683347B CN201810343131.8A CN201810343131A CN108683347B CN 108683347 B CN108683347 B CN 108683347B CN 201810343131 A CN201810343131 A CN 201810343131A CN 108683347 B CN108683347 B CN 108683347B
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switching tube
capacitor
tube
switch tube
switch
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CN108683347A (en
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付永升
巩兆伟
黄海波
黄洋
马超
雷秉山
胡文婷
刘敏
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Xian Technological University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
    • H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

Abstract

The invention discloses a seven-level inverter topological structure based on a voltage doubling circuit, which comprises a Boost main circuit, a full-bridge single-phase inverter main circuit and an auxiliary circuit(ii) a The Boost main circuit comprises an inductor L1Diode D1A first switch tube S1The full-bridge single-phase inverter main circuit comprises a tenth switching tube S10The eleventh switch tube S11The twelfth switch tube S12Thirteenth switch tube S13(ii) a A seven-level inverter is also disclosed. The seven-level inverter is realized by effectively adjusting the bus by controlling the switching-on of the switching tube. Compared with the traditional seven-level inverter, the topological structure uses fewer switching tubes, the voltage gain can reach 30 times of steady-state gain, and the seven-level inverter is suitable for inverters with low-voltage (photovoltaic, super-capacitor and the like) input; the voltage stress of part of the switch tubes is reduced, the switching loss of the switch tubes is reduced, and the system reliability is improved.

Description

Seven-level inverter topological structure based on voltage doubling circuit and seven-level inverter
Technical Field
The invention belongs to the technical field of power electronic converters, and particularly relates to a seven-level inverter topological structure based on a voltage doubling circuit and a seven-level inverter.
Background
As voltage and capacity requirements of practical systems increase, conventional converters have been unable to meet practical requirements. If a two-level converter is used in high-voltage high-capacity situations, this can occur: the voltage and current distortion of the converter is serious, the voltage conversion rate is overlarge due to the increase of the switching times, the loss of a switching tube is increased due to the surge voltage, and the system efficiency is reduced.
The multi-level converter has the advantages of easy realization of high voltage and large capacity, low voltage borne by a switching tube, more output levels, small harmonic wave of output voltage and the like. The multilevel inverter topological structure mainly comprises a diode clamping type, a flying capacitor type and a cascade type. The number of diodes of the diode-clamped multilevel inverter increases sharply with the increase of the number of levels; the midpoint voltage of the direct current bus with more than three levels is difficult to balance; the voltage born by each clamping diode is not uniform under the influence of the dispersion and the stray parameters of the clamping diodes. The number of capacitors of the flying capacitor type multilevel inverter increases sharply with an increase in the number of levels. The cascade multilevel inverter needs an independent direct current power supply or adopts a multi-winding phase-shifting transformer, so that the size is large and the cost is high.
Disclosure of Invention
In view of the above, the present invention provides a seven-level inverter topology based on a voltage doubling circuit and a seven-level inverter.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
the embodiment of the invention provides a seven-level inverter topological structure based on a voltage doubling circuit, which comprises a Boost main circuit, a full-bridge single-phase inverter main circuit and an auxiliary circuit; the Boost main circuit comprises an inductor L1Diode D1A first switch tube S1The full-bridge single-phase inverter main circuit comprises a tenth switching tube S10The eleventh switch tube S11The twelfth switch tube S12Thirteenth switch tube S13The auxiliary circuit comprises a second switch tube S2A third switch tube S3And a fourth switching tube S4The fifth switch tube S5The sixth switching tube S6Seventh switching tube S7The eighth switching tube S8The ninth switch tube S9A first capacitor C1A second capacitor C2A third capacitor C3A fourth capacitor C4The positive pole of the bus voltage passes through the inductor L in sequence1Diode D1The fifth switch tube S5Seventh switching tube S7The eighth switching tube S8The twelfth switch tube S12Thirteenth switch tube S13Connected to the negative pole of the bus voltage, and the first capacitor C1Connected in parallel between the positive and negative poles of the bus voltage and terminating at the positive pole of the bus voltage and an inductor L1The second switch tube S connected in series2A second capacitor C2Connected in parallel between the positive and negative poles of the bus voltage and terminated by a diode D1And a fifth switching tube S5In series with a third capacitor C3And a fourth switching tube S4Connected in parallel between the positive and negative poles of the bus voltage and one end connected to the fifth switching tube S5And a seventh switching tube S7In series with a fourth capacitor C4The ninth switch tube S9Connected in parallel between the positive and negative poles of the bus voltage and terminating in an eighth switching tube S8And a twelfth switching tube S12The tenth switch tube S connected in series10The eleventh switch tube S11Connected in parallel between the positive and negative poles of the bus voltage and terminating in an eighth switching tube S8And a twelfth switching tube S12To (c) to (d); the third switch tube S3Are respectively connected with a second switch tube S2And a second capacitor C2And a third capacitance C3And a fourth switching tube S4In the sixth switching tube S6Is connected to a fifth switching tube S5And a seventh switching tube S7Another end is connected to a fourth capacitor C4And a ninth switching tube S9To (c) to (d); the voltage output end is connected with a tenth switch tube S10And an eleventh switching tube S11And a twelfth switching tube S12And a thirteenth switching tube S13To (c) to (d); the diode D1A second switch tube S2The fifth switch tube S5The common junction is also directly connected with an eighth switching tube S through one path8A fourth capacitor C4And (4) a common joint.
In the foregoing solution, the first operating state of the seven-level inverter topology based on the voltage doubling circuit is as follows: the first switch tube S1On, bus voltage VinTo the inductance L1Storing energy; tenth switching tube S10And a twelfth switching tube S12Conducting and outputting voltage UabIs 0; the second capacitor C2A third capacitor C3A fourth capacitor C4The energy remains unchanged;
the second working state: first switch tube S1Off, bus voltage VinAnd an inductance L1Meanwhile, energy is provided for the full-bridge single-phase inverter main circuit; the second switch tube S2And a fourth switching tube S4The fifth switch tube S5Seventh switching tube S7The eighth switching tube S8The ninth switch tube S9Conducting; the second capacitor C2A third capacitor C3A fourth capacitor C4Connected in parallel and both ends of which are charged to VboostWhen the bus voltage is equal to Vboost(ii) a The tenth switching tube S10And a thirteenth switching tube S13Is conducted and has an output voltage of Vboost；
The third working state: the third switch tube S3The fifth switch tube S5Seventh switching tube S7The eighth switching tube S8The tenth switch tube S10Conducting; the second capacitor C2A third capacitor C3A fourth capacitor C connected in series4Disconnected and the bus voltage is equal to 2Vboost(ii) a The tenth switching tube S10And a thirteenth switching tube S13On and output voltage of 2Vboost；
The fourth working state: the third switch tube S3The fifth switch tube S5The sixth switching tube S6Conducting; the second capacitor C2A third capacitor C3A fourth capacitor C4In series, the bus voltage being equal to 3Vboost(ii) a The tenth switching tube S10And a thirteenth switching tube S13Conducting and the output voltage is 3Vboost。
The fifth working state: the first switch tube S1On, bus voltage VinTo the inductance L1Storing energy; the eleventh switch tube S11And a thirteenth switching tube S13Conducting and outputting voltage UabIs 0; the second capacitor C2A third capacitor C3A fourth capacitor C4The energy remains unchanged;
the sixth working state: the first switch tube S1Off, bus voltage VinAnd an inductance L1Meanwhile, energy is provided for the full-bridge single-phase inverter main circuit; the second switch tube S2And a fourth switching tube S4The fifth switch tube S5Seventh switching tube S7The eighth switching tube S8The ninth switch tube S9And conducting. The second capacitor C2A third capacitor C3A fourth capacitor C4Connected in parallel and both ends of which are charged to VboostWhen the bus voltage is equal to Vboost. Switch S11And S12Is conducted and has an output voltage of-Vboost；
The seventh working state: the third switch tube S3The fifth switch tube S5Seventh switching tube S7The eighth switching tube S8The tenth switch tube S10And conducting. The second capacitor C2A third capacitor C3A fourth capacitor C connected in series4Disconnected and the bus voltage is equal to 2Vboost(ii) a The eleventh switch tube S11And a twelfth switching tube S12Is conducted and the output voltage is-2Vboost；
The eighth operating state: the third switch tube S3The fifth switch tube S5Seventh switching tube S7The eighth switching tube S8The tenth switch tube S10And conducting. The second capacitor C2A third capacitor C3A fourth capacitor C4In series, the bus voltage being equal to 3Vboost(ii) a The eleventh switch tube S11And a twelfth switching tube S12Is conducted and the output voltage is-3Vboost。
In the above scheme, the first operating state and the fifth operating state represent a state when the output is 0, the second operating state and the sixth operating state represent a state when the output is ± 1, the third operating state and the eighth operating state represent a state when the output is ± 2, and the fourth operating state and the seventh operating state represent a state when the output is ± 3, which together form a power frequency alternating current cycle.
The embodiment of the present invention further provides a seven-level inverter, which includes a dc power supply, and further includes: according to the seven-level inverter topology structure based on the voltage doubling circuit in any one of the above schemes, the positive level and the negative level of the direct-current power supply are respectively connected with the positive pole and the negative pole of the bus voltage.
In the above scheme, the method further comprises: and the controller generates trigger pulses to control the on-off of each switching tube in the seven-level inverter topological structure, and different working states of the seven-level inverter topological structure are realized through the combination of the on-off of different switching tubes.
In the above scheme, the inverter comprises a plurality of seven-level inverter topological structures, and the seven-level inverter topological structure circuits are combined to form a multiphase inverter.
Compared with the prior art, the invention has the beneficial effects that:
the seven-level inverter is realized by effectively adjusting the bus by controlling the switching-on of the switching tube. Compared with the traditional seven-level inverter, the topological structure uses fewer switching tubes, the voltage gain can reach 30 times of steady-state gain, and the seven-level inverter is suitable for inverters with low-voltage (photovoltaic, super-capacitor and the like) input; the voltage stress of part of the switch tubes is reduced, the switching loss of the switch tubes is reduced, and the system reliability is improved.
Drawings
Fig. 1 is a schematic diagram of a seven-level inverter topology based on a voltage doubling circuit according to an embodiment of the present invention;
fig. 2 is a control schematic diagram of a seven-level inverter topology based on a voltage doubling circuit according to an embodiment of the present invention;
fig. 3 is a waveform diagram of an output waveform of a full-bridge single-phase inverter main circuit in a seven-level inverter topology based on a voltage doubling circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a first operating state of a seven-level inverter topology based on a voltage doubling circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a second operating state of a seven-level inverter topology based on a voltage doubling circuit according to an embodiment of the present invention;
fig. 6 is a schematic diagram illustrating a third operating state of a seven-level inverter topology based on a voltage doubling circuit according to an embodiment of the present invention;
fig. 7 is a schematic diagram illustrating a fourth operating state of a seven-level inverter topology based on a voltage doubling circuit according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a fifth operating state of a seven-level inverter topology based on a voltage doubling circuit according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a sixth operating state of a seven-level inverter topology based on a voltage doubling circuit according to an embodiment of the present invention;
fig. 10 is a schematic diagram illustrating a seventh operating state of a seven-level inverter topology based on a voltage doubling circuit according to an embodiment of the present invention;
fig. 11 is a schematic diagram illustrating an eighth operating state of a seven-level inverter topology based on a voltage doubling circuit according to an embodiment of the present invention;
FIG. 12 is a logic diagram for PWM generation of the main switching tube;
FIG. 13 is a simulation waveform of PWM signals of each switching tube of the logic circuit;
fig. 14 shows the simulation result.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The embodiment of the invention provides a seven-level inverter topological structure based on a voltage doubling circuit, which comprises a Boost main circuit, a full-bridge single-phase inverter main circuit and an auxiliary circuit, wherein the Boost main circuit is connected with the full-bridge single-phase inverter main circuit; the Boost main circuit comprises an inductor L1Diode D1A first switch tube S1The full-bridge single-phase inverter main circuit comprises a tenth switching tube S10The eleventh switch tube S11The twelfth switch tube S12Thirteenth switch tube S13The auxiliary circuit comprises a second switch tube S2A third switch tube S3And a fourth switching tube S4The fifth switch tube S5The sixth switching tube S6Seventh switching tube S7The eighth switching tube S8The ninth switch tube S9A first capacitor C1A second capacitor C2A third capacitor C3A fourth capacitor C4The positive pole of the bus voltage passes through the inductor L in sequence1Diode D1The fifth switch tube S5Seventh switching tube S7The eighth switching tube S8The twelfth switch tube S12Thirteenth switch tube S13Connected to the negative pole of the bus voltage, and the first capacitor C1Connected in parallel between the positive and negative poles of the bus voltage and terminating at the positive pole of the bus voltage and an inductor L1The second switch tube S connected in series2A second capacitor C2Connected in parallel between the positive and negative poles of the bus voltage and terminated by a diode D1And a fifth switching tube S5In series with a third capacitor C3And a fourth switching tube S4Connected in parallel between the positive and negative poles of the bus voltage and one end connected to the fifth switching tube S5And a seventh switching tube S7In series with a fourth capacitor C4The ninth switch tube S9Connected in parallel between the positive and negative poles of the bus voltage and terminating in an eighth switching tube S8And a twelfth switching tube S12The tenth switch tube S connected in series10The eleventh switch tube S11Connected in parallel between the positive and negative poles of the bus voltage and terminating in an eighth switching tube S8And a twelfth switching tube S12To (c) to (d); the third switch tube S3Are respectively connected with a second switch tube S2And a second capacitor C2And a third capacitance C3And a fourth switching tube S4In the sixth switching tube S6Is connected to a fifth switching tube S5And a seventh switching tube S7Another end is connected to a fourth capacitor C4And a ninth switching tube S9To (c) to (d); the voltage output end is connected with the tenth switch tubeS10And an eleventh switching tube S11And a twelfth switching tube S12And a thirteenth switching tube S13To (c) to (d); the diode D1A second switch tube S2The fifth switch tube S5The common junction is also directly connected with an eighth switching tube S through one path8A fourth capacitor C4And (4) a common joint.
The output voltage is determined by the modulation ratio Ma of the system when the system is in a steady state. The output voltage Vab has seven operating states: 3Vboost t、2Vboost、Vboost、0、-3Vboost t、-2Vboost、-Vboost. Voltage VboostIs the output of the front-end Boost circuit. Wherein V _ Boost ═ V _ in 1/(1-D), D is the Boost circuit duty cycle; therefore, the maximum output voltage of the full-bridge inverter is 3 x (1-D) times of the input direct current voltage, 1>D>0。
The output voltage of the inverter can be directly output by a switching tube S in a Boost circuit as shown in FIG. 11Is determined. It is assumed here that the SPWM modulation ratio of the inverter is MaThen the inverter outputs a voltage Vout-maxThis can be derived from equation 1.
Figure BDA0001631095990000061
Thus at MaWhen the output voltage of the inverter is constant, the maximum value of the output voltage of the inverter can be directly completed by adjusting the duty ratio of the Boost circuit. The system control method is as shown in fig. 2.
The relationship between the switching state and the output voltage of the switching tube is shown in table 1, wherein the Boost voltage circuit can work independently.
TABLE 1 relationship table of switch state and output voltage
Figure BDA0001631095990000071
As shown in table 1: the seven-level inverter of the system is completed by the alternate transformation of seven states, and the output waveform of an H bridge (namely a full-bridge single-phase inverter main circuit) is shown in figure 3.
As shown in fig. 3: when the working state of the positive half-cycle switching tube is ABBA, the output voltage grade of the H bridge is +1, when the working state is BCCB, the output voltage grade of the H bridge is +2, and when the working state is CDCD, the output voltage grade of the H bridge is + 3. When the output voltage level is-1, -2, -3 in the negative half cycle, the working states of the switching tube are EFFE, FGGF and GHGH respectively. The output of the filter circuit is processed by an LC filter circuit to obtain complete sine alternating current.
The different level states of the invention are mainly composed of a switch tube S2～S9And a capacitor C2、C3And C4Completing the process; the function of changing the bus voltage is realized by changing the series-parallel connection structure of the capacitor through changing the on state of the switch tube. Fig. 4 shows the operation principle of the circuit in seven states. The first working state and the fifth working state represent the state when the output is 0, the second working state and the sixth working state represent the state when the output is +/-1, the third working state and the eighth working state represent the state when the output is +/-2, and the fourth working state and the seventh working state represent the state when the output is +/-3, so that a power frequency alternating current period is formed together.
As shown in fig. 4, a first operation state of the seven-level inverter topology based on the voltage doubling circuit is as follows: the first switch tube S1On, bus voltage VinTo the inductance L1Storing energy; tenth switching tube S10And a twelfth switching tube S12Conducting and outputting voltage UabIs 0; the second capacitor C2A third capacitor C3A fourth capacitor C4The energy remains unchanged;
as shown in fig. 5, the second operating state: first switch tube S1Off, bus voltage VinAnd an inductance L1Meanwhile, energy is provided for the full-bridge single-phase inverter main circuit; the second switch tube S2And a fourth switching tube S4The fifth switch tube S5Seventh switching tube S7The eighth switching tube S8The ninth switch tube S9Conducting; the second capacitor C2A third capacitor C3A fourth capacitor C4Connected in parallel with the voltage at both endsAre all filled up to VboostWhen the bus voltage is equal to Vboost(ii) a The tenth switching tube S10And a thirteenth switching tube S13Is conducted and has an output voltage of Vboost；
As shown in fig. 6, the third operating state: the third switch tube S3The fifth switch tube S5Seventh switching tube S7The eighth switching tube S8The tenth switch tube S10Conducting; the second capacitor C2A third capacitor C3A fourth capacitor C connected in series4Disconnected and the bus voltage is equal to 2Vboost(ii) a The tenth switching tube S10And a thirteenth switching tube S13On and output voltage of 2Vboost；
As shown in fig. 7, the fourth operating state: the third switch tube S3The fifth switch tube S5The sixth switching tube S6Conducting; the second capacitor C2A third capacitor C3A fourth capacitor C4In series, the bus voltage being equal to 3Vboost(ii) a The tenth switching tube S10And a thirteenth switching tube S13Conducting and the output voltage is 3Vboost。
As shown in fig. 8, the fifth operation state: the first switch tube S1On, bus voltage VinTo the inductance L1Storing energy; the eleventh switch tube S11And a thirteenth switching tube S13Conducting and outputting voltage UabIs 0; the second capacitor C2A third capacitor C3A fourth capacitor C4The energy remains unchanged;
as shown in fig. 9, the sixth operating state: the first switch tube S1Off, bus voltage VinAnd an inductance L1Meanwhile, energy is provided for the full-bridge single-phase inverter main circuit; the second switch tube S2And a fourth switching tube S4The fifth switch tube S5Seventh switching tube S7The eighth switching tube S8The ninth switch tube S9And conducting. The second capacitor C2A third capacitor C3A fourth capacitor C4Is connected in parallel withBoth ends of the voltage are fully charged to VboostWhen the bus voltage is equal to Vboost. Switch S11And S12Is conducted and has an output voltage of-Vboost；
As shown in fig. 10, the seventh operating state: the third switch tube S3The fifth switch tube S5Seventh switching tube S7The eighth switching tube S8The tenth switch tube S10And conducting. The second capacitor C2A third capacitor C3A fourth capacitor C connected in series4Disconnected and the bus voltage is equal to 2Vboost(ii) a The eleventh switch tube S11And a twelfth switching tube S12Is conducted and the output voltage is-2Vboost；
As shown in fig. 11, the eighth operating state: the third switch tube S3The fifth switch tube S5Seventh switching tube S7The eighth switching tube S8The tenth switch tube S10And conducting. The second capacitor C2A third capacitor C3A fourth capacitor C4In series, the bus voltage being equal to 3Vboost(ii) a The eleventh switch tube S11And a twelfth switching tube S12Is conducted and the output voltage is-3Vboost。
In order to verify the feasibility of the system, a main circuit simulation model is built by using PSIM (particle swarm optimization), a reasonable logic analysis time sequence is designed according to the working state, and a PWM (pulse-width modulation) generated logic diagram of a main switching tube is shown in FIG. 12.
The high-frequency carrier signal is a triangular wave, and the frequency of the triangular wave directly controls the chopping frequency of the switching tube. The high frequency chopped signal is a square wave identical to the carrier signal with a 50% duty cycle. The simulation waveform of the PWM signal of each switching tube by the above logic circuit is shown in fig. 13.
The main topology shown in fig. 1 has circuit simulation parameters shown in table 2.
TABLE 2 Circuit simulation parameters
Figure BDA0001631095990000091
The simulation results are shown in fig. 14 by designing the circuit parameters shown in table 2. The output voltage of the H bridge is alternately completed by seven states, and the output of the load voltage is smooth through the LC filter circuit.
The voltage oscillation of the end voltages of the capacitors C2, C3 and C4 for voltage doubling is small. While the switching frequency may be increased to reduce the voltage swing across the capacitor, the switching frequency may be increased to reduce the capacitance and inductance, which may reduce the size and thus increase the power density of the system. The voltage stress of the switching tube is shown in table 3.
TABLE 3 switching tube Voltage stress
Figure BDA0001631095990000101
The voltage stress of each switching tube is shown in table 3. Compared with the traditional multi-level inverter, the topological structure reduces the voltage stress of partial switch tubes, so that the switching loss of the multi-level inverter can be effectively reduced, the system loss is reduced, and the stability of the system is improved.
The embodiment of the present invention further provides a seven-level inverter, which includes a dc power supply, and further includes: according to the seven-level inverter topology structure based on the voltage doubling circuit in the scheme, the positive level and the negative level of the direct-current power supply are respectively connected with the positive pole and the negative pole of the bus voltage.
The seven-level inverter further includes: and the controller generates trigger pulses to control the on-off of each switching tube in the seven-level inverter topological structure, and different working states of the seven-level inverter topological structure are realized through the combination of the on-off of different switching tubes.
Further, a plurality of the seven-level inversion topological structures are included, and the seven-level inversion topological structure circuits are combined to form a multi-phase inverter.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims (2)

1. A seven-level inverter topological structure based on a voltage doubling circuit is characterized by comprising a Boost mainThe circuit comprises a full-bridge single-phase inverter main circuit and an auxiliary circuit; the Boost main circuit comprises an inductor L1Diode D1A first switch tube S1The full-bridge single-phase inverter main circuit comprises a tenth switching tube S10The eleventh switch tube S11The twelfth switch tube S12Thirteenth switch tube S13The auxiliary circuit comprises a second switch tube S2A third switch tube S3And a fourth switching tube S4The fifth switch tube S5The sixth switching tube S6Seventh switching tube S7The eighth switching tube S8The ninth switch tube S9A first capacitor C1A second capacitor C2A third capacitor C3A fourth capacitor C4The positive pole of the input voltage passes through an inductor L in sequence1Diode D1The fifth switch tube S5Seventh switching tube S7The eighth switching tube S8The twelfth switch tube S12Thirteenth switch tube S13Connected to the negative pole of the input voltage, and the first capacitor C1Connected in parallel between the positive and negative poles of the input voltage and having one end connected to the positive pole of the input voltage and the inductor L1A second switch tube S2A second capacitor C2One end of the series circuit is connected to a diode D1And a fifth switching tube S5The other end of the switch is connected with the negative pole of the input voltage; third capacitor C3And a fourth switching tube S4One end of the series circuit is connected with the fifth switch tube S5And a seventh switching tube S7The other end of the switch is connected with the negative pole of the input voltage; fourth capacitor C4The ninth switch tube S9One end of the series circuit is connected to the eighth switching tube S8And a twelfth switching tube S12The other end of the switch is connected with the negative pole of the input voltage; tenth switching tube S10The eleventh switch tube S11One end of the series circuit is connected to the eighth switching tube S8And a twelfth switching tube S12The other end of the switch is connected with the negative pole of the input voltage; the third switch tube S3Are respectively connected with a second switch tube S2And a second capacitorC2And a third capacitance C3And a fourth switching tube S4In the sixth switching tube S6Is connected to a fifth switching tube S5And a seventh switching tube S7Another end is connected to a fourth capacitor C4And a ninth switching tube S9To (c) to (d); the voltage output end is connected with a tenth switch tube S10And an eleventh switching tube S11And a twelfth switching tube S12And a thirteenth switching tube S13To (c) to (d); the diode D1A second switch tube S2The fifth switch tube S5The common junction is also directly connected with an eighth switching tube S8A fourth capacitor C4A common junction;
the first working state of the seven-level inverter topology based on the voltage doubling circuit is as follows: the first switch tube S1On, input voltage VinTo the inductance L1Storing energy; tenth switching tube S10And a twelfth switching tube S12Conducting and outputting voltage UabIs 0; the second capacitor C2A third capacitor C3A fourth capacitor C4The energy remains unchanged;
the second working state: first switch tube S1Off, input voltage VinAnd an inductance L1Meanwhile, energy is provided for the full-bridge single-phase inverter main circuit; the second switch tube S2And a fourth switching tube S4The fifth switch tube S5Seventh switching tube S7The eighth switching tube S8The ninth switch tube S9Conducting; the second capacitor C2A third capacitor C3A fourth capacitor C4Parallel connection, both ends of which are charged to Vboost(ii) a The tenth switching tube S10And a thirteenth switching tube S13Is conducted and has an output voltage of Vboost；
The third working state: the third switch tube S3The fifth switch tube S5Seventh switching tube S7The eighth switching tube S8Conducting; the second capacitor C2A third capacitor C3A fourth capacitor C connected in series4Off, bus voltageEqual to 2Vboost(ii) a The tenth switching tube S10And a thirteenth switching tube S13On and output voltage of 2Vboost；
The fourth working state: the third switch tube S3The sixth switching tube S6Conducting; the second capacitor C2A third capacitor C3A fourth capacitor C4Connected in series with an input voltage equal to 3 x Vboost(ii) a The tenth switching tube S10And a thirteenth switching tube S13Conducting and the output voltage is 3Vboost；
The fifth working state: the first switch tube S1On, input voltage VinTo the inductance L1Storing energy; the eleventh switch tube S11And a thirteenth switching tube S13Conducting and outputting voltage UabIs 0; the second capacitor C2A third capacitor C3A fourth capacitor C4The energy remains unchanged;
the sixth working state: the first switch tube S1Off, input voltage VinAnd an inductance L1Meanwhile, energy is provided for the full-bridge single-phase inverter main circuit; the second switch tube S2And a fourth switching tube S4The fifth switch tube S5Seventh switching tube S7The eighth switching tube S8The ninth switch tube S9Conducting; the second capacitor C2A third capacitor C3A fourth capacitor C4Parallel connection, both ends of which are charged to VboostWhen the bus voltage is equal to Vboost(ii) a Switch S11And S12Is conducted and has an output voltage of-Vboost；
The seventh working state: the third switch tube S3The fifth switch tube S5Seventh switching tube S7The eighth switching tube S8Conducting; the second capacitor C2A third capacitor C3A fourth capacitor C connected in series4Disconnected and the bus voltage is equal to 2Vboost(ii) a The eleventh switch tube S11And a twelfth switching tube S12Is conducted and the output voltage is-2Vboost；
The eighth operating state: the third switch tube S3The sixth switching tube S6Conducting; the second capacitor C2A third capacitor C3A fourth capacitor C4Connected in series with an input voltage equal to 3 x Vboost(ii) a The eleventh switch tube S11And a twelfth switching tube S12Is conducted and the output voltage is-3Vboost。
2. The seven-level inverter topology based on voltage doubling circuit according to claim 1, wherein the first and fifth operating states represent a state when the output is 0, the second and sixth operating states represent an output of ± VboostThe time, third and eighth operating states represent an output of ± 2 × VboostThe time, fourth and seventh operating states represent an output of ± 3 × VboostThe time states, which together form a power frequency ac cycle.
CN201810343131.8A 2018-04-17 2018-04-17 Seven-level inverter topological structure based on voltage doubling circuit and seven-level inverter Expired - Fee Related CN108683347B (en)

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