CN103051231A - Three-phase five-level inverter - Google Patents

Three-phase five-level inverter Download PDF

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Publication number
CN103051231A
CN103051231A CN2012105276894A CN201210527689A CN103051231A CN 103051231 A CN103051231 A CN 103051231A CN 2012105276894 A CN2012105276894 A CN 2012105276894A CN 201210527689 A CN201210527689 A CN 201210527689A CN 103051231 A CN103051231 A CN 103051231A
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switch transistor
level
jointly
output
described switch
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汪洪亮
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Sungrow Power Supply Co Ltd
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Sungrow Power Supply Co Ltd
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Abstract

The embodiment of the invention discloses a three-phase five-level inverter, which comprises a direct-current unit and a three-phase inversion unit, wherein the first input end of the direct-current unit is connected to the anode of a direct-current power supply; the second input end of the direct-current unit is connected to the cathode of the direct-current power supply; the direct-current unit comprises three output ends, i.e., a two-level output end, a one-level output end and a zero-level output end; the three-phase inversion unit comprises three single-phase five-level full-bridge inversion units; each single-phase five-level full-bridge inversion unit comprises a two-level input end, a one-level input end, a zero-level input end, a first output end and a second output end, wherein the two-level input end is connected with the two-level output end; the one-level input end is connected with the one-level output end; the zero-level input end is connected with the zero-level output end; and the first output end and the second output end are used for outputting the alternating current voltage. According to the three-phase five-level inverter disclosed by the invention, the output voltage is correspondingly improved by one time, the boosting efficiency is improved, the line transmission loss in a medium-voltage transformer boosting process is reduced, and the problem of low boosting efficiency in the prior art is solved.

Description

A kind of three-phase five-electrical level inverter
Technical field
The present invention relates to electric and electronic technical field, relate in particular to a kind of three-phase five-electrical level inverter.
Background technology
In the high-power photovoltaic power station, generally adopt three-phase inverter of semibridge type output 270V or 315V voltage, again by the external middle pressure transformer access medium voltage network that boosts.Inverter output voltage is higher, and the circuit loss of boosting in the process by middle pressure transformer is less.So it is one of main flow trend of high-power photovoltaic power station type inverter development that output voltage raises.Prior art generally adopts superimposed type boost booster circuit to improve the voltage of inverter direct-flow side, thereby reaches the purpose that improves ac output voltage.But because the wider range that boosts of boost booster circuit causes the boosting efficiency of above-mentioned step-up method low.
Summary of the invention
In view of this, the object of the invention is to provide a kind of three-phase five-electrical level inverter, the inverter problem low to the boosting efficiency of output voltage that generally adopts to solve existing high-power photovoltaic power station.
For achieving the above object, the invention provides following technical scheme:
A kind of three-phase five-electrical level inverter comprises direct current unit and three-phase inversion unit; Wherein,
Described direct current unit is used to described three-phase inversion unit that five level DC voltages are provided; The first input end of described direct current unit is connected to the positive pole of DC power supply, and the second input of described direct current unit is connected to the negative pole of described DC power supply; Described direct current unit comprises 3 outputs, is respectively 2 level output ends, 1 level output end and 0 level output end;
Described three-phase inversion unit comprises 3 single-phase five Level Full Bridge inversion units; Each single-phase five Level Full Bridge inversion unit comprises the 2 level inputs that are connected with described 2 level output ends, the 1 level input that is connected with described 1 level output end, the 0 level input that is connected with described 0 level output end, and the first output of output AC voltage and the second output.
Preferably, described direct current unit comprises the first electric capacity and the second electric capacity;
The second end of described the first electric capacity be connected the first end of electric capacity and connect, and jointly be connected to described 1 level output end;
The first end of described the first electric capacity respectively with described first input end with are connected level output end and are connected;
The second end of described the second electric capacity respectively with described the second input with is connected level output end and is connected.
Preferably, described single-phase five Level Full Bridge inversion units are the first full-bridge inverting unit, or the second full-bridge inverting unit, or the 3rd full-bridge inverting unit, or the 4th full-bridge inverting unit, or the 5th full-bridge inverting unit, or the 6th full-bridge inverting unit, or the 7th full-bridge inverting unit, or eight convergent points bridge inversion unit;
Described the first full-bridge inverting unit comprises switch transistor T 11, switch transistor T 12, switch transistor T 13, switch transistor T 14, switch transistor T 15 and switch transistor T 16, diode of each switching tube reverse parallel connection; Wherein,
The second end of described switch transistor T 11 is connected with the first end of described switch transistor T 12, and jointly is connected to described the first output; The second end of described switch transistor T 13 is connected with the first end of described switch transistor T 14, and jointly is connected to described the second output; The second end of described switch transistor T 12 is connected with the second end of described switch transistor T 14, and jointly is connected to described 0 level input; The first end of described switch transistor T 11 is connected with the first end of described switch transistor T 13, and jointly is connected to the first end of described switch transistor T 15 and the second end of described switch transistor T 16; Second of described switch transistor T 15 is terminated at described 1 level input; The first end of described switch transistor T 16 is connected to described 2 level inputs;
Described the second full-bridge inverting unit comprises switch transistor T 21, switch transistor T 22, switch transistor T 23, switch transistor T 24, switch transistor T 25 and switch transistor T 26, diode of each switching tube reverse parallel connection; Wherein,
The second end of described switch transistor T 21 is connected with the first end of described switch transistor T 22, and jointly is connected to described the first output; The second end of described switch transistor T 23 is connected with the first end of described switch transistor T 24, and jointly is connected to described the second output; The first end of described switch transistor T 21 is connected with the first end of described switch transistor T 23, and jointly is connected to described 2 level inputs; The second end of described switch transistor T 22 is connected with the second end of described switch transistor T 24, and jointly is connected to the second end of described switch transistor T 25 and the first end of described switch transistor T 26; The first end of described switch transistor T 25 is connected to described 1 level input; Second of described switch transistor T 26 is terminated at described 0 level input;
Described the 3rd full-bridge inverting unit comprises switch transistor T 31, switch transistor T 32, switch transistor T 33, switch transistor T 34, switch transistor T 35 and switch transistor T 36, diode of each switching tube reverse parallel connection; Wherein,
The second end of described switch transistor T 31 is connected with the first end of described switch transistor T 32, and jointly is connected to the first end of described the first output and described switch transistor T 35; The second end of described switch transistor T 33 is connected with the first end of described switch transistor T 34, and jointly is connected to described the second output; The first end of described switch transistor T 31 is connected with the first end of described switch transistor T 33, and jointly is connected to described 2 level inputs; The second end of described switch transistor T 32 is connected with the second end of described switch transistor T 34, and jointly is connected to described 0 level input; The second end of described switch transistor T 35 is connected with the second end of described switch transistor T 36, and the first end of described switch transistor T 36 is connected with described 1 level input;
Described the 4th full-bridge inverting unit comprises switch transistor T 41, switch transistor T 42, switch transistor T 43, switch transistor T 44, switch transistor T 45 and switch transistor T 46, diode of each switching tube reverse parallel connection; Wherein,
The second end of described switch transistor T 41 is connected with the first end of described switch transistor T 42, and jointly is connected to described the first output; The second end of described switch transistor T 43 is connected with the first end of described switch transistor T 44, and jointly is connected to described the second output; The first end of described switch transistor T 41 is connected with the first end of described switch transistor T 46 with the second end of described switch transistor T 45 respectively; The first end of described switch transistor T 45 is connected with the first end of described switch transistor T 43, and jointly is connected to described 2 level inputs; The second end of described switch transistor T 46 is connected with described 1 level input; The second end of described switch transistor T 42 is connected with the second end of described switch transistor T 44, and jointly is connected to described 0 level input;
Described the 5th full-bridge inverting unit comprises switch transistor T 51, switch transistor T 52, switch transistor T 53, switch transistor T 54, switch transistor T 55 and switch transistor T 56, diode of each switching tube reverse parallel connection; Wherein,
The second end of described switch transistor T 51 is connected with the first end of described switch transistor T 52, and jointly is connected to described the first output; The second end of described switch transistor T 53 is connected with the first end of described switch transistor T 54, and jointly is connected to described the second output; The second end of described switch transistor T 52 respectively with the first end of described switch transistor T 55 be connected the second end of switch transistor T 56 and be connected; The second end of described switch transistor T 55 is connected with the second end of described switch transistor T 54, and jointly is connected to described 0 level input; The first end of described switch transistor T 56 is connected with described 1 level input; The first end of described switch transistor T 51 is connected with the first end of described switch transistor T 53, and jointly is connected to described 2 level inputs;
Described the 6th full-bridge inverting unit comprises diode D61, diode D62, switch transistor T 61, switch transistor T 62, switch transistor T 63, switch transistor T 64, switch transistor T 65 and switch transistor T 66, diode of each switching tube reverse parallel connection; Wherein,
The second end of described switch transistor T 61 is connected with the first end of described switch transistor T 62, and jointly is connected to described the first output; The second end of described switch transistor T 63 is connected with the first end of described switch transistor T 64, and jointly is connected to described the second output; The first end of described switch transistor T 61 respectively with the second end of described switch transistor T 65 be connected the negative electrode of diode D61 and be connected; The first end of described switch transistor T 65 is connected with the first end of described switch transistor T 63, and jointly is connected to described 2 level inputs; The second end of described switch transistor T 62 respectively with the first end of described switch transistor T 66 and the anodic bonding of described diode D62; The second end of described switch transistor T 66 is connected with the second end of described switch transistor T 64, and jointly is connected to described 0 level input; The anode of described diode D61 is connected with the negative electrode of described diode D62, and jointly is connected to described 1 level input;
Described the 7th full-bridge inverting unit comprises diode D71, diode D72, diode D73, diode D74, switch transistor T 71, switch transistor T 72, switch transistor T 73, switch transistor T 74 and switch transistor T 75, diode of each switching tube reverse parallel connection; Wherein,
The second end of described switch transistor T 71 is connected with the first end of described switch transistor T 72, and jointly is connected to described the first output; The second end of described switch transistor T 73 is connected with the first end of described switch transistor T 74, and jointly is connected to described the second output; The first end of described switch transistor T 71 is connected with the first end of described switch transistor T 73, and jointly is connected to described 2 level inputs; The second end of described switch transistor T 72 is connected with the second end of described switch transistor T 74, and jointly is connected to described 0 level input; The negative electrode of described diode D71 is connected with the negative electrode of described diode D73, and jointly is connected to the first end of described switch transistor T 75; The anodic bonding of the anode of described diode D72 and described diode D74, and jointly be connected to the second end of described switch transistor T 75; The anode of described diode D73 is connected with the negative electrode of described diode D74, and jointly is connected to the first end of described switch transistor T 72; The anode of described diode D71 is connected with the negative electrode of described diode D72, and jointly is connected to described 1 level input;
Described eight convergent points bridge inversion unit comprises diode D81, diode D82, the first inductance, the second inductance, switch transistor T 81, switch transistor T 82, switch transistor T 83, switch transistor T 84, switch transistor T 85 and switch transistor T 86, diode of each switching tube reverse parallel connection; Wherein,
The second end of described the first inductance is connected by electric capacity with the second end of described the second inductance; The second end of described switch transistor T 81 is connected with the first end of described switch transistor T 82, and jointly is connected to described the first output; The second end of described switch transistor T 83 is connected with the first end of described switch transistor T 84, and jointly is connected to described the second output; The first end of described switch transistor T 81 is connected with the first end of described switch transistor T 83, and jointly is connected to the second end of described the first inductance; The first end of described the first inductance respectively with the second end of described switch transistor T 85 be connected the negative electrode of diode D81 and be connected; The first end of described switch transistor T 85 is connected with described 2 level inputs; The anode of described diode D81 is connected with the negative electrode of described diode D82, and jointly is connected to described 1 level input; The second end of described switch transistor T 82 is connected with the second end of described switch transistor T 84, and jointly is connected to the second end of described the second inductance; The first end of described the second inductance respectively with the anode of described diode D82 be connected the first end of switch transistor T 86 and be connected; The second end of described switch transistor T 86 is connected with described 0 level input.
Preferably, described direct current unit comprises boosting unit and the second electric capacity, described boosting unit comprise the first electric capacity and with the boost booster circuit of described the first Capacitance parallel connection;
The second end of described the first electric capacity be connected the first end of electric capacity and connect, and jointly be connected to described 1 level output end and first input end; The first end of described the first electric capacity is connected to described 2 level output ends; The second end of described the second electric capacity respectively with described the second input with is connected level output end and is connected.
Preferably, described single-phase five Level Full Bridge inversion units comprise switch transistor T 11, switch transistor T 12, switch transistor T 13, switch transistor T 14, switch transistor T 15 and switch transistor T 16, diode of each switching tube reverse parallel connection; Wherein,
The second end of described switch transistor T 11 is connected with the first end of described switch transistor T 12, and jointly is connected to described the first output; The second end of described switch transistor T 13 is connected with the first end of described switch transistor T 14, and jointly is connected to described the second output; The second end of described switch transistor T 12 is connected with the second end of described switch transistor T 14, and jointly is connected to described 0 level input; The first end of described switch transistor T 11 is connected with the first end of the 3rd switch transistor T 13, and jointly is connected to the first end of described switch transistor T 15 and the second end of described switch transistor T 16; Second of described switch transistor T 15 is terminated at described 1 level input; The first end of described switch transistor T 16 is connected to described 2 level inputs.
Preferably, described direct current unit comprises the first electric capacity and boosting unit, described boosting unit comprise the second electric capacity and with the boost booster circuit of described the second Capacitance parallel connection;
The second end of described the first electric capacity be connected the first end of electric capacity and connect, and jointly be connected to described 1 level output end and the second input; The first end of described the first electric capacity respectively with described first input end be connected 2 level output ends and be connected; The second end of described the second electric capacity is connected with described 0 level output end.
Preferably, described single-phase five Level Full Bridge inversion units comprise switch transistor T 21, switch transistor T 22, switch transistor T 23, switch transistor T 24, switch transistor T 25 and switch transistor T 26, diode of each switching tube reverse parallel connection; Wherein,
The second end of described switch transistor T 21 is connected with the first end of described switch transistor T 22, and jointly is connected to described the first output; The second end of described switch transistor T 23 is connected with the first end of described switch transistor T 24, and jointly is connected to described the second output; The first end of described switch transistor T 21 is connected with the first end of described switch transistor T 23, and jointly is connected to described 2 level inputs; The second end of described switch transistor T 22 is connected with the second end of described switch transistor T 24, and jointly is connected to the second end of described switch transistor T 25 and the first end of described switch transistor T 26; The first end of described switch transistor T 25 is connected to described 1 level input; Second of described switch transistor T 26 is terminated at described 0 level input.
Preferably, described boosting unit has 3.
Preferably, described inverter also comprises filter unit; The first output of described filter unit and described single-phase five Level Full Bridge inversion units be connected output and be connected.
Can find out from above-mentioned technical scheme, the present invention is with single-phase five Level Full Bridge inversion units, when being applied in the three-phase five-electrical level inverter, necessarily, do not use at DC power supply voltage in the situation of any booster circuit, the semi-bridge inversion unit that generally adopts with respect to prior art, make not only that output voltage is corresponding to be doubled, and the problem that does not have the wide ranges of boosting, improved boosting efficiency, reduce boost circuit loss in the process of middle pressure transformer, be applicable to the higher high-power photovoltaic power station type of the output voltage application scenario of being incorporated into the power networks.Therefore, the embodiment of the invention has solved the low problem of prior art boosting efficiency.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The structural representation of the three-phase five-electrical level inverter that Fig. 1 provides for the embodiment of the invention one;
The structural representation of the three-phase five-electrical level inverter that Fig. 2 provides for the embodiment of the invention two;
The structural representation of the first inversion unit that Fig. 3 provides for the embodiment of the invention;
The structural representation of the second inversion unit that Fig. 4 provides for the embodiment of the invention;
The structural representation of the 3rd inversion unit that Fig. 5 provides for the embodiment of the invention;
The structural representation of the 4th inversion unit that Fig. 6 provides for the embodiment of the invention;
The structural representation of the 5th inversion unit that Fig. 7 provides for the embodiment of the invention;
The structural representation of the 6th inversion unit that Fig. 8 provides for the embodiment of the invention;
The structural representation of the 7th inversion unit that Fig. 9 provides for the embodiment of the invention;
The structural representation of the 8th inversion unit that Figure 10 provides for the embodiment of the invention;
Conducting schematic diagram when the inversion unit that Figure 11 a provides for the embodiment of the invention is in first mode;
Conducting schematic diagram when the inversion unit that Figure 11 b provides for the embodiment of the invention is in second mode;
Conducting schematic diagram when the inversion unit that Figure 11 c provides for the embodiment of the invention is in the 3rd mode;
Conducting schematic diagram when the inversion unit that Figure 11 d provides for the embodiment of the invention is in the 4th mode;
Conducting schematic diagram when the inversion unit that Figure 11 e provides for the embodiment of the invention is in the 5th mode;
Conducting schematic diagram when the inversion unit that Figure 11 f provides for the embodiment of the invention is in the 6th mode;
The control sequential chart of the three-phase five-electrical level inverter that Figure 12 provides for the embodiment of the invention;
The structural representation of the three-phase five-electrical level inverter that Figure 13 provides for the embodiment of the invention three;
Another structural representation of the three-phase five-electrical level inverter that Figure 14 provides for the embodiment of the invention three;
The structural representation of the three-phase five-electrical level inverter that Figure 15 provides for the embodiment of the invention four;
Another structural representation of the three-phase five-electrical level inverter that Figure 16 provides for the embodiment of the invention four;
The inverter that Figure 17 provides for the embodiment of the invention does not reach control sequential chart in the minimum inverter voltage situation at direct voltage;
Figure 18 reaches the lower control sequential chart of minimum inverter voltage situation for the inverter that the embodiment of the invention provides at direct voltage;
Figure 19 a for the inversion unit output voltage that the embodiment of the invention three provides is+V 2The time the conducting schematic diagram;
Figure 19 b for the inversion unit output voltage that the embodiment of the invention three provides is+V 1The time the conducting schematic diagram;
The inversion unit output voltage that Figure 19 c provides for the embodiment of the invention three is 0 o'clock conducting schematic diagram;
Figure 19 d for the inversion unit output voltage that the embodiment of the invention three provides is-V 1The time the conducting schematic diagram;
Figure 19 e for the inversion unit output voltage that the embodiment of the invention three provides is-V 2The time the conducting schematic diagram;
Figure 20 a for the inversion unit output voltage that the embodiment of the invention four provides is+V 2The time the conducting schematic diagram;
Figure 20 b for the inversion unit output voltage that the embodiment of the invention four provides is+V 1The time the conducting schematic diagram;
The inversion unit output voltage that Figure 20 c provides for the embodiment of the invention four is 0 o'clock conducting schematic diagram;
Figure 20 d for the inversion unit output voltage that the embodiment of the invention four provides is-V 1The time the conducting schematic diagram;
Figure 20 e for the inversion unit output voltage that the embodiment of the invention four provides is-V 2The time the conducting schematic diagram;
The another structural representation of the three-phase five-electrical level inverter that Figure 21 provides for the embodiment of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
The embodiment of the invention discloses a kind of three-phase five-electrical level inverter, to solve the existing low problem of inverter output voltage boosting mode boosting efficiency.
With reference to Fig. 1, the three-phase five-electrical level inverter that the embodiment of the invention one provides comprises direct current unit 100 and three-phase inversion unit 200.
Direct current unit 100 is used to three-phase inversion unit 200 that five level (± 2, ± 1 and 0) direct voltage is provided, and comprises 2 inputs and 3 outputs.Wherein, first input end S1 is connected to the anodal PV+ of DC power supply, and the second input S2 is connected to the negative pole PV-of DC power supply; 3 outputs are respectively 2 level output end Q2,1 level output end Q1 and 0 level output end Q0.
The direct current that three-phase inversion unit 200 is used for direct current unit 100 is provided is converted to alternating current, and it is comprised of 3 identical single-phase five Level Full Bridge inversion units of structure: A phase full-bridge inverting unit 201, B phase full-bridge inverting unit 202 and C be full-bridge inverting unit 203 mutually.The 0 level input R0 that each single-phase five Level Full Bridge inversion unit includes the 2 level input R2 that are connected with 2 level output end Q2, the 1 level input R1 that is connected with 1 level output end Q1, is connected with 0 level output end Q0, and the first output X1 of output AC voltage and the second output X2.In the inverter course of work, electric current has the path of two-way circulating between the input of single-phase five Level Full Bridge inversion units and output.
Form and to find out from said structure, the embodiment of the invention is with single-phase five Level Full Bridge inversion units, be applied in the three-phase five-electrical level inverter,, direct current unit certain at DC power supply voltage do not use in the situation of any booster circuit, the semi-bridge inversion unit that generally adopts with respect to prior art, make not only that output voltage is corresponding to be doubled, and the problem that does not have the wide ranges of boosting, improved boosting efficiency, reduce boost circuit loss in the process of middle pressure transformer, be applicable to the higher high-power photovoltaic power station type of the output voltage application scenario of being incorporated into the power networks.Therefore, the embodiment of the invention has solved the low problem of prior art boosting efficiency.
With reference to Fig. 2, the three-phase five-electrical level inverter that the embodiment of the invention two provides comprises direct current unit 100 and three-phase inversion unit 200.
There are 2 inputs and 3 outputs in direct current unit 100: first input end S1 is connected to the anodal PV+ of DC power supply, and the second input S2 is connected to the negative pole PV-of DC power supply; 3 outputs are respectively 2 level output end Q2,1 level output end Q1 and 0 level output end Q0.Concrete, direct current unit 100 is comprised of the first capacitor C 1 that is connected in series and the second capacitor C 2.Wherein, the second end of the first capacitor C 1 be connected the first end of capacitor C 2 and connect, and jointly be connected to 1 above-mentioned level output end Q1; The first end of the first capacitor C 1 respectively with above-mentioned first input end S1 with are connected level output end Q2 and are connected; The second end of the second capacitor C 2 respectively with above-mentioned the second input S2 with is connected level output end Q0 and is connected.
Three-phase inversion unit 200 is comprised of 3 identical single-phase five Level Full Bridge inversion units of structure: A phase full-bridge inverting unit 201, B phase full-bridge inverting unit 202 and C be full-bridge inverting unit 203 mutually.The 0 level input R0 that each single-phase five Level Full Bridge inversion unit includes the 2 level input R2 that are connected with 2 level output end Q2, the 1 level input R1 that is connected with 1 level output end Q1, is connected with 0 level output end Q0, and the first output X1 of output AC voltage and the second output X2.
A phase full-bridge inverting unit 201, B phase full-bridge inverting unit 202 and the C mutually concrete structure of full-bridge inverting unit 203 can have multiple, Fig. 3 ~ 10 show respectively wherein 8 kinds, for ease of narration, successively called after the first full-bridge inverting unit, the second full-bridge inverting unit, the 3rd full-bridge inverting unit, the 4th full-bridge inverting unit, the 5th full-bridge inverting unit, the 6th full-bridge inverting unit, the 7th full-bridge inverting unit and eight convergent points bridge inversion unit.
As shown in Figure 3, the first full-bridge inverting unit comprises switch transistor T 11, switch transistor T 12, switch transistor T 13, switch transistor T 14, switch transistor T 15 and switch transistor T 16, diode of each switching tube reverse parallel connection.
Wherein, the second end of switch transistor T 11 is connected with the first end of switch transistor T 12, and jointly is connected to the first output X1; The second end of switch transistor T 13 is connected with the first end of switch transistor T 14, and jointly is connected to the second output X2; The second end of switch transistor T 12 is connected with the second end of switch transistor T 14, and jointly is connected to 0 level input R0; The first end of switch transistor T 11 is connected with the first end of switch transistor T 13, and jointly is connected to the first end of switch transistor T 15 and the second end of switch transistor T 16; Second of switch transistor T 15 is terminated at 1 level input R1; The first end of switch transistor T 16 is connected to 2 level input R2.
As shown in Figure 4, the second full-bridge inverting unit comprises switch transistor T 21, switch transistor T 22, switch transistor T 23, switch transistor T 24, switch transistor T 25 and switch transistor T 26, diode of each switching tube reverse parallel connection.
Wherein, the second end of switch transistor T 21 is connected with the first end of switch transistor T 22, and jointly is connected to the first output X1; The second end of switch transistor T 23 is connected with the first end of switch transistor T 24, and jointly is connected to the second output X2; The first end of switch transistor T 21 is connected with the first end of switch transistor T 23, and jointly is connected to 2 level input R2; The second end of switch transistor T 22 is connected with the second end of switch transistor T 24, and jointly is connected to the second end of switch transistor T 25 and the first end of switch transistor T 26; The first end of switch transistor T 25 is connected to 1 level input R1; Second of switch transistor T 26 is terminated at 0 level input R0.
As shown in Figure 5, the 3rd full-bridge inverting unit comprises switch transistor T 31, switch transistor T 32, switch transistor T 33, switch transistor T 34, switch transistor T 35 and switch transistor T 36, diode of each switching tube reverse parallel connection.
Wherein, the second end of switch transistor T 31 is connected with the first end of switch transistor T 32, and jointly is connected to the first end of the first output X1 and switch transistor T 35; The second end of switch transistor T 33 is connected with the first end of switch transistor T 34, and jointly is connected to the second output X2; The first end of switch transistor T 31 is connected with the first end of switch transistor T 33, and jointly is connected to 2 level input R2; The second end of switch transistor T 32 is connected with the second end of switch transistor T 34, and jointly is connected to 0 level input R0; The second end of switch transistor T 35 is connected with the second end of switch transistor T 36, and the first end of switch transistor T 36 is connected with 1 level input R0.
As shown in Figure 6, the 4th full-bridge inverting unit comprises switch transistor T 41, switch transistor T 42, switch transistor T 43, switch transistor T 44, switch transistor T 45 and switch transistor T 46, diode of each switching tube reverse parallel connection.
Wherein, the second end of switch transistor T 41 is connected with the first end of switch transistor T 42, and jointly is connected to the first output X1; The second end of switch transistor T 43 is connected with the first end of switch transistor T 44, and jointly is connected to the second output X2; The first end of switch transistor T 1 is connected with the first end of switch transistor T 46 with the second end of switch transistor T 45 respectively; The first end of switch transistor T 45 is connected with the first end of switch transistor T 43, and jointly is connected to 2 level input R2; The second end of switch transistor T 46 is connected R1 with 1 level input; The second end of switch transistor T 42 is connected with the second end of switch transistor T 44, and jointly is connected to 0 level input R0.
As shown in Figure 7, the 5th full-bridge inverting unit comprises switch transistor T 51, switch transistor T 52, switch transistor T 53, switch transistor T 54, switch transistor T 55 and switch transistor T 56, diode of each switching tube reverse parallel connection.
Wherein, the second end of switch transistor T 51 is connected with the first end of switch transistor T 52, and jointly is connected to the first output X1; The second end of switch transistor T 53 is connected with the first end of switch transistor T 54, and jointly is connected to the second output X2; The second end of switch transistor T 52 is connected with the second end that the first end of switch transistor T 55 is connected with switch transistor T respectively; The second end of switch transistor T 55 is connected with the second end of switch transistor T 54, and jointly is connected to 0 level input R0; The first end of switch transistor T 56 is connected with 1 level input R1; The first end of switch transistor T 51 is connected with the first end of switch transistor T 53, and jointly is connected to 2 level input R2.
As shown in Figure 8, the 6th full-bridge inverting unit comprises diode D61, diode D62, switch transistor T 61, switch transistor T 62, switch transistor T 63, switch transistor T 64, switch transistor T 65 and switch transistor T 66, diode of each switching tube reverse parallel connection.
Wherein, the second end of switch transistor T 61 is connected with the first end of switch transistor T 62, and jointly is connected to the first output X1; The second end of switch transistor T 63 is connected with the first end of switch transistor T 64, and jointly is connected to the second output X2; The first end of switch transistor T 61 is connected negative electrode with the second end of switch transistor T 65 respectively and is connected with diode D61; The first end of switch transistor T 65 is connected with the first end of switch transistor T 63, and jointly is connected to 2 level input R2; The second end of switch transistor T 62 respectively with the first end of switch transistor T 66 and the anodic bonding of diode D62; The second end of switch transistor T 66 is connected with the second end of switch transistor T 64, and jointly is connected to 0 level input R0; The anode of diode D61 is connected with the negative electrode of diode D62, and jointly is connected to 1 level input R1.
As shown in Figure 9, the 7th full-bridge inverting unit comprises diode D71, diode D72, diode D73, diode D74, switch transistor T 71, switch transistor T 72, switch transistor T 73, switch transistor T 74 and switch transistor T 75, diode of each switching tube reverse parallel connection.
Wherein, the second end of switch transistor T 71 is connected with the first end of switch transistor T 72, and jointly is connected to the first output X1; The second end of switch transistor T 73 is connected with the first end of switch transistor T 74, and jointly is connected to the second output X2; The first end of switch transistor T 71 is connected with the first end of switch transistor T 73, and jointly is connected to 2 level input R2; The second end of switch transistor T 72 is connected with the second end of switch transistor T 74, and jointly is connected to 0 level input R0; The negative electrode of diode D71 is connected with the negative electrode of diode D73, and jointly is connected to the first end of switch transistor T 75; The anodic bonding of the anode of diode D72 and diode D74, and jointly be connected to the second end of switch transistor T 75; The anode of diode D73 is connected with the negative electrode of diode D74, and jointly is connected to the first end of switch transistor T 72; The anode of diode D71 is connected with the negative electrode of diode D72, and jointly is connected to 1 level input R1.
As shown in figure 10, eight convergent points bridge inversion unit comprises diode D81, diode D82, the first inductance, the second inductance, switch transistor T 81, switch transistor T 82, switch transistor T 83, switch transistor T 84, switch transistor T 85 and switch transistor T 86, diode of each switching tube reverse parallel connection.
Wherein, the second end of the first inductance L 1 is connected by electric capacity with the second end of the second inductance L 2; The second end of switch transistor T 81 is connected with the first end of switch transistor T 82, and jointly is connected to the first output X1; The second end of switch transistor T 83 is connected with the first end of switch transistor T 84, and jointly is connected to the second output X2; The first end of switch transistor T 81 is connected with the first end of switch transistor T 83, and jointly is connected to the second end of the first inductance L 1; The first end of the first inductance L 1 is connected negative electrode with the second end of switch transistor T 85 respectively and is connected with diode D81; The first end of switch transistor T 85 is connected with 2 level input R2; The anode of diode D81 is connected with the negative electrode of diode D82, and jointly is connected to 1 level input R1; The second end of switch transistor T 82 is connected with the second end of switch transistor T 84, and jointly is connected to the second end of the second inductance L 2; The first end of the second inductance L 2 is connected with the first end that the anode of diode D82 is connected with switch transistor T respectively; The second end of switch transistor T 86 is connected with 0 level input R0.
By above-mentioned inverter structure as can be known, the three-phase full-bridge inverter that the embodiment of the invention provides, the direct current unit is formed by two capacitances in series, namely adopts the mode of capacitance partial pressure to provide DC power supply for the three-phase inversion unit; The three-phase inversion unit is made of 3 single-phase five Level Full Bridge inversion units.Compare with the existing three-phase inverter of semibridge type of superimposed type boost boosting unit that adopts, the beneficial effect of the embodiment of the invention is:
(1) necessarily, do not use in the situation of any boosting unit at DC power supply voltage, the embodiment of the invention also can make output voltage and double than the output voltage of the three-phase inverter of semibridge type that does not have the boost boosting unit, reduce boost circuit loss in the process of middle pressure transformer, be applicable to the higher high-power photovoltaic power station type of the output voltage application scenario of being incorporated into the power networks;
(2) in the identical situation of output voltage, the required DC power supply voltage of the embodiment of the invention is lower, and the stress of switching tube is little, is convenient to choosing of switching tube, has reduced the cost of device;
(3) avoided current zero to pass through the distortion phenomenon in zone.Existing inverter of semibridge type is for reducing switching device, removed the idle path of part (inversion unit can only one-way conduction), causes current zero to pass through regional generation current distortion.And electric current corresponding to each mode of full-bridge inverting subelement that the embodiment of the invention adopts has the path of two-way circulating, namely guaranteeing to provide all idle paths in the less situation of device count, so the distortion phenomenon that current zero passes through the zone can not occur.Concrete, the single-phase five Level Full Bridge inversion units that the inverter that above-described embodiment provides adopts include six operation modes, to realize the output of five level.The total voltage of supposing DC power supply PV is 2V 0, then under six mode, the voltage U between the input of inversion unit and the conducting situation between the output and the first output X1 and the second output X2 is as follows:
First mode: two-way admittance between 2 level input R2 and the first output X1, two-way admittance between 0 level input R0 and the second output X2, output voltage U is 2V 0, shown in Figure 11 a;
Second mode: two-way admittance between 1 level input R1 and the first output X1, two-way admittance between 0 level input R0 and the second output X2, output voltage U is V 0, shown in Figure 11 b;
The 3rd mode: two-way admittance between 0 level input R0 and the first output X1, two-way admittance between 0 level input R0 and the second output X2, output voltage U is 0, shown in Figure 11 c;
The 4th mode: two-way admittance between 2 level input R2 and the first output X1, two-way admittance between 2 level input R2 and the second output X2, output voltage U is 0, shown in Figure 11 d;
The 5th mode: two-way admittance between 2 level input R2 and the second output X2, two-way admittance between 1 level input R1 and the first output X1, output voltage U is-V 0, shown in Figure 11 e;
The 6th mode: two-way admittance between 2 level input R2 and the second output X2, two-way admittance between 0 level input R0 and the first output X1, output voltage U is-2V 0, shown in Figure 11 f.
The below is described in detail above-mentioned six operation modes take the first full-bridge inverting unit as example, and those skilled in the art can correspondingly derive the conduction mode of full-bridge inverting unit under above-mentioned six operation modes of other structures.
First mode: electric current flows to the first output X1 by 2 level input R2 through switch transistor T 16 and switch transistor T 11, by the second output X2, flows to 0 level input R0 through switch transistor T 14, realizes forward conduction; Electric current is by 0 level input R0, flow to the second output X2 through the diode with switch transistor T 14 reverse parallel connections, by the first output X1, through flowing to 2 level input R2 with the diode of switch transistor T 11 reverse parallel connections with the diode of switch transistor T 16 reverse parallel connections, realize reverse-conducting;
Second mode: electric current flows to the first output X1 by 1 level input R1 through diode and switch transistor T 11 with switch transistor T 15 reverse parallel connections, by the second output X2, flows to 0 level input R0 through switch transistor T 14, realizes forward conduction; Electric current flows to the second output X2 by 0 level input R0 through the diode with switch transistor T 14 reverse parallel connections, by the first output X1, flows to 1 level input R1 through diode and switch transistor T 15 with switch transistor T 11 reverse parallel connections, realizes reverse-conducting;
The 3rd mode: electric current flows to the first output X1 by 0 level input R0 through the diode with switch transistor T 12 reverse parallel connections, by the second output X2, flows to 0 level input R0 through switch transistor T 14, realizes forward conduction; Electric current flows to the second output X2 by 0 level input R0 through the diode with switch transistor T 14 reverse parallel connections, by the first output X1, flows to 0 level input R0 through switch transistor T 12, realizes reverse-conducting;
The 4th mode: electric current is by 2 level input R2, flow to the first output X1 through switch transistor T 16 and switch transistor T 11, by the second output X2, through flowing to 2 level input R2 with the diode of switch transistor T 13 reverse parallel connections with the diode of switch transistor T 16 reverse parallel connections, realize forward conduction; Electric current is by 2 level input R2, flow to the second output X2 through switch transistor T 16 and switch transistor T 13, by the first output X1, through flowing to 2 level input R2 with the diode of switch transistor T 11 reverse parallel connections with the diode of switch transistor T 16 reverse parallel connections, realize reverse-conducting;
The 5th mode: electric current is by 2 level input R2, flow to the second output X2 through switch transistor T 16 and switch transistor T 13, by the first output X1, flow to 1 level input R1 through diode and switch transistor T 15 with switch transistor T 11 reverse parallel connections, realize forward conduction; Electric current is by 1 level input R1, flow to the first output X1 through diode and switch transistor T 11 with switch transistor T 15 reverse parallel connections, by the second output X2, through flowing to 2 level input R2 with the diode of switch transistor T 13 reverse parallel connections with the diode of switch transistor T 16 reverse parallel connections, realize reverse-conducting;
The 6th mode: electric current flows to the second output X2 by 2 level input R2 through switch transistor T 16 and switch transistor T 13, by the first output X1, flows to 0 level input R0 through switch transistor T 12, realizes forward conduction; Electric current is by 0 level input R0, flow to the first output X1 through the diode with switch transistor T 12 reverse parallel connections, by the second output X2, through flowing to 2 level input R2 with the diode of switch transistor T 13 reverse parallel connections with the diode of switch transistor T 16 reverse parallel connections, realize reverse-conducting.
Electric current corresponding to each mode has the path of two-way circulating, and can avoid current zero to pass through the distortion phenomenon in zone.
Figure 12 shows the sequential chart that the single-phase five Level Full Bridge inversion units in the embodiment of the invention two adopt six mode combinations to control.Be to guarantee inversion efficiency, when output voltage be in positive half cycle, when the demand output voltage is 0, preferred the 3rd mode; When output voltage be in negative half period, when the demand output voltage is 0, preferred the 4th mode.So, as shown in figure 12, t 0~ t 1, t 2~ t 3In period, second mode and the 3rd mode alternate conduction; t 1~ t 2In period, first mode and second mode alternate conduction; t 3~ t 4, t 5~ t 6In period, the 4th mode and the 5th mode alternate conduction; t 4~ t 5In period, the 5th mode and the 6th mode alternate conduction.
Referring to Figure 13, the three-phase five-electrical level inverter that the embodiment of the invention three provides comprises direct current unit 100 and three-phase inversion unit 200.
Wherein, direct current unit 100 comprises boosting unit 101 and the second capacitor C 2.Boosting unit 101 is formed in parallel by the first capacitor C 1 and boost booster circuit, the second end of the first capacitor C 1 be connected the first end of capacitor C 2 and connect, and jointly be connected to 1 level output end Q1 and first input end S1; The first end of the first capacitor C 1 is connected to 2 level output end Q2; The second end of the second capacitor C 2 respectively with the second input S2 with is connected level output end Q0 and is connected.
Three-phase inversion unit 200 is comprised of 3 identical single-phase five Level Full Bridge inversion units of structure: A phase full-bridge inverting unit 201, B phase full-bridge inverting unit 202 and C be full-bridge inverting unit 203 mutually.The 0 level input R0 that each single-phase five Level Full Bridge inversion unit includes the 2 level input R2 that are connected with 2 level output end Q2, the 1 level input R1 that is connected with 1 level output end Q1, is connected with 0 level output end Q0, and the first output X1 of output AC voltage and the second output X2.
A phase full-bridge inverting unit 201 in the present embodiment, B phase full-bridge inverting unit 202 and C mutually full-bridge inverting unit 203 specifically can adopt the first full-bridge inverting unit shown in Figure 3, namely comprise switch transistor T 11, switch transistor T 12, switch transistor T 13, switch transistor T 14, switch transistor T 15 and switch transistor T 16, diode of each switching tube reverse parallel connection.The second end of switch transistor T 11 is connected with the first end of switch transistor T 12, and jointly is connected to the first output X1; The second end of switch transistor T 13 is connected with the first end of switch transistor T 14, and jointly is connected to the second output X2; The second end of switch transistor T 12 is connected with the second end of switch transistor T 14, and jointly is connected to 0 level input R0; The first end of switch transistor T 11 is connected with the first end of switch transistor T 13, and jointly is connected to the first end of switch transistor T 15 and the second end of switch transistor T 16; Second of switch transistor T 15 is terminated at 1 level input R1; The first end of switch transistor T 16 is connected to 2 level input R2.
Concrete, suppose that the voltage of DC power supply PV is V1, the voltage that obtains after boosting unit boosts is V2, then in above-described embodiment three, the conducting situation of 3 single-phase five Level Full Bridge inversion units with the corresponding relation of five kinds of level of output is:
When current flowing two-way circulating during the path between 2 level input R2 and the first output X1 and between 0 level input R0 and the second output X2, output voltage U is+V2, such as Figure 19 a;
When current flowing two-way circulating during the path between 1 level input R1 and the first output X1 and between 0 level input R0 and the second output X2, output voltage U is+V1, such as Figure 19 b;
When current flowing two-way circulating during the path between 0 level input R0 and the first output X1 and between 0 level input R0 and the second output X2, output voltage U is 0, such as Figure 19 c;
When current flowing two-way circulating during the path between 1 level input R1 and the second output X2 and between 0 level input R0 and the first output X1, output voltage U is-V1, such as Figure 19 d;
When current flowing two-way circulating during the path between 2 level input R2 and the second output X2 and between 0 level input R0 and the first output X1, output voltage U is-the path e that two-way circulates of V2.
By said structure as can be known, the embodiment of the invention three is with single-phase five Level Full Bridge inversion units, be applied in the three-phase five-electrical level inverter, in the certain situation of the direct voltage of input three-phase inversion unit, with respect to the semi-bridge inversion unit that prior art generally adopts, output voltage is corresponding to be doubled; And by the first electric capacity and boost booster circuit formation in parallel boosting unit, and then consist of the direct current unit of three-phase five-electrical level inverter with the second capacitances in series, then improved the output voltage (namely inputting the direct voltage of three-phase inversion unit) of direct current unit, be applicable to the not too high occasion of PV voltage, thereby further improved the ac output voltage of inverter, improved boosting efficiency, reduce boost circuit loss in the process of middle pressure transformer, be applicable to the higher high-power photovoltaic power station type of the output voltage application scenario of being incorporated into the power networks.Simultaneously, the single-phase five Level Full Bridge inversion units in the present embodiment have the path of two-way circulating, namely guaranteeing to provide all idle paths in the less situation of device count, so the distortion phenomenon that current zero passes through the zone can not occur.
Further, as shown in figure 14, for corresponding with 3 single-phase five Level Full Bridge inversion units, be convenient to inverter is controlled and modularization, direct current unit in above-described embodiment three described three-phase five-electrical level inverters can increase by two boosting units: boosting unit 102 and boosting unit 103, its structure and connected mode and boosting unit 101 are identical.
With reference to Figure 15, corresponding with above-described embodiment three, the embodiment of the invention four also provides a kind of three-phase five-electrical level inverter, comprises direct current unit 100 and three-phase inversion unit 200.
Wherein, direct current unit 200 comprises the first capacitor C 1 and boosting unit 101, and boosting unit 101 is made of the second capacitor C 2 and the parallel connection of boost booster circuit.The second end of the first capacitor C 1 be connected the first end of capacitor C 2 and connect, and jointly be connected to 1 level output end Q1 and the second input S2; The first end of the first capacitor C 1 respectively with first input end S1 with are connected level output end Q2 and are connected; The second end of the second capacitor C 2 is connected with 0 level output end Q0.
Three-phase inversion unit 200 is comprised of 3 identical single-phase five Level Full Bridge inversion units of structure: A phase full-bridge inverting unit 201, B phase full-bridge inverting unit 202 and C be full-bridge inverting unit 203 mutually.The 0 level input R0 that each single-phase five Level Full Bridge inversion unit includes the 2 level input R2 that are connected with 2 level output end Q2, the 1 level input R1 that is connected with 1 level output end Q1, is connected with 0 level output end Q0, and the first output X1 of output AC voltage and the second output X2.
A phase full-bridge inverting unit 201 in the present embodiment, B phase full-bridge inverting unit 202 and C mutually full-bridge inverting unit 203 specifically can adopt the second full-bridge inverting unit shown in Figure 4, namely comprise switch transistor T 21, switch transistor T 22, switch transistor T 23, switch transistor T 24, switch transistor T 25 and switch transistor T 26, diode of each switching tube reverse parallel connection.
Wherein, the second end of switch transistor T 21 is connected with the first end of switch transistor T 22, and jointly is connected to the first output X1; The second end of switch transistor T 23 is connected with the first end of switch transistor T 24, and jointly is connected to the second output X2; The first end of switch transistor T 21 is connected with the first end of switch transistor T 23, and jointly is connected to 2 level input R2; The second end of switch transistor T 22 is connected with the second end of switch transistor T 24, and jointly is connected to the second end of switch transistor T 25 and the first end of switch transistor T 26; The first end of switch transistor T 25 is connected to 1 level input R1; Second of switch transistor T 26 is terminated at 0 level input R0.
Concrete, the voltage of still supposing DC power supply PV is V 1, the total voltage that obtains after boosting unit boosts is V 2, then in above-described embodiment four, the conducting situation of 3 single-phase five Level Full Bridge inversion units with the corresponding relation of five kinds of level of output is:
When current flowing two-way circulating during the path between 2 level input R2 and the first output X1 and between 0 level input R0 and the second output X2, output voltage U is+V2, such as Figure 20 a;
When current flowing two-way circulating during the path between 2 level input R2 and the first output X1 and between 1 level input R1 and the second output X2, output voltage U is+V1, such as Figure 20 b;
When current flowing two-way circulating during the path between 2 level input R2 and the first output X1 and between 2 level input R2 and the second output X2, output voltage U is 0, such as Figure 20 c;
When current flowing two-way circulating during the path between 2 level input R2 and the second output X2 and between 1 level input R1 and the first output X1, output voltage U is-V1, such as Figure 20 d;
When current flowing two-way circulating during the path between 2 level input R2 and the second output X2 and between 0 level input R0 and the first output X1, output voltage U is-V2, such as Figure 20 e.
By said structure as can be known, the embodiment of the invention three is applied to single-phase five Level Full Bridge inversion units in the three-phase five-electrical level inverter, under direct voltage one stable condition of input three-phase inversion unit, with respect to the semi-bridge inversion unit that prior art generally adopts, output voltage is corresponding to be doubled; And by the first electric capacity and boost booster circuit formation in parallel boosting unit, and then consist of the direct current unit of three-phase five-electrical level inverter with the second capacitances in series, then improved the output voltage (namely inputting the direct voltage of three-phase inversion unit) of direct current unit, be applicable to the not too high occasion of PV voltage, thereby further improved the ac output voltage of inverter, improved boosting efficiency, reduce boost circuit loss in the process of middle pressure transformer, be applicable to the higher high-power photovoltaic power station type of the output voltage application scenario of being incorporated into the power networks.Simultaneously, the single-phase five Level Full Bridge inversion units in the present embodiment have the path of two-way circulating, namely guaranteeing to provide all idle paths in the less situation of device count, so the distortion phenomenon that current zero passes through the zone can not occur.Further, as shown in figure 16, for corresponding with 3 single-phase five Level Full Bridge inversion units, be convenient to inverter is controlled and modularization, direct current unit in above-described embodiment four described three-phase five-electrical level inverters can increase by two boosting units: boosting unit 102 and boosting unit 103, its structure and connected mode and boosting unit 101 are identical.
Figure 17 shows the control sequential chart of inverter under different direct voltages that the embodiment of the invention three, four provides with Figure 18.The voltage V of DC power supply PV shown in Figure 17 1Do not reach in the minimum inverter voltage situation, the work of boost boosting unit makes total direct voltage rise to V 2, reach minimum inverter voltage; The voltage V of DC power supply PV shown in Figure 180 1Reach in the minimum inverter voltage situation, the boost boosting unit is still worked, and makes total direct voltage rise to V 2, with the output of match five level, reach the purpose that reduces the ripple loss, reduces the filter volume.
In addition, as shown in figure 21, in the three-phase five-electrical level inverter that above-mentioned all embodiment provide, the output of inversion unit 200 all accesses filter unit 300, and the ac output voltage of inversion unit 200 is carried out filtering.
In addition, the three-phase five-electrical level inverter among above-mentioned all embodiment all adopts the three-phase Unified Control Strategy, is about to three-phase current and is converted in two-phase rest frame or the two-phase rotating coordinate system, unifies control, to guarantee preferably magnetic balance; Simultaneously, correct the saturated of magnetic circuit by D.C. magnetic biasing control.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and General Principle as defined herein can in the situation that does not break away from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.

Claims (10)

1. a three-phase five-electrical level inverter is characterized in that, comprises direct current unit and three-phase inversion unit; Wherein,
Described direct current unit is used to described three-phase inversion unit that five level DC voltages are provided; The first input end of described direct current unit is connected to the positive pole of DC power supply, and the second input of described direct current unit is connected to the negative pole of described DC power supply; Described direct current unit comprises 3 outputs, is respectively 2 level output ends, 1 level output end and 0 level output end;
Described three-phase inversion unit comprises 3 single-phase five Level Full Bridge inversion units; Each single-phase five Level Full Bridge inversion unit comprises the 2 level inputs that are connected with described 2 level output ends, the 1 level input that is connected with described 1 level output end, the 0 level input that is connected with described 0 level output end, and the first output of output AC voltage and the second output.
2. inverter according to claim 1 is characterized in that, described direct current unit comprises the first electric capacity and the second electric capacity;
The second end of described the first electric capacity be connected the first end of electric capacity and connect, and jointly be connected to described 1 level output end;
The first end of described the first electric capacity respectively with described first input end with are connected level output end and are connected;
The second end of described the second electric capacity respectively with described the second input with is connected level output end and is connected.
3. inverter according to claim 2, it is characterized in that, described single-phase five Level Full Bridge inversion units are the first full-bridge inverting unit, or the second full-bridge inverting unit, or the 3rd full-bridge inverting unit, or the 4th full-bridge inverting unit, or the 5th full-bridge inverting unit, or the 6th full-bridge inverting unit, or the 7th full-bridge inverting unit, or eight convergent points bridge inversion unit;
Described the first full-bridge inverting unit comprises switch transistor T 11, switch transistor T 12, switch transistor T 13, switch transistor T 14, switch transistor T 15 and switch transistor T 16, diode of each switching tube reverse parallel connection; Wherein,
The second end of described switch transistor T 11 is connected with the first end of described switch transistor T 12, and jointly is connected to described the first output; The second end of described switch transistor T 13 is connected with the first end of described switch transistor T 14, and jointly is connected to described the second output; The second end of described switch transistor T 12 is connected with the second end of described switch transistor T 14, and jointly is connected to described 0 level input; The first end of described switch transistor T 11 is connected with the first end of described switch transistor T 13, and jointly is connected to the first end of described switch transistor T 15 and the second end of described switch transistor T 16; Second of described switch transistor T 15 is terminated at described 1 level input; The first end of described switch transistor T 16 is connected to described 2 level inputs;
Described the second full-bridge inverting unit comprises switch transistor T 21, switch transistor T 22, switch transistor T 23, switch transistor T 24, switch transistor T 25 and switch transistor T 26, diode of each switching tube reverse parallel connection; Wherein,
The second end of described switch transistor T 21 is connected with the first end of described switch transistor T 22, and jointly is connected to described the first output; The second end of described switch transistor T 23 is connected with the first end of described switch transistor T 24, and jointly is connected to described the second output; The first end of described switch transistor T 21 is connected with the first end of described switch transistor T 23, and jointly is connected to described 2 level inputs; The second end of described switch transistor T 22 is connected with the second end of described switch transistor T 24, and jointly is connected to the second end of described switch transistor T 25 and the first end of described switch transistor T 26; The first end of described switch transistor T 25 is connected to described 1 level input; Second of described switch transistor T 26 is terminated at described 0 level input;
Described the 3rd full-bridge inverting unit comprises switch transistor T 31, switch transistor T 32, switch transistor T 33, switch transistor T 34, switch transistor T 35 and switch transistor T 36, diode of each switching tube reverse parallel connection; Wherein,
The second end of described switch transistor T 31 is connected with the first end of described switch transistor T 32, and jointly is connected to the first end of described the first output and described switch transistor T 35; The second end of described switch transistor T 33 is connected with the first end of described switch transistor T 34, and jointly is connected to described the second output; The first end of described switch transistor T 31 is connected with the first end of described switch transistor T 33, and jointly is connected to described 2 level inputs; The second end of described switch transistor T 32 is connected with the second end of described switch transistor T 34, and jointly is connected to described 0 level input; The second end of described switch transistor T 35 is connected with the second end of described switch transistor T 36, and the first end of described switch transistor T 36 is connected with described 1 level input;
Described the 4th full-bridge inverting unit comprises switch transistor T 41, switch transistor T 42, switch transistor T 43, switch transistor T 44, switch transistor T 45 and switch transistor T 46, diode of each switching tube reverse parallel connection; Wherein,
The second end of described switch transistor T 41 is connected with the first end of described switch transistor T 42, and jointly is connected to described the first output; The second end of described switch transistor T 43 is connected with the first end of described switch transistor T 44, and jointly is connected to described the second output; The first end of described switch transistor T 41 is connected with the first end of described switch transistor T 46 with the second end of described switch transistor T 45 respectively; The first end of described switch transistor T 45 is connected with the first end of described switch transistor T 43, and jointly is connected to described 2 level inputs; The second end of described switch transistor T 46 is connected with described 1 level input; The second end of described switch transistor T 42 is connected with the second end of described switch transistor T 44, and jointly is connected to described 0 level input;
Described the 5th full-bridge inverting unit comprises switch transistor T 51, switch transistor T 52, switch transistor T 53, switch transistor T 54, switch transistor T 55 and switch transistor T 56, diode of each switching tube reverse parallel connection; Wherein,
The second end of described switch transistor T 51 is connected with the first end of described switch transistor T 52, and jointly is connected to described the first output; The second end of described switch transistor T 53 is connected with the first end of described switch transistor T 54, and jointly is connected to described the second output; The second end of described switch transistor T 52 respectively with the first end of described switch transistor T 55 be connected the second end of switch transistor T 56 and be connected; The second end of described switch transistor T 55 is connected with the second end of described switch transistor T 54, and jointly is connected to described 0 level input; The first end of described switch transistor T 56 is connected with described 1 level input; The first end of described switch transistor T 51 is connected with the first end of described switch transistor T 53, and jointly is connected to described 2 level inputs;
Described the 6th full-bridge inverting unit comprises diode D61, diode D62, switch transistor T 61, switch transistor T 62, switch transistor T 63, switch transistor T 64, switch transistor T 65 and switch transistor T 66, diode of each switching tube reverse parallel connection; Wherein,
The second end of described switch transistor T 61 is connected with the first end of described switch transistor T 62, and jointly is connected to described the first output; The second end of described switch transistor T 63 is connected with the first end of described switch transistor T 64, and jointly is connected to described the second output; The first end of described switch transistor T 61 respectively with the second end of described switch transistor T 65 be connected the negative electrode of diode D61 and be connected; The first end of described switch transistor T 65 is connected with the first end of described switch transistor T 63, and jointly is connected to described 2 level inputs; The second end of described switch transistor T 62 respectively with the first end of described switch transistor T 66 and the anodic bonding of described diode D62; The second end of described switch transistor T 66 is connected with the second end of described switch transistor T 64, and jointly is connected to described 0 level input; The anode of described diode D61 is connected with the negative electrode of described diode D62, and jointly is connected to described 1 level input;
Described the 7th full-bridge inverting unit comprises diode D71, diode D72, diode D73, diode D74, switch transistor T 71, switch transistor T 72, switch transistor T 73, switch transistor T 74 and switch transistor T 75, diode of each switching tube reverse parallel connection; Wherein,
The second end of described switch transistor T 71 is connected with the first end of described switch transistor T 72, and jointly is connected to described the first output; The second end of described switch transistor T 73 is connected with the first end of described switch transistor T 74, and jointly is connected to described the second output; The first end of described switch transistor T 71 is connected with the first end of described switch transistor T 73, and jointly is connected to described 2 level inputs; The second end of described switch transistor T 72 is connected with the second end of described switch transistor T 74, and jointly is connected to described 0 level input; The negative electrode of described diode D71 is connected with the negative electrode of described diode D73, and jointly is connected to the first end of described switch transistor T 75; The anodic bonding of the anode of described diode D72 and described diode D74, and jointly be connected to the second end of described switch transistor T 75; The anode of described diode D73 is connected with the negative electrode of described diode D74, and jointly is connected to the first end of described switch transistor T 72; The anode of described diode D71 is connected with the negative electrode of described diode D72, and jointly is connected to described 1 level input;
Described eight convergent points bridge inversion unit comprises diode D81, diode D82, the first inductance, the second inductance, switch transistor T 81, switch transistor T 82, switch transistor T 83, switch transistor T 84, switch transistor T 85 and switch transistor T 86, diode of each switching tube reverse parallel connection; Wherein,
The second end of described the first inductance is connected by electric capacity with the second end of described the second inductance; The second end of described switch transistor T 81 is connected with the first end of described switch transistor T 82, and jointly is connected to described the first output; The second end of described switch transistor T 83 is connected with the first end of described switch transistor T 84, and jointly is connected to described the second output; The first end of described switch transistor T 81 is connected with the first end of described switch transistor T 83, and jointly is connected to the second end of described the first inductance; The first end of described the first inductance respectively with the second end of described switch transistor T 85 be connected the negative electrode of diode D81 and be connected; The first end of described switch transistor T 85 is connected with described 2 level inputs; The anode of described diode D81 is connected with the negative electrode of described diode D82, and jointly is connected to described 1 level input; The second end of described switch transistor T 82 is connected with the second end of described switch transistor T 84, and jointly is connected to the second end of described the second inductance; The first end of described the second inductance respectively with the anode of described diode D82 be connected the first end of switch transistor T 86 and be connected; The second end of described switch transistor T 86 is connected with described 0 level input.
4. inverter according to claim 1 is characterized in that, described direct current unit comprises boosting unit and the second electric capacity, described boosting unit comprise the first electric capacity and with the boost booster circuit of described the first Capacitance parallel connection;
The second end of described the first electric capacity be connected the first end of electric capacity and connect, and jointly be connected to described 1 level output end and first input end; The first end of described the first electric capacity is connected to described 2 level output ends; The second end of described the second electric capacity respectively with described the second input with is connected level output end and is connected.
5. inverter according to claim 4, it is characterized in that, described single-phase five Level Full Bridge inversion units comprise switch transistor T 11, switch transistor T 12, switch transistor T 13, switch transistor T 14, switch transistor T 15 and switch transistor T 16, diode of each switching tube reverse parallel connection; Wherein,
The second end of described switch transistor T 11 is connected with the first end of described switch transistor T 12, and jointly is connected to described the first output; The second end of described switch transistor T 13 is connected with the first end of described switch transistor T 14, and jointly is connected to described the second output; The second end of described switch transistor T 12 is connected with the second end of described switch transistor T 14, and jointly is connected to described 0 level input; The first end of described switch transistor T 11 is connected with the first end of the 3rd switch transistor T 13, and jointly is connected to the first end of described switch transistor T 15 and the second end of described switch transistor T 16; Second of described switch transistor T 15 is terminated at described 1 level input; The first end of described switch transistor T 16 is connected to described 2 level inputs.
6. according to claim 4 or 5 described inverters, it is characterized in that described boosting unit has 3.
7. inverter according to claim 1 is characterized in that, described direct current unit comprises the first electric capacity and boosting unit, described boosting unit comprise the second electric capacity and with the boost booster circuit of described the second Capacitance parallel connection;
The second end of described the first electric capacity be connected the first end of electric capacity and connect, and jointly be connected to described 1 level output end and the second input; The first end of described the first electric capacity respectively with described first input end be connected 2 level output ends and be connected; The second end of described the second electric capacity is connected with described 0 level output end.
8. inverter according to claim 7, it is characterized in that, described single-phase five Level Full Bridge inversion units comprise switch transistor T 21, switch transistor T 22, switch transistor T 23, switch transistor T 24, switch transistor T 25 and switch transistor T 26, diode of each switching tube reverse parallel connection; Wherein,
The second end of described switch transistor T 21 is connected with the first end of described switch transistor T 22, and jointly is connected to described the first output; The second end of described switch transistor T 23 is connected with the first end of described switch transistor T 24, and jointly is connected to described the second output; The first end of described switch transistor T 21 is connected with the first end of described switch transistor T 23, and jointly is connected to described 2 level inputs; The second end of described switch transistor T 22 is connected with the second end of described switch transistor T 24, and jointly is connected to the second end of described switch transistor T 25 and the first end of described switch transistor T 26; The first end of described switch transistor T 25 is connected to described 1 level input; Second of described switch transistor T 26 is terminated at described 0 level input.
9. according to claim 7 or 8 described inverters, it is characterized in that described boosting unit has 3.
10. inverter according to claim 1 is characterized in that, also comprises filter unit; The first output of described filter unit and described single-phase five Level Full Bridge inversion units be connected output and be connected.
CN2012105276894A 2012-12-10 2012-12-10 Three-phase five-level inverter Pending CN103051231A (en)

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