CN102780411A

CN102780411A - Inversion unit and five-level inverter with same

Info

Publication number: CN102780411A
Application number: CN2012102725868A
Authority: CN
Inventors: 汪洪亮; 宋炀
Original assignee: Sungrow Power Supply Co Ltd
Current assignee: Sungrow Power Supply Co Ltd
Priority date: 2012-07-31
Filing date: 2012-07-31
Publication date: 2012-11-14
Anticipated expiration: 2032-07-31
Also published as: CN102780411B

Abstract

The invention discloses an inversion unit. A switch tube T1 is connected in parallel with a diode D1; a switch tube T2 is connected in parallel with a diode D2; a switch tube T3 is connected in parallel with a diode D3; a switch tube T4 is connected in parallel with a diode D4; a switch tube T5 is connected in parallel with a diode T5; the switch tube T2 is connected in series with a diode DF1; one end (where an emitting electrode is located) in a series connection circuit is connected with a common end of an emitting electrode of the switch tube T1 and a collector electrode of the switch tube T5; the switch tube T4 is connected in series with a diode DF2; one end (where a collector electrode is located) in the series connection circuit is connected with the common end of the emitting electrode of the switch tube T1 and the collector electrode of the switch tube T5; the switch tube T3 is connected in parallel with a first branch and a second branch; the first branch comprises a diode DA1 and a diode DB2 which are connected in series; the second branch comprises a diode DB1 and a diode DA2 which are connected in series; and a common end of the diode DB1 and the diode DA2 is connected with the common end of the emitting electrode of the switch tube T1 and the collector electrode of the switch tube T5.

Description

Inversion unit and have the five-electrical level inverter of this inversion unit

Technical field

The application relates to electric and electronic technical field, particularly a kind of inversion unit and have the five-electrical level inverter of this inversion unit.

Background technology

The big capacity occasion of middle pressure, multi-electrical level inverter is widely used, and present five-electrical level inverter mainly is a diode-clamped.Introduce in the face of the diode-clamped five-level inverter down.

Referring to Fig. 1; The diode-clamped five-level inverter comprises: power subsystem 101, inversion unit 102 and filtering and net unit 103; Wherein: power subsystem 101

generation

2,1,0 ,-1 and-2 five kind of level; Above-mentioned five kinds of level are alternating current through inversion unit 102 inversions, again the alternating current of formation standard after the effect of filtering and net unit 103.

Yet the inversion unit in the five-electrical level inverter of prior art comprises eight switching tubes; Each switching tube all is parallel with diode; Also comprise DB1, DB2, DB3, DB4, DB5 and six clamping diodes of DB6, make the complex structure of inversion unit, and cost is higher.

Summary of the invention

The application provides a kind of inversion unit and has the five-electrical level inverter of this inversion unit, to solve the problem that the conventional inversion cellular construction is complicated, cost is high.

For addressing the above problem, the existing scheme that proposes is following:

A kind of inversion unit comprises: switch transistor T 1, switch transistor T 2, switch transistor T 3, switch transistor T 4 and switch transistor T 5; Wherein:

Said switch transistor T 1 reverse parallel connection has diode D1, and said switch transistor T 2 reverse parallel connections have diode D2, and said switch transistor T 3 reverse parallel connections have diode D3, and said switch transistor T 4 reverse parallel connections have diode D4, and said switch transistor T 5 reverse parallel connections have diode D5;

Said switch transistor T 2 is in series with diode DF 1, and the residing end of emitter links to each other with the emitter of said switch transistor T 1 and the common port of the collector electrode of switch transistor T 5 in this series circuit;

Said switch transistor T 4 is in series with diode DF2, and the residing end of collector electrode links to each other with the emitter of said switch transistor T 1 and the common port of the collector electrode of switch transistor T 5 in this series circuit;

Said switch transistor T 3 is parallel with first branch road and second branch road, and said first branch road comprises the diode DA1 and the diode DB2 of differential concatenation, and said second branch road comprises the diode DB1 and the diode DA2 of differential concatenation;

The common port of said diode DB1 and diode DA2 links to each other with the common port of switch transistor T 1 emitter with switch transistor T 5 collector electrodes.

A kind of five-electrical level inverter comprises: power subsystem, three inversion units and filtering and net unit, wherein:

Said inversion unit input links to each other with the output of said power subsystem; Said filtering and net unit link to each other with the output of said inversion unit; Said inversion unit comprises: switch transistor T 1, switch transistor T 2, switch transistor T 3, switch transistor T 4 and switch transistor T 5;

Said switch transistor T 1 reverse parallel connection has diode D1; The collector electrode of said switch transistor T 1 is as 2 level inputs of said inversion unit; Said switch transistor T 2 reverse parallel connections have diode D2, and said switch transistor T 3 reverse parallel connections have diode D3, and said switch transistor T 4 reverse parallel connections have diode D4; Said switch transistor T 5 reverse parallel connections have diode D5, and the emitter of said switch transistor T 5 is as-2 level inputs of said inversion unit;

Said switch transistor T 2 is in series with diode DF1, and the residing end of emitter links to each other with the emitter of said switch transistor T 1 and the common port of the collector electrode of switch transistor T 5 in this series circuit, and the residing end of collector electrode is as 1 level input of said inversion unit;

Said switch transistor T 4 is in series with diode DF2, and the residing end of collector electrode links to each other with the emitter of said switch transistor T 1 and the common port of the collector electrode of switch transistor T 5 in this series circuit, and the residing end of emitter is as-1 level input of said inversion unit;

Said switch transistor T 3 is parallel with first branch road and second branch road; Said first branch road comprises the diode DA1 and the diode DB2 of differential concatenation; The common port of said diode DA1 and diode DB2 is as 0 level input of said inversion unit, and said second branch road comprises the diode DB1 and the diode DA2 of differential concatenation;

The common port of said diode DB1 and diode DA2; Link to each other with the common port of switch transistor T 1 emitter with switch transistor T 5 collector electrodes, the link of said diode DB1, diode DA2, switch transistor T 1 emitter and switch transistor T 5 collector electrodes is as the output of said inversion unit.

Preferably, said power subsystem comprises:

DC source;

Be connected in parallel on the 3rd branch road at said DC source two ends, said the 3rd branch road comprises the capacitor C A1 and the capacitor C B1 of series connection;

The inductance L 1 that one end links to each other with said capacitor C A1, said inductance L 1 other end is connected with diode DD1;

The inductance L 2 that one end links to each other with said capacitor C B1, said inductance L 2 other ends oppositely are connected with diode DD2;

The switch transistor T D1 that collector electrode links to each other with the common port of said inductance L 1 and diode DD1, the emitter of said switch transistor T D1 links to each other with the common port of capacitor C B1 with said capacitor C A1;

The capacitor C A2 that one end links to each other with said diode DD1, the other end of said capacitor C A2 links to each other with the common port of capacitor C B1 with said capacitor C A1;

The switch transistor T D2 that emitter links to each other with the common port of said inductance L 2 and diode DD2, the collector electrode of said switch transistor T D2 links to each other with the common port of capacitor C B 1 with said capacitor C A1;

The capacitor C B2 that one end links to each other with said diode DD2, the other end of said capacitor C B2 links to each other with the common port of capacitor C B1 with said capacitor C A1.

Preferably, said power subsystem comprises:

DC source;

Be connected in parallel on the 4th branch road at said DC source two ends, said the 4th branch road comprises the capacitor C A3 and the capacitor C B3 of series connection;

The inductance L 3 that one end links to each other with said capacitor C A3, said inductance L 3 other ends are connected with diode DD3;

The inductance L 4 that one end links to each other with said capacitor C B3, said inductance L 4 other ends oppositely are connected with diode DD4;

The switch transistor T D3 that collector electrode links to each other with the common port of said inductance L 3 and diode DD3, the emitter of said switch transistor T D3 links to each other with the common port of capacitor C B3 with said capacitor C A3;

The capacitor C A4 that one end links to each other with said diode DD3, the other end of said capacitor C A4 links to each other with said DC source;

The switch transistor T D4 that emitter links to each other with the common port of said inductance L 4 and diode DD4, the collector electrode of said switch transistor T D4 links to each other with the common port of capacitor C B3 with said capacitor C A3;

The capacitor C B4 that one end links to each other with said diode DD4, the other end of said capacitor C B4 links to each other with said DC source.

Preferably, said power subsystem comprises:

Two DC sources of both positive and negative polarity butt joint;

Be connected in parallel on the 6th branch road at said DC source two ends, said the 6th branch road comprises the capacitor C A5 and the capacitor C B5 of series connection, and the common port of said capacitor C A5 and capacitor C B5 links to each other with the common port of said two DC sources;

The inductance L 5 that one end links to each other with said capacitor C A5, said inductance L 5 other ends are connected with diode DD5;

The inductance L 6 that one end links to each other with said capacitor C B5, said inductance L 6 other ends oppositely are connected with diode DD6;

The switch transistor T D5 that collector electrode links to each other with the common port of said inductance L 5 and diode DD5, the emitter of said switch transistor T D5 links to each other with the common port of capacitor C B5 with said capacitor C A5;

The capacitor C A6 that one end links to each other with said diode DD5, the other end of said capacitor C A6 links to each other with the common port of capacitor C B5 with said capacitor C A5;

The switch transistor T D6 that emitter links to each other with the common port of said inductance L 6 and diode DD6, the collector electrode of said switch transistor T D6 links to each other with the common port of capacitor C B5 with said capacitor C A5;

The capacitor C B6 that one end links to each other with said diode DD6, the other end of said capacitor C B6 links to each other with the common port of capacitor C B5 with said capacitor C A5.

Preferably, said power subsystem comprises:

First and second DC sources of both positive and negative polarity butt joint;

Be connected in parallel on the 7th branch road at said DC source two ends, said the 7th branch road comprises the capacitor C A7 and the capacitor C B7 of series connection, and the common port of said capacitor C A7 and capacitor C B7 links to each other with the common port of said two DC sources;

The inductance L 7 that one end links to each other with said capacitor C A7, said inductance L 7 other ends are connected with diode DD7;

The inductance L 8 that one end links to each other with said capacitor C B7, said inductance L 8 other ends oppositely are connected with diode DD8;

The switch transistor T D7 that collector electrode links to each other with the common port of said inductance L 7 and diode DD7, the emitter of said switch transistor T D7 links to each other with the common port of capacitor C B7 with said capacitor C A7;

The capacitor C A8 that one end links to each other with said diode DD7, the other end of said capacitor C A8 links to each other with said first DC source;

The switch transistor T D8 that emitter links to each other with the common port of said inductance L 8 and diode DD8, the collector electrode of said switch transistor T D8 links to each other with the common port of capacitor C B7 with said capacitor C A7;

The capacitor C B8 that one end links to each other with said diode DD8, the other end of said capacitor C B8 links to each other with said second DC source.

Preferably, the said filtering unit that is incorporated into the power networks comprises:

The inductance L 11 that links to each other with the first inversion unit output; The inductance L 12 that links to each other with the second inversion unit output; The inductance L 13 that links to each other with the 3rd inversion unit output; Said inductance L 11, inductance L 12 and inductance L 13 are connected with alternating current source respectively;

Be connected the branch road between said inductance L 11 and the inductance L 12, said branch road comprises the capacitor C 1 and capacitor C 2 of series connection;

Be connected the capacitor C 3 between said inductance L 13 and the capacitor C 2.

Be connected the capacitor C 3 between said inductance L 13 and the capacitor C 2;

The common port of said capacitor C 1, capacitor C 2 and capacitor C 3 links to each other with 0 output of power subsystem.

A kind of five-electrical level inverter comprises: power subsystem, four inversion units and filtering and net unit, wherein:

Said inversion unit input links to each other with the output of said power subsystem; Said filtering and net unit link to each other with the output of said inversion unit; Said inversion unit comprises: switch transistor T 1, switch transistor T 2, switch transistor T 3, switch transistor T 4 and switch transistor T 5; Wherein:

Preferably, the power subsystem of this five-electrical level inverter also has four kinds of forms, and is identical with the described four kinds of power subsystem structures of preamble, do not giving unnecessary details at this.

The inductance L 14 that links to each other with the first inversion unit output; The inductance L 15 that links to each other with the second inversion unit output; The inductance L 16 that links to each other with the 3rd inversion unit output; Said inductance L 14, inductance L 15 and inductance L 16 are connected with alternating current source respectively;

Be connected the branch road between said inductance L 14 and the inductance L 15, said branch road comprises the capacitor C 4 and capacitor C 5 of series connection, and the common port of said capacitor C 4 and capacitor C 5 links to each other with the 4th inversion unit output;

Be connected the capacitor C 6 between said inductance L 16 and the capacitor C 5.

From the above, in the inversion unit that the application provides, reduce the quantity of switching tube, simplified circuit structure, reduced cost.

Description of drawings

In order to be illustrated more clearly in the technical scheme among the application embodiment; The accompanying drawing of required use is done to introduce simply in will describing embodiment below; Obviously, the accompanying drawing in describing below only is some embodiment of the application, for those of ordinary skills; Under the prerequisite of not paying creative work property, can also obtain other accompanying drawing according to these accompanying drawings.

Fig. 1 is diode-clamped five-level inverter topology figure in the prior art;

A kind of inversion unit circuit diagram that Fig. 2 provides for the application;

Fig. 3 (a) is in the structure chart under first operating state for a kind of inversion unit that the application embodiment provides;

Fig. 3 (b) is in the structure chart under second operating state for a kind of inversion unit that the application embodiment provides;

Fig. 3 (c) is in the structure chart under the 3rd operating state for a kind of inversion unit that the application embodiment provides;

Fig. 3 (d) is in the structure chart under the 4th operating state for a kind of inversion unit that the application embodiment provides;

Fig. 3 (e) is in the structure chart under the 5th operating state for a kind of inversion unit that the application embodiment provides;

Fig. 3 (f) is in the structure chart under the 6th operating state for a kind of inversion unit that the application embodiment provides;

Fig. 3 (g) is in the structure chart under the 7th operating state for a kind of inversion unit that the application embodiment provides;

Fig. 3 (h) is in the structure chart under the 8th operating state for a kind of inversion unit that the application embodiment provides;

The SECO figure of the inversion unit output waveform that Fig. 4 (a) provides for the application;

The SECO figure of the inversion unit output waveform that Fig. 4 (b) provides for the application;

The structure chart of the corresponding chip in a kind of five level inverse conversion unit that Fig. 5 provides for the application;

A kind of five-electrical level inverter circuit diagram that Fig. 6 provides for the application embodiment;

The circuit diagram of a kind of power subsystem that Fig. 7 (a) provides for the application embodiment;

The circuit diagram of a kind of power subsystem that Fig. 7 (b) provides for another embodiment of the application;

The circuit diagram of a kind of power subsystem that Fig. 7 (c) provides for another embodiment of the application;

The circuit diagram of a kind of power subsystem that Fig. 7 (d) provides for another embodiment of the application;

A kind of five-electrical level inverter circuit diagram that Fig. 8 provides for another embodiment of the application;

A kind of five-electrical level inverter circuit diagram that Fig. 9 provides for another embodiment of the application.

Embodiment

To combine the accompanying drawing among the application embodiment below, the technical scheme among the application embodiment is carried out clear, intactly description, obviously, described embodiment only is the application's part embodiment, rather than whole embodiment.Based on the embodiment among the application, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the application's protection.

The embodiment of the invention discloses a kind of inversion unit, to solve the problem that the conventional inversion cellular construction is complicated, cost is high.

As shown in Figure 2, the disclosed inversion unit of present embodiment comprises: switch transistor T 1, switch transistor T 2, switch transistor T 3, switch transistor T 4 and switch transistor T 5; Wherein:

The collector electrode of switch transistor T 1 is as the input of 2 level, the input of emitter conduct-2 level of switch transistor T 5;

Said switch transistor T 2 series diode DF1, and emitter links to each other with the emitter of said switch transistor T 1 and the common port of the collector electrode of switch transistor T 5, and concrete; Can between switch transistor T 1 emitter and switch transistor T 2 emitters, be connected with diode DF1; At this moment, the collector electrode of switch transistor T 2 also can connect diode DF1 at the collector electrode of switch transistor T 2 as the input of 1 level; At this moment, the other end of diode DF1 is as the input of 1 level;

Said switch transistor T 4 forwards connect the end of diode DF2, and the input of other end conduct-1 level of diode DF2 is same; Diode DF2 can be connected the emitter of switch transistor T 4; The collector electrode of switch transistor T 4 links to each other with the emitter of switch transistor T 1 and the common port of the collector electrode of switch transistor T 5, or diode DF2 is connected between the emitter of collector electrode and switch transistor T 1 of switch transistor T 4; At this moment, the input of emitter conduct-1 level of switch transistor T 4;

Said switch transistor T 3 is parallel with first branch road and second branch road, and said first branch road comprises the diode DA1 and the diode DB2 of differential concatenation, and said second branch road comprises the diode DB1 and the diode DA2 of differential concatenation; The common port of diode DA1 and diode DB2 is as the input of 0 level;

The common port of said diode DB1 and diode DA2 links to each other with the common port of switch transistor T 1 emitter with switch transistor T 5 collector electrodes, and the common port of diode DB1 and diode DA2 is as output.

In the disclosed inversion unit of present embodiment,, only adopt five switching tubes, reduced the quantity of switching tube, simplified circuit structure, reduced cost with respect to inversion unit of the prior art.

And, the disclosed inversion unit of present embodiment,

reception

2,1,0 ,-1 and-2 five kind of level fit to sine wave with five kinds of above-mentioned level, like Fig. 3 (a) with (b), wherein, V ₂Refer to 2 level, V ₁Refer to 1 level, 0 refers to 0 level ,-V ₁Refer to-1 level ,-V ₂Refer to-2 level.Below in conjunction with Fig. 2, Fig. 4 (a) with (b) the inversion process of inversion unit is described.

Inversion unit comprises eight kinds of operation modes, and is concrete:

Shown in Fig. 3 (a), first mode: switch transistor T 1 conducting, perhaps switch transistor T 1 and T2 conducting, other switching tube all ends, and electric current at this moment, is 2 level through 2 ports → T1 → AC;

Shown in Fig. 3 (b), second mode: switch transistor T 2 conductings, other switching tube all ends, and electric current at this moment, is 1 level through 1 port → T2 → DF1 → AC;

Shown in Fig. 3 (c), the 3rd mode: switch transistor T 3 conductings, other switching tube all ends, and electric current at this moment, is 0 level through 0 port → DA1 → T3 → DA2 → AC;

Shown in Fig. 3 (d), the 4th mode: switch transistor T 1 and switch transistor T 2 conductings, perhaps switch transistor T 2 conductings, other switching tube ends, and electric current at this moment, is the idle path of 2 level through AC → D1 → 2 ports;

Shown in Fig. 3 (e), the 5th mode: switch transistor T 5 conductings, perhaps switch transistor T 4 and T5 conducting, other switching tube all ends, and electric current at this moment, is-2 level through AC → T5 →-2 ports;

Shown in Fig. 3 (f), the 6th mode: switch transistor T 4 conductings, other switching tube all ends, and electric current at this moment, is-1 level through AC → T4 → DF2 →-1 port;

Shown in Fig. 3 (g), the 7th mode: switch transistor T 3 conductings, other switching tube all ends, and electric current at this moment, is 0 level through AC → DB1 → T3 → DB2 → 0 port;

Shown in Fig. 3 (h), the 8th mode: switch transistor T 4 and switch transistor T 5 conductings, perhaps switch transistor T 4 conductings, other switching tube ends, and electric current at this moment, is the idle path of-2 level through-2 ports → D5 → AC.

Sequential through above-mentioned operation mode is controlled, and just can obtain the sinusoidal ac that needs, Fig. 4 (a) with (b) be SECO figure, wherein, u is the voltage waveform that inverter is exported, establishing the minimal reverse time variant voltage that satisfies the inversion requirement is Vm.

< Vm is < during V2 as V1; Sequential by shown in Fig. 4 (a) is controlled, promptly the t0 moment～t1 constantly, t2 moment～t4 constantly and the t5 moment～t6 moment, second operation mode and the 6th operation mode alternation; The t1 moment～t2 constantly; First operation mode and the second operation mode alternation, the t4 moment～t5 moment, the 6th operation mode and the 5th operation mode alternation;

< V1 < during V2, control by the sequential shown in Fig. 4 (b), repeat no more at this referring to Fig. 3 (a) by concrete SECO as Vm.And the peak value of the sine wave after the inversion unit inversion is during less than 1 level, at this moment; The DC power supply that is illustrated as inversion unit input power supply satisfies the requirement of inversion unit inverter voltage; But, in order to reduce energy consumption, still in the t1-t2 time period; Be controlled to be the input of 2 level, the t4-t5 time period in like manner.

And the inventor studies in the disclosed inversion unit process of present embodiment and finds, inversion unit fits to five level in the sinusoidal wave process; If remove the idle path of 1 level and-1 level, little to the course of work influence of inversion unit, therefore; Get rid of the idle path of 1 level and-1 level, save the switching tube that needs in the idle path of 1 level and-1 level, formed the disclosed inversion unit of present embodiment; And realize simplifying circuit structure, the purpose that reduces cost.

The disclosed inversion unit of present embodiment when reality generates use, generally is packaged into chip with inversion unit; As shown in Figure 5; Comprise six ports, be respectively 0 level, 1 level, 2 level ,-1 level and five input ports of-2 level, also comprise the AC output port.

The embodiment of the invention also discloses a kind of five-electrical level inverter, be applicable to three-phase three wire system, as shown in Figure 6, comprising: power subsystem, three inversion units and filtering and net unit, wherein:

Said inversion unit input links to each other with the output of said power subsystem; Said filtering and net unit link to each other with the output of said inversion unit; Concrete: the disclosed power subsystem of present embodiment can be exported 0 level, 1 level, 2 level ,-1 level and five kinds of level of-2 level; 0 level of said inversion unit, 1 level, 2 level ,-1 level and five input ports of-2 level link to each other with the corresponding output of said power subsystem respectively; The AC output port of said inversion unit links to each other with said filtering and net unit;

The disclosed inversion unit of present embodiment is identical, as shown in Figure 2 with the disclosed inversion unit structure of the foregoing description, comprising: switch transistor T 1, switch transistor T 2, switch transistor T 3, switch transistor T 4 and switch transistor T 5; Wherein:

Said switch transistor T 2 series diode DF1, and emitter links to each other with the emitter of said switch transistor T 1 and the common port of the collector electrode of switch transistor T 5, and concrete; Can between switch transistor T 1 emitter and switch transistor T 2 emitters, be connected with diode DF1; At this moment, the collector electrode of switch transistor T 2 also can connect diode DF 1 at the collector electrode of switch transistor T 2 as the input of 1 level; At this moment, the other end of diode DF 1 is as the input of 1 level;

The common port of said diode DB1 and diode DA2 links to each other with the common port of switch transistor T 1 emitter with switch transistor T 5 collector electrodes, and the common port of diode DB 1 and diode DA2 is as output.

As shown in Figure 6 equally, the unit that is incorporated into the power networks of the filtering in the five-electrical level inverter in the foregoing description comprises:

And, the disclosed inversion unit of present embodiment, the course of work is seen the disclosed content of the foregoing description, repeats no more here.

And in the disclosed five-electrical level inverter of the foregoing description, power subsystem has four kinds of forms, and is concrete, and referring to Fig. 7 (a), said power subsystem comprises:

DC source;

Be connected in parallel on the 3rd branch road at said DC source two ends, said the 3rd branch road comprises the capacitor C A1 and the capacitor C B1 of series connection, and the common port of capacitor C A1 and capacitor C B1 is as the output of 0 level;

The inductance L 1 that one end links to each other with said capacitor C A1, said inductance L 1 other end is connected with diode DD1, and the other end of diode DD1 is as the output of 2 level, and the common port of inductance L 1 and capacitor C A1 is as the output of 1 level;

The inductance L 2 that one end links to each other with said capacitor C B1, said inductance L 2 other ends oppositely are connected with diode DD2, the output of other end conduct-2 level of diode DD2, the output of common port conduct-1 level of inductance L 2 and capacitor C B1;

The switch transistor T D2 that emitter links to each other with the common port of said inductance L 2 and diode DD2, the collector electrode of said switch transistor T D2 links to each other with the common port of capacitor C B1 with said capacitor C A1;

The disclosed power subsystem of present embodiment, inductance L 1, diode DD1, switch transistor T D1 and capacitor C A2 form booster circuit, and it is 2 level that 1 level of power subsystem is raise, and the voltage of 2 level can not be 2 times of 1 level; Equally, inductance L 2, diode DD2, switch transistor T D2 and capacitor C B2 form booster circuit, and-1 level of power subsystem is raise is-2 level, and the voltage of-2 level can not be 2 times of-1 level yet.

Perhaps, shown in Fig. 7 (b), said power subsystem comprises:

DC source;

Be connected in parallel on the 4th branch road at said DC source two ends, said the 4th branch road comprises the capacitor C A3 and the capacitor C B3 of series connection, and the common port of capacitor C A3 and capacitor C B3 is as the output of 0 level;

The inductance L 3 that one end links to each other with said capacitor C A3, said inductance L 3 other ends are connected with diode DD3, and the other end of diode DD3 is as the output of 2 level, and the common port of inductance L 3 and capacitor C A3 is as the output of 1 level;

The inductance L 4 that one end links to each other with said capacitor C B3, said inductance L 4 other ends oppositely are connected with diode DD4, the output of other end conduct-2 level of diode DD4, the output of common port conduct-1 level of inductance L 4 and capacitor C B3;

Present embodiment is same as the previously described embodiments, and inductance L 3, diode DD3, switch transistor T D3 and capacitor C A4 form booster circuit, and it is 2 level that 1 level of power subsystem is raise, and the voltage of 2 level can not be 2 times of 1 level; Equally, inductance L 4, diode DD4, switch transistor T D4 and capacitor C B4 form booster circuit, and-1 level of power subsystem is raise is-2 level, and the voltage of-2 level can not be 2 times of-1 level yet.

Perhaps, shown in Fig. 7 (c), said power subsystem comprises:

Two DC sources of both positive and negative polarity butt joint, the common port of two DC sources is as the output of 0 level;

The inductance L 5 that one end links to each other with said capacitor C A5, said inductance L 5 other ends are connected with diode DD5, and the other end of diode DD5 is as the output of 2 level, and the common port of inductance L 5 and capacitor C A5 is as the output of 1 level;

The inductance L 6 that one end links to each other with said capacitor C B5, said inductance L 6 other ends oppositely are connected with diode DD6, the output of other end conduct-2 level of diode DD6, the output of common port conduct-1 level of inductance L 6 and capacitor C B5;

Same as the previously described embodiments, inductance L 5, diode DD5, switch transistor T D5 and capacitor C A6 form booster circuit, and it is 2 level that 1 level of power subsystem is raise, and the voltage of 2 level can not be 2 times of 1 level; Equally, inductance L 6, diode DD6, switch transistor T D6 and capacitor C B6 form booster circuit, and-1 level of power subsystem is raise is-2 level, and the voltage of-2 level can not be 2 times of-1 level yet.

Perhaps, shown in Fig. 7 (d), said power subsystem comprises:

The inductance L 7 that one end links to each other with said capacitor C A7, said inductance L 7 other ends are connected with diode DD7, and the other end of diode DD7 is as the output of 2 level, and the common port of inductance L 7 and capacitor C A7 is as the output of 1 level;

The inductance L 8 that one end links to each other with said capacitor C B7, said inductance L 8 other ends oppositely are connected with diode DD8, the output of other end conduct-2 level of diode DD8, the output of inductance L 8 and capacitor C B7 common port conduct-1 level;

The capacitor C A8 that one end links to each other with said diode DD7, the other end of said capacitor C A8 links to each other with said DC source;

The capacitor C B8 that one end links to each other with said diode DD8, the other end of said capacitor C B8 links to each other with said another DC source.

Same as the previously described embodiments, inductance L 7, diode DD7, switch transistor T D7 and capacitor C A8 form booster circuit, and it is 2 level that 1 level of power subsystem is raise, and the voltage of 2 level can not be 2 times of 1 level; Equally, inductance L 8, diode DD8, switch transistor T D8 and capacitor C B8 form booster circuit, and-1 level of power subsystem is raise is-2 level, and the voltage of-2 level can not be 2 times of-1 level yet.

When the disclosed five-electrical level inverter of the foregoing description is applicable to three-phase four wire system, as shown in Figure 7, except that comprising, also comprise as disclosed power subsystem of above-mentioned embodiment and the inversion unit: filtering and net unit, wherein: the said filtering unit that is incorporated into the power networks comprises:

The common port of capacitor C 1, capacitor C 2 and capacitor C 3 links to each other with 0 output of power subsystem.

Another embodiment of the present invention also discloses a kind of five-electrical level inverter, and is as shown in Figure 9, comprising: power subsystem, four inversion units and filtering and net unit, wherein:

The disclosed inversion unit of present embodiment is identical with the disclosed inversion unit structure of the foregoing description, and said inversion unit is as shown in Figure 2, comprising:

Switch transistor T 1, switch transistor T 2, switch transistor T 3, switch transistor T 4 and switch transistor T 5; Wherein:

And as shown in Figure 9 equally, the said filtering unit that is incorporated into the power networks comprises:

In the disclosed five-electrical level inverter of present embodiment, power subsystem also has four kinds of forms, and referring to Fig. 7 (a), said power subsystem comprises equally:

DC source;

Perhaps, shown in Fig. 7 (b), said power subsystem comprises:

DC source;

Be connected in parallel on the 4th branch road at said DC source two ends, said the 3rd branch road comprises the capacitor C A3 and the capacitor C B3 of series connection, and the common port of capacitor C A3 and capacitor C B3 is as the output of 0 level;

Perhaps, shown in Fig. 7 (c), said power subsystem comprises:

Perhaps, shown in Fig. 7 (d), said power subsystem comprises:

Need to prove that each embodiment in this specification all adopts the mode of going forward one by one to describe, what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.

At last; Also need to prove; In this article; Relational terms such as first and second grades only is used for an entity or operation are made a distinction with another entity or operation, and not necessarily requires or hint relation or the order that has any this reality between these entities or the operation.And; Term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability; Thereby make and comprise that process, method, article or the equipment of a series of key elements not only comprise those key elements; But also comprise other key elements of clearly not listing, or also be included as this process, method, article or equipment intrinsic key element.Under the situation that do not having much more more restrictions, the key element that limits by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises said key element and also have other identical element.

More than a kind of five level inverse conversion topology unit and five-electrical level inverter that the application provided have been carried out detailed introduction; Used concrete example among this paper the application's principle and execution mode are set forth, the explanation of above embodiment just is used to help to understand the application's method and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to the application's thought, the part that on embodiment and range of application, all can change, in sum, this description should not be construed as the restriction to the application.

Claims

1. an inversion unit is characterized in that, comprising: switch transistor T 1, switch transistor T 2, switch transistor T 3, switch transistor T 4 and switch transistor T 5; Wherein:

Said switch transistor T 2 is in series with diode DF1, and the residing end of emitter links to each other with the emitter of said switch transistor T 1 and the common port of the collector electrode of switch transistor T 5 in this series circuit;

2. a five-electrical level inverter is characterized in that, comprising: power subsystem, three inversion units and filtering and net unit, wherein:

3. five-electrical level inverter according to claim 2 is characterized in that, said power subsystem comprises:

DC source;

4. five-electrical level inverter according to claim 2 is characterized in that, said power subsystem comprises:

DC source;

5. five-electrical level inverter according to claim 2 is characterized in that, said power subsystem comprises:

Two DC sources of both positive and negative polarity butt joint;

6. five-electrical level inverter according to claim 2 is characterized in that, said power subsystem comprises:

First and second DC sources of both positive and negative polarity butt joint;

7. according to any described five-electrical level inverter among the claim 2-6, it is characterized in that the said filtering unit that is incorporated into the power networks comprises:

8. according to any described five-electrical level inverter among the claim 2-6, it is characterized in that the said filtering unit that is incorporated into the power networks comprises:

9. a five-electrical level inverter is characterized in that, comprising: power subsystem, four inversion units and filtering and net unit, wherein:

The common port of said diode DB1 and diode DA2; Link to each other with the common port of switch transistor T 1 emitter with switch transistor T 5 collector electrodes, the link of said diode DB 1, diode DA2, switch transistor T 1 emitter and switch transistor T 5 collector electrodes is as the output of said inversion unit.

10. five-electrical level inverter according to claim 9 is characterized in that, said power subsystem comprises:

DC source;

11. five-electrical level inverter according to claim 9 is characterized in that, said power subsystem comprises:

DC source;

12. five-electrical level inverter according to claim 9 is characterized in that, said power subsystem comprises:

First and second DC sources of both positive and negative polarity butt joint;

13. five-electrical level inverter according to claim 9 is characterized in that, said power subsystem comprises:

First and second DC sources of both positive and negative polarity butt joint;

14., it is characterized in that the said filtering unit that is incorporated into the power networks comprises according to any described five-electrical level inverter among the claim 9-13: