CN102751895B

CN102751895B - Multi-level circuit, grid-connected inverter and modulation method of grid-connected inverter

Info

Publication number: CN102751895B
Application number: CN201210193018.9A
Authority: CN
Inventors: 汪洪亮; 赵为
Original assignee: Sungrow Power Supply Co Ltd
Current assignee: Sungrow Power Supply Co Ltd
Priority date: 2012-06-12
Filing date: 2012-06-12
Publication date: 2014-12-03
Anticipated expiration: 2032-06-12
Also published as: CN102751895A

Abstract

The invention relates to a multi-level circuit, which comprises a first direct-current booster circuit, a second direct-current booster circuit and a symmetrical dual-buck circuit connected with a direct-current power supply in parallel, wherein the symmetrical dual-buck circuit is implemented in a manner that a first capacitor and a second capacitor are connected to the two sides of the direct-current power supply in parallel after being connected with each other in series, a first diode and a second diode are connected with the direct-current power supply in parallel after being connected with each other in series, a first switch tube is arranged between the first capacitor and the first diode, and a second switch tube is arranged between the second capacitor and the second diode; a first inductor is arranged between the first diode and a third capacitor, and a second inductor is arranged between the common end of the second switch tube and the second diode, and the third capacitor; and the common end of the first capacitor and the second capacitor is directly connected with the common end of the first diode and the second diode. The multi-level circuit, a grid-connected inverter and a control method of the grid-connected inverter, provided by the invention, can avoid current leakage and realize high efficiency.

Description

A kind of multi-level circuit, combining inverter and modulator approach thereof

Technical field

The present invention relates to electric and electronic technical field, particularly a kind of multi-level circuit, combining inverter and modulator approach thereof.

Background technology

The classification of inverter, be generally can be divided into from net type inverter and grid type inverter according to the difference of inverter applications occasion and control mode, in grid type inverter, whether basis can be divided into transformer isolation type inverter and inverter without transformer again with transformer.

The plurality of advantages such as inverter without transformer is because system configuration is simple, and efficiency is high, and volume is little, and cost is low, have obtained development fast.

But inverter without transformer is due to the electrical isolation that can not realize between direct current input source and AC load, and leakage problem is one of key index of its reliability.

For obtaining higher efficiency, often adopt unipolarity modulation strategy, traditional H4 topology can not be taken into account leakage current and high efficiency simultaneously.The high frequency common mode voltage producing for eliminating Unipolar SPWM modulation, must make clamped half at solar array voltage of the continuous current circuit in afterflow stage, just can reach the object of eliminating common-mode voltage leakage current.Employing modified model topology, as H5, H6, Heric topology, has realized unipolarity modulation strategy, has solved to a certain extent leakage problem, and its brachium pontis output voltage is equivalent to three level outputs.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of multi-level circuit, combining inverter and modulator approach thereof and system, realizes the problem of taking into account leakage current and high efficiency two aspects.

The invention provides a kind of multi-level circuit, the symmetric double Buck circuit that described multi-level circuit comprises first and second DC voltage booster circuit, is in parallel with DC power supply;

Described the first DC voltage booster circuit comprises: the first DC chopper and the 4th capacitances in series, and the negative busbar end of DC power supply is connected with the 4th electric capacity, and the positive bus-bar end of DC power supply connects the first DC chopper;

Between the common port of described the first DC chopper and the 4th electric capacity and the first switching tube and the common port of the first diode, be connected with the 9th switching tube;

Described the second DC voltage booster circuit also comprises: the series connection of the 5th electric capacity and the second DC chopper, and the negative busbar end of DC power supply is connected with the second DC chopper, positive bus-bar end connection the 5th electric capacity of DC power supply;

Between the common port of second switch pipe and the second diode and described the second DC chopper and the common port of the 5th electric capacity, be connected with the tenth switching tube;

Described symmetric double Buck circuit comprises: after the first electric capacity and the second capacitances in series, be connected in parallel on described DC power supply both sides, in parallel with described DC power supply after the first diode and the series connection of the second diode, between the first electric capacity and the first diode, be provided with the first switching tube, between the second diode and the second electric capacity, be provided with second switch pipe; Between the common port of the first diode and the first switching tube and seven level circuit outputs, be provided with the first inductance, between the common port of second switch pipe and the second diode and seven level circuit outputs, be provided with the second inductance; The first electric capacity is directly connected with the tie point of the second diode with the first diode with the tie point of the second electric capacity.

Compared with prior art, the present invention has the following advantages:

Multi-level circuit described in the embodiment of the present invention, the symmetric double Buck circuit that comprises DC voltage booster circuit, is in parallel with DC power supply due to circuit; During described DC voltage booster circuit work, can realize many level adjustment mode and work.

When described in the embodiment of the present invention, multi-level circuit is applied to combining inverter, can meet when DC power output voltage can not reach requiring of inverter voltage, thereby the requirement of the inverter voltage that boosts by DC voltage booster circuit realizes inversion.

The modulator approach of combining inverter described in the embodiment of the present invention, the first half period and the second half period at modulating wave are that the 3rd mode C and the 4th mode D appear in compartment of terrain, the voltage fluctuation producing in the first capacitor C 1 of two Buck circuit and the second capacitor C 2 in the time of can effectively offsetting the 3rd mode C and the 4th mode D like this.And continuous discharge and the lasting charging interval of first and second capacitor C 1, C2 and first and second inductance L 1, L2 are all shorter, greatly reduced the voltage undulation of first and second capacitor C 1, C2 and first and second inductance L 1, L2, thereby the ripple that reduces output voltage, has improved output waveform.And modulator approach and the device of combining inverter described in the embodiment of the present invention, can be so that switching tube, according to the regulative mode work of five level or seven level, have improved efficiency.Because number of levels increases, the voltage difference between level reduces simultaneously, and common-mode voltage is corresponding minimizing also, thereby has suppressed leakage current.

Accompanying drawing explanation

Fig. 1 is that multi-level circuit of the present invention is applied to combining inverter the first embodiment circuit diagram;

Fig. 2 is that multi-level circuit of the present invention is applied to combining inverter the second embodiment circuit diagram;

Fig. 3 a is the first operation mode A schematic diagram of embodiment of the present invention multi-level circuit;

Fig. 3 b is the second operation mode B schematic diagram of embodiment of the present invention multi-level circuit;

Fig. 3 c is the third operation mode C schematic diagram of embodiment of the present invention multi-level circuit;

Fig. 3 d is the 4th kind of operation mode D schematic diagram of embodiment of the present invention multi-level circuit;

Fig. 3 e is the 5th kind of operation mode E schematic diagram of embodiment of the present invention multi-level circuit;

Fig. 3 f is the 5th kind of operation mode F schematic diagram of embodiment of the present invention multi-level circuit;

Fig. 3 g is the 5th kind of operation mode G schematic diagram of embodiment of the present invention multi-level circuit;

Fig. 4 is the schematic diagram of modulator approach first embodiment of five level circuits in combining inverter described in the embodiment of the present invention;

Fig. 5 a is the schematic diagram of modulator approach first embodiment of seven level circuits in combining inverter described in the embodiment of the present invention;

Fig. 5 b is the schematic diagram of modulator approach second embodiment of seven level circuits in combining inverter described in the embodiment of the present invention;

Fig. 5 c is the schematic diagram of modulator approach the 3rd embodiment of seven level circuits in combining inverter described in the embodiment of the present invention;

Fig. 6 is the schematic diagram of modulator approach the 5th embodiment of seven level circuits in combining inverter described in the embodiment of the present invention;

Fig. 7 is the schematic diagram of modulator approach the 6th embodiment of seven level circuits in combining inverter described in the embodiment of the present invention;

Fig. 8 is the schematic diagram of modulator approach the 7th embodiment of seven level circuits in combining inverter described in the embodiment of the present invention;

Fig. 9 A is the schematic diagram of modulator approach first embodiment of nine level circuits in combining inverter described in the embodiment of the present invention;

Fig. 9 B is the schematic diagram of modulator approach second embodiment of nine level circuits in combining inverter described in the embodiment of the present invention;

Fig. 9 C is the schematic diagram of modulator approach the 3rd embodiment of nine level circuits in combining inverter described in the embodiment of the present invention;

Figure 10 A is the schematic diagram of modulator approach first embodiment of 11 level circuits in combining inverter described in the embodiment of the present invention;

Figure 10 B is the schematic diagram of modulator approach second embodiment of 11 level circuits in combining inverter described in the embodiment of the present invention.

Embodiment

For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.

Referring to Fig. 1, this is that multi-level circuit of the present invention is applied to combining inverter the first embodiment circuit diagram.

Multi-level circuit described in first embodiment of the invention, the symmetric double Buck circuit that comprises DC voltage booster circuit, is in parallel with DC power supply.

Described the first DC voltage booster circuit comprises: the first DC chopper and the 4th capacitor C B1 series connection, and the negative busbar end of DC power supply is connected with the 4th capacitor C B1, and the positive bus-bar end of DC power supply connects the first DC chopper;

Between the common port of described the first DC chopper and the 4th capacitor C B1 and the first switch transistor T 1 and the common port of the first diode D1, be connected with the 9th switch transistor T B3;

Described the second DC voltage booster circuit also comprises: the series connection of the 5th capacitor C B2 and the second DC chopper, and the negative busbar end of DC power supply is connected with the second DC chopper, positive bus-bar end connection the 5th capacitor C B2 of DC power supply;

Between the common port of second switch pipe T2 and the second diode D2 and described the second DC chopper and the common port of the 5th capacitor C B2, be connected with the tenth switch transistor T B4.

Described symmetric double Buck circuit comprises: after the first capacitor C 1 and the second capacitor C 2 series connection, be connected in parallel on described DC power supply both sides, in parallel with described DC power supply after the first diode D1 and the second diode D2 series connection, between the first capacitor C 1 and the first diode D1, be provided with between the first switch transistor T 1, the second diode D2 and the second capacitor C 2 and be provided with second switch pipe T2; Between the common port of the first diode D1 and the first switching tube and seven level circuit outputs, be provided with the first inductance L 1, between the common port of second switch pipe T2 and the second diode D2 and described seven level circuit outputs, be provided with the second inductance L 2.The first electric capacity is directly connected with the tie point of the second diode with the first diode with the tie point of the second electric capacity.

Referring to Fig. 1, when multi-level circuit is applied to combining inverter described in the embodiment of the present invention, described inverter circuit comprises described multi-level circuit, and the power frequency commutation inverter circuit being in parallel with described multi-level circuit.

When described in first embodiment of the invention, multi-level circuit is applied to combining inverter, can meet when DC power output voltage can not reach requiring of inverter voltage, by boosting of DC voltage booster circuit, thereby reach the requirement of inverter voltage, realize inversion.

Between described multi-level circuit and power frequency commutation inverter circuit, can also be parallel with the 3rd capacitor C 3, further reduce THD.

Referring to Fig. 2, this figure is that multi-level circuit of the present invention is applied to combining inverter the second embodiment circuit diagram.

The difference of relative the first embodiment of second embodiment of the invention is, described DC chopper provides concrete implementation.

Described the first DC chopper comprises: the 5th inductance L B1 and the 3rd diode DB1 that between the positive bus-bar end of DC power supply and described the 4th capacitor C B1, connect; The 7th switching tube TB1 arranging between the common port of the 5th inductance L B1 and the 3rd diode DB1 and the negative busbar end of DC power supply.

Described the second DC chopper comprises: the 4th diode DB2 and the 6th inductance L B2 that between the negative busbar end of described the 5th capacitor C B2 and DC power supply, connect; The 8th switching tube TB2 arranging between the positive bus-bar end of DC power supply and the 4th diode DB2 and the common port of the 6th inductance L B2.

Referring to Fig. 2, when multi-level circuit is applied to combining inverter described in the embodiment of the present invention, described inverter circuit comprises described multi-level circuit, and the power frequency commutation inverter circuit being in parallel with described multi-level circuit.

When described in second embodiment of the invention, multi-level circuit is applied to combining inverter, can meet when DC power output voltage can not reach requiring of inverter voltage, by boosting of DC voltage booster circuit, thereby reach the requirement of inverter voltage, realize inversion.

The modulator approach of the multi-level circuit described in the embodiment of the present invention, comprising:

Control the on off state of described the first switch transistor T 1, second switch pipe T2, the 9th switch transistor T B3 and the tenth switch transistor T B4, the voltage that makes the common port of the first capacitor C 1 and the second capacitor C 2 is half of DC power output voltage V1; The output voltage V 4(of described multi-level circuit i.e. the 3rd capacitor C 3 both end voltage) be the absolute value of line voltage.

Referring to Fig. 3 a to Fig. 3 g, Fig. 3 a is the first operation mode A schematic diagram of embodiment of the present invention multi-level circuit; Fig. 3 b is the second operation mode B schematic diagram of embodiment of the present invention multi-level circuit; Fig. 3 c is the third operation mode C schematic diagram of embodiment of the present invention multi-level circuit; Fig. 3 d is the 4th kind of operation mode D schematic diagram of embodiment of the present invention multi-level circuit; Fig. 3 e is the 5th kind of operation mode E schematic diagram of embodiment of the present invention multi-level circuit; Fig. 3 f is the 5th kind of operation mode F schematic diagram of embodiment of the present invention multi-level circuit; Fig. 3 g is the 5th kind of operation mode G schematic diagram of embodiment of the present invention multi-level circuit.

The first operation mode A of embodiment of the present invention multi-level circuit: first and second switch transistor T 1, T2 conducting simultaneously; Nine, ten switch transistor T B3, TB4 turn-off.

First and second capacitor C 1, C2 discharge simultaneously, and now the 3rd capacitor C 3 voltages are DC power supply voltage V1, i.e. V4=V1.

The second operation mode B of the present invention's seven level circuits: first and second, nine, ten switch transistor T 1, T2, TB3, TB4 turn-off simultaneously; First and second inductance L 1, L2 are by first and second diode D1, D2 afterflow, and the 3rd capacitor C 3 voltages are 0, i.e. V4=0.

The third operation mode C of multi-level circuit of the present invention: the first switch transistor T 1 conducting, second, nine, ten switch transistor T 2, TB3, TB4 turn-off.The first capacitor C 1 is load supplying, and capacitor C 3 voltages are V1, i.e. V4=V1/2.

The 4th kind of operation mode state D of multi-level circuit of the present invention: the first, nine, ten switch transistor T 1, TB3, TB4 turn-off, second switch pipe T2 conducting.The second capacitor C 2 is load supplying, and the voltage V4 of the 3rd capacitor C 3 is V1, i.e. V4=V1/2.

The 5th kind of operation mode state E of multi-level circuit of the present invention: the first, ten switch transistor T 1, TB4 turn-off, second switch pipe T2, the 9th switch transistor T B3 conducting.The 4th capacitor C B1 is load supplying, and the voltage V4 of the 3rd capacitor C 3 is V2, i.e. V4=V2.

The 6th kind of operation mode state F of multi-level circuit of the present invention: second switch pipe T2 turn-offs, the first switch transistor T 1, the tenth switch transistor T B4 conducting.The 5th capacitor C B2 is load supplying, and the voltage V4 of the 3rd capacitor C 3 is V3, i.e. V4=V3.

The 7th kind of operation mode state G of multi-level circuit of the present invention:

First and second switch transistor T 1, T2 turn-offs simultaneously, the 9th, ten switch transistor T B3, TB4 conducting simultaneously.Electric capacity.Fourth, fifth capacitor C B1, CB2 be powering load simultaneously, and the voltage V4 of the 3rd capacitor C 3 is that capacitor C 4 voltage V4 are V2+V3-V1, i.e. V4=V2+V3-V1.

Referring to Fig. 4, this figure is the schematic diagram of modulator approach first embodiment of five level circuits in combining inverter described in the embodiment of the present invention.

In Fig. 4, the instantaneous value of grid-connected absolute value of voltage is u, and the instantaneous value of grid-connected current is i.Because modulating wave is according to obtaining after described line voltage sampling processing, described modulating wave waveform and described grid voltage waveform are basically identical, and difference can be ignored.Therefore in figure, adopt grid voltage waveform, can be considered to modulating wave.

The modulator approach of the multi-level circuit that the present embodiment provides, the voltage of the common port of the first capacitor C 1 and the second capacitor C 2 is that half of direct voltage V1 is V1/2;

When DC power output voltage is during higher than modulating wave peak value, described first, second DC voltage booster circuit is not worked, and controls turning on and off of first and second switch transistor T 1, T2, and described multi-level circuit is worked according to five level adjustment modes.

When multi-level circuit of the present invention is applied to photovoltaic combining inverter, judgement DC power output voltage (photovoltaic PV voltage also claims MPPT maximum power point tracking voltage (MPPT)) is during higher than the peak value of modulating wave, described DC voltage booster circuit is not worked, control turning on and off of first and second switch transistor T 1, T2, described multi-level circuit is worked according to five level adjustment modes, and the 3rd to the 6th switch transistor T 3, T4, T5, T6 play power frequency commutation effect.

Modulating wave has three zero crossings in one-period T, is designated as respectively t ₀, t ₄and t ₈; t ₄mid point for cycle T; Obtain this three zero crossing t ₀, t ₄and t ₈.

By t ₀postpone 1/4 mid point t that cycle T was the first half period ₂; By t ₀postpone 3/4 mid point t that cycle T was the second half period ₆.

The waveform of the first half period of modulating wave and the waveform of the second half period respectively straight line corresponding with V1/2 have two intersection points, are designated as respectively t ₁and t ₃, and t ₅and t ₇.

T ₀-t ₁time period, control the first switch transistor T 1 and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control second switch pipe T2 and turn-off;

T ₁-t ₂time period, control described the first switch transistor T 1 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described second switch pipe T2 conducting;

T ₂-t ₃time period, control described second switch pipe T2 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switch transistor T 1 conducting;

T ₃-t ₄time period, control described second switch pipe T2 and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described the first switch transistor T 1 and turn-off;

T ₄-t ₅time period, control described the first switch transistor T 1 and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described second switch pipe T2 and turn-off;

T ₅-t ₆time period, control described the first switch transistor T 1 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described second switch pipe T2 conducting;

T ₆-t ₇time period, control described second switch pipe T2 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switch transistor T 1 conducting;

T ₇-t ₈time period, control described second switch pipe T2 and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described the first switch transistor T 1 and turn-off.

It should be noted that, switching tube turn-on and turn-off discontinuously in the embodiment of the present invention, to be realized by drive pulse signal, for example, drive pulse signal is provided to the control end of the first switch transistor T 1, the first switch transistor T 1 conducting in the high level time section of drive pulse signal, 1 shutoff of the first switch transistor T in the low level time section of drive pulse signal.The turn-on and turn-off condition of second switch pipe T2 is similar.This drive pulse signal obtains according to Using Sinusoidal Pulse Width Modulation.

As seen from Figure 4, t ₀-t ₁time period, the third operation mode C of the second operation mode B of multi-level circuit of the present invention and multi-level circuit of the present invention switches;

T ₁-t ₂time period, the 4th kind of operation mode D of the first operation mode A of multi-level circuit of the present invention and multi-level circuit of the present invention switches;

T ₂-t ₃time period, the third operation mode C of the first operation mode A of multi-level circuit of the present invention and multi-level circuit of the present invention switches;

T ₃-t ₄time period, the 4th kind of operation mode D of the second operation mode B of multi-level circuit of the present invention and multi-level circuit of the present invention switches;

T ₄-t ₅time period, the third operation mode C of the second operation mode B of multi-level circuit of the present invention and multi-level circuit of the present invention switches;

T ₅-t ₆time period, the 4th kind of operation mode D of the first operation mode A of multi-level circuit of the present invention and multi-level circuit of the present invention switches;

T ₆-t ₇time period, the third operation mode C of the first operation mode A of multi-level circuit of the present invention and multi-level circuit of the present invention switches;

T ₇-t ₈time period, the 4th kind of operation mode D of the second operation mode B of multi-level circuit of the present invention and multi-level circuit of the present invention switches.

As can be seen from Figure 4, the operation mode switching in the first half period of modulating wave is respectively BC, AD, AC and BD.Because circuit structure in the first operation mode A and the second operation mode B is symmetrical, in the first operation mode A, the state of the first capacitor C 1, the second capacitor C 2 is identical, electric discharge simultaneously, therefore, during the first operation mode A, can think that the voltage of DC power supply is constant, the mid point electric current of the first capacitor C 1 and the second capacitor C 2 is zero, and it is constant that the voltage of the first capacitor C 1 and the second capacitor C 2 keeps, and can not be offset.

In the second operation mode B, the state of the first capacitor C 1 and the second capacitor C 2 is also identical, do not discharge simultaneously, therefore, during the second operation mode B, can think that the mid point electric current of the first capacitor C 1 and the second capacitor C 2 is zero, it is constant that the voltage of the first capacitor C 1 and the second capacitor C 2 keeps, and can not be offset.Therefore, in the first capacitor C 1 and the second capacitor C 2, voltage stabilization can not produce fluctuation.Therefore, in modulation, the voltage fluctuation in the time of can not considering the first operation mode A and the second operation mode B in the first capacitor C 1 and the second capacitor C 2.

During the third operation mode C, the first capacitor C 1 electric discharge, the second capacitor C 2 chargings.The voltage of such the first capacitor C 1 and the second capacitor C 2 is offset.

During the 4th kind of operation mode D, the first capacitor C 1 charging, the second capacitor C 2 electric discharges.Like this, the voltage of the first capacitor C 1 and the second capacitor C 2 is offset.

Voltage fluctuation when therefore, the embodiment of the present invention is mainly considered the third operation mode C and the 4th kind of operation mode D in the first capacitor C 1 and the second capacitor C 2.In the first half period of modulating wave, the operation mode that can regard switching as is: the third operation mode C, the 4th kind of operation mode D, the third operation mode C, the 4th kind of operation mode D.So just make the third operation mode C and the 4th kind of operation mode D compartment of terrain occur, thereby can effectively offset the voltage fluctuation producing in the first capacitor C 1 and the second capacitor C 2 in the third operation mode C and the 4th kind of operation mode D.In like manner, the operation mode switching in the second half period of modulating wave is also the third operation mode of mode C, the 4th kind of operation mode D, the third operation mode C, the 4th kind of operation mode D.

Particularly, in the first half period of modulating wave, t ₀-t ₁time period the third operation mode C makes the first capacitor C 1 electric discharge, voltage drop; t ₁-t ₂time period the 4th kind of operation mode D makes the first capacitor C 1 charging, and voltage rises; t ₂-t ₃time period, the third operation mode C makes the first capacitor C 1 electric discharge, voltage drop; t ₃-t ₄time period, the 4th kind of operation mode D makes the first capacitor C 1 charging, and voltage rises.

The modulator approach of multi-level circuit provided by the invention, the voltage fluctuation in the first capacitor C 1 reduces significantly.Similar due in the fluctuation voltage in the second capacitor C 2 and the first capacitor C 1, does not repeat them here.

The modulator approach of the multi-level circuit that the embodiment of the present invention provides, the first half period and the second half period at modulating wave are that the third operation mode C and the 4th kind of operation mode D appear in compartment of terrain, the voltage fluctuation producing in the first capacitor C 1 and the second capacitor C 2 in the time of can effectively offsetting like this third operation mode C and the 4th kind of operation mode D.And continuous discharge and the lasting charging interval of the first capacitor C 1, the second capacitor C 2 and the first inductance L 1, the second inductance L 2 are all shorter, greatly reduced the voltage undulation of the first capacitor C 1, the second capacitor C 2 and the first inductance L 1, the second inductance L 2, thereby the ripple that reduces output voltage, has improved output waveform.

It should be noted that, obtain modulating wave at three zero crossing t of one-period T ₀, t ₄and t ₈can there be a lot of implementations, for example, can by grid-connected phase-locked loop, find out the moment of modulating wave zero crossing, obtain this three zero crossings.

It should be noted that, described cycle T determines by mains frequency, and for example, when mains frequency is 50Hz, described cycle T is 20ms.

Referring to Fig. 5 a, this figure is the schematic diagram of modulator approach first embodiment of seven level circuits in combining inverter described in the embodiment of the present invention.

When DC power output voltage is during higher than the peak value of modulating wave, described the first DC voltage booster circuit work, control first and second, the turning on and off of nine switch transistor T 1, T2, TB3, described multi-level circuit is worked according to seven level adjustment modes;

In described DC voltage booster circuit, the voltage of the 4th capacitor C B1 is V2;

Modulating wave has three zero crossings in one-period T, is designated as respectively t ₀, t ₄and t ₈; t ₄mid point for cycle T; Obtain this three zero crossing t ₀, t ₄and t ₈;

By t ₀postpone 1/4 mid point t that cycle T was the first half period ₂; By t ₀postpone 3/4 mid point t that cycle T was the second half period ₆;

The waveform of the first half period of modulating wave and the waveform of the second half period respectively straight line corresponding with V1/2 have two intersection points, are designated as respectively t ₁and t ₃, and t ₅and t ₇;

At time point t ₁and t ₂between setup times point t _1x, at time point t ₂and t ₃between setup times point t _2x, time point t _1xwith time point t _2xwith time point t ₂centered by;

At time point t ₅and t ₆between setup times point t _5x, at time point t ₆and t ₇between setup times point t _7x, time point t _5xwith time point t _7xwith time point t ₂centered by; And t _1x-t _2xtime period equals t _5x-t _7xtime period;

T ₀-t ₁time period, the first switch transistor T 1 of control is turn-offed and conducting according to Using Sinusoidal Pulse Width Modulation, controls second switch pipe T2 and turn-offs, and the 9th switch transistor T B3 controlling in DC voltage booster circuit turn-offs;

T ₁-t _1xtime period, control described the first switch transistor T 1 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described second switch pipe T2 conducting, control the 9th switch transistor T B3 and turn-off;

T _1x-t _3xtime period, control described second switch pipe T2 conducting, control the first switch transistor T 1 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the 9th switch transistor T B3 turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _3x-t ₃time period, control described second switch pipe T2 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube conducting, control the 9th switching tube and turn-off;

T ₃-t ₄time period, control described second switch pipe T2 and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described the first switching tube and turn-off, control the 9th switching tube and turn-off;

T ₄-t ₅time period, control described the first switching tube and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described second switch pipe T2 and turn-off, control the 9th switching tube and turn-off;

T ₅-t _5xtime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described second switch pipe T2 conducting, control the 9th switching tube and turn-off;

T _5x-t _7xtime period, control described second switch pipe T2 conducting, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the 9th switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _7x-t ₇time period, control described second switch pipe T2 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube conducting, control the 9th switching tube and turn-off;

T ₇-t ₈time period, control described second switch pipe T2 and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described the first switching tube and turn-off, control the 9th switching tube and turn-off.(Fig. 5 a scheme)

Referring to Fig. 5 b, this figure is the schematic diagram of modulator approach second embodiment of seven level circuits in combining inverter described in the embodiment of the present invention.

When DC power output voltage is during higher than the peak value of modulating wave, described the second DC voltage booster circuit work, control first and second, the turning on and off of ten switch transistor T 1, T2, TB4, described multi-level circuit is worked according to seven level adjustment modes;

In described DC voltage booster circuit, the voltage of the 5th capacitor C B2 is V3;

Modulating wave has three zero crossings in one-period T, is designated as respectively t ₀, t ₄and tx; t ₄mid point for cycle T; Obtain this three zero crossing t ₀, t ₄and t ₈;

T ₀-t ₁time period, the first switching tube of control turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation, controls second switch pipe and turn-offs, and the tenth switching tube of controlling in DC voltage booster circuit turn-offs;

T ₁-t _1xtime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control the conducting of described second switch pipe, control the tenth switching tube and turn-off;

T _1x-t _3xtime period, control described the first switching tube conducting, control second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the tenth switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _3x-t ₃time period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube conducting, control the tenth switching tube and turn-off;

T ₃-t ₄time period, control described second switch pipe and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described the first switching tube and turn-off, control the tenth switching tube and turn-off;

T ₄-t ₅time period, control described the first switching tube and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described second switch pipe and turn-off, control the tenth switching tube and turn-off;

T ₅-t _5xtime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control the conducting of described second switch pipe, control the tenth switching tube and turn-off;

T _5x-t _7xtime period, control described the first switching tube conducting, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the tenth switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _7x-t ₇time period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube conducting, control the tenth switching tube and turn-off;

T ₇-t ₈time period, control described second switch pipe and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described the first switching tube and turn-off, control the tenth switching tube and turn-off.

Referring to Fig. 5 c, this figure is the schematic diagram of modulator approach the 3rd embodiment of seven level circuits in combining inverter described in the embodiment of the present invention.

When DC power output voltage is during higher than the peak value of modulating wave, described first and second DC voltage booster circuit is worked simultaneously, control first and second, the turning on and off of nine, ten switch transistor T 1, T2, TB3, TB4, described multi-level circuit is worked according to seven level adjustment modes;

In described the first DC voltage booster circuit, the voltage of the 4th capacitor C B1 is V2; In described the second DC voltage booster circuit, the voltage of the 4th capacitor C B2 is V3; And V2=V3;

T ₀-t ₁time period, the first switching tube of control turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation, controls second switch pipe and turn-offs, and the 9th, ten switching tubes of controlling in DC voltage booster circuit turn-off;

T _1x-t _3xtime period, control the conducting of described second switch pipe, control the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the 9th switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the tenth switching tube turn-offs;

T _3x-t ₃time period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube conducting, control the 9th, ten switching tubes and turn-off;

T ₃-t ₄time period, control described second switch pipe and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described the first switching tube and turn-off, control the 9th, ten switching tubes and turn-off;

T ₄-t ₅time period, control described the first switching tube and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described second switch pipe and turn-off, control the 9th, ten switching tubes and turn-off;

T ₅-t _5xtime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control the conducting of described second switch pipe, control the 9th, ten switching tubes and turn-off;

T _5x-t _7xtime period, control described the first switching tube conducting, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the tenth switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the 9th switching tube turn-offs;

T _7x-t ₇time period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube conducting, control the 9th, ten switching tubes and turn-off;

T ₇-t ₈time period, control described second switch pipe and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described the first switching tube and turn-off, control the 9th, ten switching tubes and turn-off.

Referring to Fig. 6, this figure is the schematic diagram of modulator approach the 5th embodiment of seven level circuits in combining inverter described in the embodiment of the present invention.

When DC power output voltage is during lower than the peak value of modulating wave, described the first DC voltage booster circuit work, control first and second, the turning on and off of nine switch transistor T 1, T2, TB3, described multi-level circuit is worked according to seven level adjustment modes;

The waveform of the first half period of modulating wave and the waveform of the second half period respectively straight line corresponding with V1 have two intersection points, are designated as respectively t _1yand t _3y, and t _5yand t _7y;

T ₀-t ₁time period, control the first switching tube and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, to control second switch pipe and turn-off, the 9th switching tube of controlling in DC voltage booster circuit turn-offs;

T ₁-t _1ytime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control the conducting of described second switch pipe, control the 9th switching tube and turn-off;

T _1y-t _3ytime period, control the conducting of described second switch pipe, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the 9th switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _3y-t ₃time period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube conducting, control the 9th switching tube and turn-off;

T ₃-t ₄time period, control described second switch pipe and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described the first switching tube and turn-off, control the 9th switching tube and turn-off;

T ₄-t ₅time period, control described the first switching tube and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described second switch pipe and turn-off, control the 9th switching tube and turn-off;

T ₅-t _5ytime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control the conducting of described second switch pipe, control the 9th switching tube and turn-off;

T _5y-t _7ytime period, control the conducting of described second switch pipe, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the 9th switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _7y-t ₇time period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube conducting, control the 9th switching tube and turn-off;

T ₇-t ₈time period, control described second switch pipe and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described the first switching tube and turn-off, control the 9th switching tube and turn-off.

Referring to Fig. 7, this figure is the schematic diagram of modulator approach the 6th embodiment of seven level circuits in combining inverter described in the embodiment of the present invention.

When DC power output voltage is during lower than the peak value of modulating wave Vgrid, described the second DC voltage booster circuit work, control first and second, the turning on and off of ten switch transistor T 1, T2, TB4, described multi-level circuit is worked according to seven level adjustment modes;

T ₀-t ₁time period, control the first switching tube and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, to control second switch pipe and turn-off, the tenth switching tube of controlling in DC voltage booster circuit turn-offs;

T ₁-t _1ytime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control the conducting of described second switch pipe, control the tenth switching tube and turn-off;

T _1y-t _3ytime period, control described the first switching tube conducting, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the tenth switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _3y-t ₃time period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube conducting, control the tenth switching tube and turn-off;

T ₅-t _5ytime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control the conducting of described second switch pipe, control the tenth switching tube and turn-off;

T _5y-t _7ytime period, control described the first switching tube conducting, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the tenth switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _7y-t ₇time period, control described second switch pipe and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described the first switching tube conducting, control the tenth switching tube and turn-off;

T ₇-t ₈time period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube and turn-off, control the tenth switching tube and turn-off.

Referring to Fig. 8, this figure is the schematic diagram of modulator approach the 7th embodiment of seven level circuits in combining inverter described in the embodiment of the present invention.

When DC power output voltage is during lower than the peak value of modulating wave, described first and second DC voltage booster circuit is worked simultaneously, control first and second, the turning on and off of nine, ten switch transistor T 1, T2, TB3, TB4, described multi-level circuit is worked according to seven level adjustment modes;

In described the first DC voltage booster circuit, the voltage of the 4th capacitor C B1 is V2; In described the second DC voltage booster circuit, the voltage of the 5th capacitor C B2 is V3; And V2=V3;

T ₀-t ₁time period, control the first switching tube and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, to control second switch pipe and turn-off, the 9th, ten switching tubes of controlling in DC voltage booster circuit turn-off;

T ₁-t _1ytime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control the conducting of described second switch pipe, control the 9th, ten switching tubes and turn-off;

T _1y-t _3ytime period, control the conducting of described second switch pipe, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control the 9th switching tube and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control the tenth switching tube and turn-off;

T _3y-t ₃time period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube conducting, control the 9th, ten switching tubes and turn-off;

T ₅-t _5ytime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control the conducting of described second switch pipe, control the 9th, ten switching tubes and turn-off;

T _5y-t _7ytime period, control described the first switching tube conducting, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control the tenth switching tube and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control the 9th switching tube and turn-off;

T _7y-t ₇time period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube conducting, control the 9th, ten switching tubes and turn-off;

Referring to Fig. 9 A, this figure is the schematic diagram of modulator approach first embodiment of nine level circuits in combining inverter described in the embodiment of the present invention.

When DC power output voltage is during lower than the peak value of modulating wave, described first and second DC voltage booster circuit work, control first and second, the turning on and off of nine, ten switch transistor T 1, T2, TB3, TB4, described multi-level circuit is worked according to nine level adjustment modes;

In described the first DC voltage booster circuit, the voltage of the 4th capacitor C B1 is V2; In described the second DC voltage booster circuit, the voltage of the 5th capacitor C B2 is V3;

The waveform of the first half period of modulating wave and the waveform of the second half period respectively straight line corresponding with V1 have two intersection points, and the time corresponding to two intersection points of the straight line that the waveform of the first half period of modulating wave is corresponding with V1 is designated as respectively t _1aand t _3a, the time corresponding to two intersection points of the straight line that the waveform of the second half period of modulating wave is corresponding with V1 is designated as respectively t _5aand t _7a;

The waveform of the first half period of modulating wave and the waveform of the second half period respectively straight line corresponding with V2 have two intersection points, and the time corresponding to two intersection points of the straight line that the waveform of the first half period of modulating wave is corresponding with V2 is designated as respectively t _1band t _3b, the time corresponding to two intersection points of the straight line that the waveform of the second half period of modulating wave is corresponding with V2 is designated as respectively t _5band t _7b;

T ₀-t ₁time period, control the first switching tube and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control second, nine, ten switching tubes and turn-off;

T ₁-t _1atime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control the conducting of described second switch pipe, control the 9th, ten switching tubes and turn-off;

T _1a-t _1btime period, control the conducting of second switch pipe, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the 9th switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the tenth switching tube turn-offs;

T _1b-t _3btime period, control described the first switching tube and turn-off; Control the 9th switching tube conducting; Control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the tenth switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _3b-t _3atime period, control the conducting of second switch pipe, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the 9th switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the tenth switching tube turn-offs;

T _3a-t ₃time period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube conducting, control the 9th, ten switching tubes and turn-off;

T ₃-t ₄time period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube and turn-off, control the 9th, ten switching tubes and turn-off;

T ₄-t ₅time period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described second switch pipe and turn-off, control the 9th, ten switching tubes and turn-off;

T ₅-t _5atime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control the conducting of described second switch pipe, control the 9th, ten switching tubes and turn-off;

T _5a-t _5btime period, control the conducting of second switch pipe, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the 9th switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the tenth switching tube turn-offs;

T _5b-t _7btime period, control described the first switching tube and turn-off; Control the 9th switching tube conducting; Control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the tenth switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _7b-t _7atime period, control the conducting of second switch pipe, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the 9th switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the tenth switching tube turn-offs;

T _7a-t ₇time period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube conducting, control the 9th, ten switching tubes and turn-off;

T ₇-t ₈time period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube and turn-off, control the 9th, ten switching tubes and turn-off.

Referring to Fig. 9 B, this figure is the schematic diagram of modulator approach second embodiment of nine level circuits in combining inverter described in the embodiment of the present invention.

T _1a-t _1btime period, control described the first switching tube conducting, control second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the tenth switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the 9th switching tube turn-offs;

T _1b-t _3btime period, control the tenth switching tube conducting; Control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the 9th switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling second switch pipe turn-offs;

T _3b-t _3atime period, control described the first switching tube conducting, control second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the tenth switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the 9th switching tube turn-offs;

T _5a-t _5btime period, control described the first switching tube conducting, control second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the tenth switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the 9th switching tube turn-offs;

T _5b-t _7btime period, control the tenth switching tube conducting; Control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the 9th switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; ; Controlling second switch pipe turn-offs;

T _7b-t _7atime period, control described the first switching tube conducting, control second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the tenth switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the 9th switching tube turn-offs;

Referring to Fig. 9 C, this figure is the schematic diagram of modulator approach the 3rd embodiment of nine level circuits in combining inverter described in the embodiment of the present invention.

When DC power output voltage is during lower than the peak value of modulating wave, described first and second DC voltage booster circuit is worked simultaneously, control first and second, the turning on and off of nine, ten switch transistor T 1, T2, TB3, TB4, described multi-level circuit is worked according to nine level adjustment modes;

T ₁-t _1atime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control the conducting of described second switch pipe, control the 9th, ten switching tubes and turn-off; Controlling the tenth switching tube turn-offs;

T _5b-t _7btime period, control the tenth switching tube conducting; Control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the 9th switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling second switch pipe turn-offs;

Referring to Figure 10 A, this figure is the schematic diagram of modulator approach first embodiment of 11 level circuits in combining inverter described in the embodiment of the present invention.

When DC power output voltage is during lower than the peak value of modulating wave, described first and second DC voltage booster circuit is worked simultaneously, control first and second, the turning on and off of nine, ten switch transistor T 1, T2, TB3, TB4, described multi-level circuit is worked according to 11 level adjustment modes;

In described the first DC voltage booster circuit, the voltage of the 4th capacitor C B1 is V2; In described the second DC voltage booster circuit, the voltage of the 5th capacitor C B2 is V3; And V3 > V2;

The waveform of the first half period of modulating wave and the waveform of the second half period respectively straight line corresponding with V1 have two intersection points, are designated as respectively t _1aand t _3a, and t _5aand t _7a;

The waveform of the first half period of modulating wave and the waveform of the second half period respectively straight line corresponding with V2 have two intersection points, are designated as respectively t _1band t _3b, and t _5band t _7b;

The waveform of the first half period of modulating wave and the waveform of the second half period respectively straight line corresponding with V3 have two intersection points, are designated as respectively t _1cand t _3c, and t _5cand t _7c;

T ₀-t ₁time period, control the first switch transistor T 1 and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control second, nine, ten switch transistor T 2, TB3, TB4 shutoff;

T ₁-t _1atime period, control described the first switch transistor T 1 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described second switch pipe T2 conducting, control the 9th, ten switch transistor T B3, TB4 and turn-off;

T _1a-t _1btime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control the conducting of second switch pipe; Controlling the 9th switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the tenth switching tube turn-offs;

T _1b-t _1ctime period, described second, nine switch transistor T 2, TB3 are according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control first, ten switch transistor T 1, TB4 according to Using Sinusoidal Pulse Width Modulation shutoff and conducting;

T _1c-t _3ctime period, control described second switch pipe T2 and turn-off; Control the tenth switch transistor T B4 conducting; Control described the first switch transistor T 1 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the 9th switch transistor T B3 turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _3c-t _3btime period, described second, nine switch transistor T 2, TB3 are according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control first, ten switch transistor T 1, TB4 according to Using Sinusoidal Pulse Width Modulation shutoff and conducting;

T _3b-t _3atime period, control described the first switch transistor T 1 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control second switch pipe T2 conducting; Controlling the 9th switch transistor T B3 turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _3a-t ₃time period, control described second switch pipe T2 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switch transistor T 1 conducting, control the 9th, ten switch transistor T B3, TB4 and turn-off;

T ₃-t ₄time period, control described second switch pipe T2 and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described first, nine, ten switch transistor T 1, TB3, TB4 shutoff;

T ₄-t ₅time period, control the first switch transistor T 1 and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control second, nine, ten switch transistor T 2, TB3, TB4 shutoff;

T ₅-t _5atime period, control described the first switch transistor T 1 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described second switch pipe T2 conducting, control the 9th, ten switch transistor T B3, TB4 and turn-off;

T _5a-t _5btime period, control described the first switch transistor T 1 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control second switch pipe T2 conducting; Controlling the 9th switch transistor T B3 turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the tenth switching tube turn-offs;

T _5b-t _5ctime period, described second, nine switch transistor T 2, TB3 are according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control first, ten switch transistor T 1, TB4 according to Using Sinusoidal Pulse Width Modulation shutoff and conducting;

T _5c-t _7ctime period, control described second switch pipe and turn-off; Control the tenth switch transistor T B4 conducting; Control described the first switch transistor T 1 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the 9th switch transistor T B3 turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _7c-t _7btime period, described second, nine switch transistor T 2, TB3 are according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control first, ten switch transistor T 1, TB4 according to Using Sinusoidal Pulse Width Modulation shutoff and conducting;

T _7b-t _7atime period, control described the first switch transistor T 1 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control second switch pipe T2 conducting; Controlling the 9th switch transistor T B3 turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the tenth switching tube turn-offs;

T _7a-t ₇time period, control described second switch pipe T2 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switch transistor T 1 conducting, control the 9th, ten switch transistor T B3, TB4 and turn-off;

T ₇-t ₈time period, control described second switch pipe T2 and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described first, nine, ten switch transistor T 1, TB3, TB4 shutoff.

Referring to Figure 10 B, this figure is the schematic diagram of modulator approach second embodiment of 11 level circuits in combining inverter described in the embodiment of the present invention.

In described the first DC voltage booster circuit, the voltage of the 4th capacitor C B1 is V2; In described the second DC voltage booster circuit, the voltage of the 5th capacitor C B2 is V3; And V2 > V3;

T ₀-t ₁time period, control the first switching tube and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control second, nine, ten switch transistor T 2, TB3, TB4 shutoff;

T ₁-t _1atime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control the conducting of described second switch pipe, control the 9th, ten switch transistor T B3, TB4 and turn-off;

T _1a-t _1btime period, control described second switch pipe T2 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control the first switch transistor T 1 conducting; Controlling the tenth switch transistor T B4 turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the 9th switching tube turn-offs;

T _1c-t _3ctime period, control described the first switch transistor T 1 and turn-off; Control the 9th switch transistor T B3 conducting; Control described second switch pipe T2 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the tenth switch transistor T B4 turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _3b-t _3atime period, control described second switch pipe T2 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control the first switch transistor T 1 conducting; Controlling the tenth switch transistor T B4 turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T ₄-t ₅time period, control the first switch transistor T 1 and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control second, nine, ten switch transistor T 2 and turn-off;

T ₅-t _5atime period, control described the first switch transistor T 1 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control the conducting of described second switch pipe, control the 9th, ten switch transistor T B3, TB4 and turn-off;

T _5a-t _5btime period, control described second switch pipe T2 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control the first switch transistor T 1 conducting; Controlling the tenth switch transistor T B4 turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the 9th switching tube turn-offs;

T _5c-t _7ctime period, control described the first switch transistor T 1 and turn-off; Control the 9th switch transistor T B3 conducting; Control described second switch pipe T2 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the tenth switch transistor T B4 turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _7b-t _7atime period, control described second switch pipe T2 according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control the first switch transistor T 1 conducting; Controlling the tenth switch transistor T B4 turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the 9th switching tube turn-offs;

The invention also discloses a kind of combining inverter, comprise previously described seven level circuits, and the power frequency commutation inverter circuit in parallel with described seven level circuit outlet sides.

The invention also discloses a kind of combining inverter, comprise previously described seven level circuits, the power frequency commutation inverter circuit in parallel with described seven level circuit outlet sides, and between described seven level circuits and power frequency commutation inverter circuit, be parallel with the 3rd electric capacity.

The invention also discloses a kind of method of controlling combining inverter, described combining inverter comprises previously described seven level circuits, and described seven level circuits adopt previously described any modulator approach.

The above, be only preferred embodiment of the present invention, not the present invention done to any pro forma restriction.Although the present invention discloses as above with preferred embodiment, yet not in order to limit the present invention.Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.

Claims

1. a multi-level circuit, is characterized in that, the symmetric double Buck circuit that described multi-level circuit comprises first and second DC voltage booster circuit, is in parallel with DC power supply;

2. multi-level circuit according to claim 1, is characterized in that, described the first DC chopper comprises: the 5th inductance and the 3rd diode of between the positive bus-bar end of DC power supply and described the 4th electric capacity, connecting; The 7th switching tube arranging between the common port of the 5th inductance and the 3rd diode and the negative busbar end of DC power supply;

Described the second DC chopper comprises: the 4th diode and the 6th inductance of between the negative busbar end of described the 5th electric capacity and DC power supply, connecting; The 8th switching tube arranging between the positive bus-bar end of DC power supply and the 4th diode and the common port of the 6th inductance.

3. the modulator approach of multi-level circuit according to claim 1 and 2, is characterized in that, comprising:

Control the on off state of described the first switching tube, second switch pipe, the 9th switching tube and the tenth switching tube, the voltage that makes the common port of the first electric capacity and the second electric capacity is half of DC power output voltage V1; The output voltage V 4 that makes described multi-level circuit is the absolute value of line voltage.

4. the modulator approach of multi-level circuit according to claim 3, it is characterized in that, comprise: when DC power output voltage is during higher than the peak value of modulating wave, described first, second DC voltage booster circuit is not worked, control turning on and off of first and second switching tube, described multi-level circuit is worked according to five level adjustment modes;

The waveform of the first half period of modulating wave and the waveform of the second half period respectively straight line corresponding with V1/2 have two intersection points, are designated as respectively t ₁and t ₃and t ₅and t ₇;

T ₀-t ₁time period, control the first switching tube and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control second switch pipe and turn-off;

T ₁-t ₂time period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control the conducting of described second switch pipe;

T ₂-t ₃time period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube conducting;

T ₃-t ₄time period, control described second switch pipe and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described the first switching tube and turn-off;

T ₄-t ₅time period, control described the first switching tube and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described second switch pipe and turn-off;

T ₅-t ₆time period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control the conducting of described second switch pipe;

T ₆-t ₇time period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube conducting;

T ₇-t ₈time period, control described second switch pipe and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described the first switching tube and turn-off.

5. the modulator approach of multi-level circuit according to claim 3, it is characterized in that, when DC power output voltage is during higher than the peak value of modulating wave, described the first DC voltage booster circuit work, control first and second, the turning on and off of nine switching tubes, described multi-level circuit is worked according to seven level adjustment modes;

In described DC voltage booster circuit, the voltage of the 4th electric capacity is V2;

At time point t ₅and t ₆between setup times point t _5x, at time point t ₆and t ₇between setup times point t _7x, time point t _5xwith time point t _7xwith time point t ₆centered by; And t _1x-t _2xtime period equals t _5x-t _7xtime period;

T ₀-t ₁time period, the first switching tube of control turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation, controls second switch pipe and turn-offs, and controls the 9th switching tube and turn-offs;

T ₁-t _1xtime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control the conducting of described second switch pipe, control the 9th switching tube and turn-off;

T _1x-t _3xtime period, control the conducting of described second switch pipe, control the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the 9th switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _3x-t ₃time period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube conducting, control the 9th switching tube and turn-off;

T ₅-t _5xtime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control the conducting of described second switch pipe, control the 9th switching tube and turn-off;

T _5x-t _7xtime period, control the conducting of described second switch pipe, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the 9th switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _7x-t ₇time period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube conducting, control the 9th switching tube and turn-off;

6. the modulator approach of multi-level circuit according to claim 3, it is characterized in that, when DC power output voltage is during higher than the peak value of modulating wave, described the second DC voltage booster circuit work, control first and second, the turning on and off of ten switching tubes, described multi-level circuit is worked according to seven level adjustment modes;

In described DC voltage booster circuit, the voltage of the 5th electric capacity is V3;

Modulating wave has three zero crossings in one-period T, is designated as respectively t0, t4 and t8; T4 is the mid point of cycle T; Obtain this three zero crossing t0, t4 and t8;

T ₀-t ₁time period, the first switching tube of control turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation, controls second switch pipe and turn-offs, and controls the tenth switching tube and turn-offs;

7. the modulator approach of multi-level circuit according to claim 3, it is characterized in that, when DC power output voltage is during higher than the peak value of modulating wave, described first and second DC voltage booster circuit is worked simultaneously, control first and second, the turning on and off of nine, ten switching tubes, described multi-level circuit is worked according to seven level adjustment modes;

In described the first DC voltage booster circuit, the voltage of the 4th electric capacity is V2; In described the second DC voltage booster circuit, the voltage of the 4th electric capacity is V3; And V2=V3;

T ₀-t ₁time period, the first switching tube of control turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation, controls second switch pipe and turn-offs, and controls the 9th, ten switching tubes and turn-offs;

8. the modulator approach of multi-level circuit according to claim 3, it is characterized in that, when DC power output voltage is during lower than the peak value of modulating wave, described the first DC voltage booster circuit work, control first and second, the turning on and off of nine switching tubes, described multi-level circuit is worked according to seven level adjustment modes;

T ₀-t ₁time period, control the first switching tube and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control second switch pipe and turn-off, control the 9th switching tube and turn-off;

9. the modulator approach of multi-level circuit according to claim 3, it is characterized in that, when DC power output voltage is during lower than the peak value of modulating wave, described the second DC voltage booster circuit work, control first and second, the turning on and off of ten switching tubes, described multi-level circuit is worked according to seven level adjustment modes;

T _7y-t ₇time period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off, control described the first switching tube conducting, control the tenth switching tube and turn-off;

10. the modulator approach of multi-level circuit according to claim 3, it is characterized in that, when DC power output voltage is during lower than the peak value of modulating wave, described first and second DC voltage booster circuit is worked simultaneously, control first and second, the turning on and off of nine, ten switching tubes, described multi-level circuit is worked according to seven level adjustment modes;

In described the first DC voltage booster circuit, the voltage of the 4th electric capacity is V2; In described the second DC voltage booster circuit, the voltage of the 5th electric capacity is V3; And V2=V3;

The modulator approach of 11. multi-level circuits according to claim 3, it is characterized in that, when DC power output voltage is during lower than the peak value of modulating wave, described first and second DC voltage booster circuit work, control first and second, the turning on and off of nine, ten switching tubes, described multi-level circuit is worked according to nine level adjustment modes;

In described the first DC voltage booster circuit, the voltage of the 4th electric capacity is V2; In described the second DC voltage booster circuit, the voltage of the 5th electric capacity is V3;

T ₀-t ₁time period, control the first switching tube and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control the shutoff of second switch pipe, the 9th, ten switching tubes shutoffs;

The modulator approach of 12. multi-level circuits according to claim 3, it is characterized in that, when DC power output voltage is during lower than the peak value of modulating wave, described first and second DC voltage booster circuit work, control first and second, the turning on and off of nine, ten switching tubes, described multi-level circuit is worked according to nine level adjustment modes;

The modulator approach of 13. multi-level circuits according to claim 3, it is characterized in that, when DC power output voltage is during lower than the peak value of modulating wave, described first and second DC voltage booster circuit is worked simultaneously, control first and second, the turning on and off of nine, ten switching tubes, described multi-level circuit is worked according to nine level adjustment modes;

The modulator approach of 14. multi-level circuits according to claim 3, it is characterized in that, when DC power output voltage is during lower than the peak value of modulating wave, described first and second DC voltage booster circuit is worked simultaneously, control first and second, the turning on and off of nine, ten switching tubes, described multi-level circuit is worked according to 11 level adjustment modes;

In described the first DC voltage booster circuit, the voltage of the 4th electric capacity is V2; In described the second DC voltage booster circuit, the voltage of the 5th electric capacity is V3; And V3 > V2;

T _1b-t _1ctime period, described second, nine switching tubes are according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling first, ten switching tubes turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _1c-t _3ctime period, control described second switch pipe and turn-off; Control the tenth switching tube conducting; Control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the 9th switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _3c-t _3btime period, described second, nine switching tubes are according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling first, ten switching tubes turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _3b-t _3atime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control the conducting of second switch pipe; Controlling the 9th switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T ₃-t ₄time period, control described second switch pipe and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described first, nine, ten switching tubes and turn-off;

T ₄-t ₅time period, control the first switching tube and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control second, nine, ten switching tubes and turn-off;

T _5a-t _5btime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control the conducting of second switch pipe; Controlling the 9th switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the tenth switching tube turn-offs;

T _5b-t _5ctime period, described second, nine switching tubes are according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling first, ten switching tubes turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _5c-t _7ctime period, control described second switch pipe and turn-off; Control the tenth switching tube conducting; Control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the 9th switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _7c-t _7btime period, described second, nine switching tubes are according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling first, ten switching tubes turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _7b-t _7atime period, control described the first switching tube according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control the conducting of second switch pipe; Controlling the 9th switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the tenth switching tube turn-offs;

T ₇-t ₈time period, control described second switch pipe and turn-off and conducting according to Using Sinusoidal Pulse Width Modulation, control described first, nine, ten switching tubes and turn-off.

The modulator approach of 15. multi-level circuits according to claim 3, it is characterized in that, when DC power output voltage is during lower than the peak value of modulating wave, described first and second DC voltage booster circuit is worked simultaneously, control first and second, the turning on and off of nine, ten switching tubes, described multi-level circuit is worked according to 11 level adjustment modes;

In described the first DC voltage booster circuit, the voltage of the 4th electric capacity is V2; In described the second DC voltage booster circuit, the voltage of the 5th electric capacity is V3; And V2 > V3;

T _1a-t _1btime period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control the first switching tube conducting; Controlling the tenth switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the 9th switching tube turn-offs;

T _1c-t _3ctime period, control described the first switching tube and turn-off; Control the 9th switching tube conducting; Control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the tenth switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _3b-t _3atime period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control the first switching tube conducting; Controlling the tenth switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the 9th switching tube turn-offs;

T _5a-t _5btime period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control the first switching tube conducting; Controlling the tenth switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the 9th switching tube turn-offs;

T _5c-t _7ctime period, control described the first switching tube and turn-off; Control the 9th switching tube conducting; Control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Controlling the tenth switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation;

T _7b-t _7atime period, control described second switch pipe according to Using Sinusoidal Pulse Width Modulation turn-on and turn-off; Control the first switching tube conducting; Controlling the tenth switching tube turn-offs and conducting according to Using Sinusoidal Pulse Width Modulation; Controlling the 9th switching tube turn-offs;

16. 1 kinds of combining inverters, is characterized in that, comprise the multi-level circuit described in claim 1 or 2, and the power frequency commutation inverter circuit in parallel with described multi-level circuit outlet side.

17. 1 kinds of combining inverters, it is characterized in that, comprise the multi-level circuit described in claim 1 or 2, the power frequency commutation inverter circuit in parallel with described multi-level circuit outlet side, and between described multi-level circuit and power frequency commutation inverter circuit, be parallel with the 3rd electric capacity.

18. 1 kinds of methods of controlling combining inverter, is characterized in that, described combining inverter comprises the multi-level circuit described in claim 1 or 2, and described multi-level circuit adopts the modulator approach as described in claim 3 to 15 any one.