CN102437761B - Single-phase full bridge three-level inverter and three-phase three-level inverter - Google Patents
Single-phase full bridge three-level inverter and three-phase three-level inverter Download PDFInfo
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- CN102437761B CN102437761B CN201110326567.4A CN201110326567A CN102437761B CN 102437761 B CN102437761 B CN 102437761B CN 201110326567 A CN201110326567 A CN 201110326567A CN 102437761 B CN102437761 B CN 102437761B
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Abstract
The invention discloses a single-phase full bridge three-level inverter and a three-phase three-level inverter. The three-phase three-level inverter comprises a three-phase topology unit, wherein, each phase of topology unit is a random topology unit in the following units: a first topology unit comprising four switch devices, wherein, a first switch device, a second switch device and a fourth switch device are in series connection with a direct current power supply, a second terminal of a third switch device is connected with a partial pressure middle point of the direct current power supply, and a first terminal of the third switch device is connected with a second terminal of the first switch and a first terminal of the second switch device; a second topology unit comprising four switch devices, wherein, a first switch device, a third switch device and a fourth switch device are in series connection with the direct current power supply, a first terminal of a second switch device is connected with the partial pressure middle point of the direct current power supply, a second terminal of the second switch device is connected with a second terminal of the third switch device and a first terminal of the fourth switch device. By utilizing the single-phase full bridge three-level inverter and the three-phase three-level inverter in the invention, loss can be reduced, and conversion efficiency can be raised.
Description
Technical field
The present invention relates to voltage transitions technical field, be specifically related to a kind of single-phase full bridge three-level inverter and a kind of three-phase tri-level inverter.
Background technology
Inverter refers to the effect that turns on and off by semiconductor power switch device, direct current energy is converted to a kind of converter of AC energy.In recent years, three-level inverter, owing to having the advantages such as output capacity is large, output voltage is high, current harmonic content is little, is widely used in high-power ac motor speed control by variable frequency field.
Owing to being subject to power device capacity, neutral line current, the requirement of electrical network load balance and with the restriction of the character (as three-phase AC asynchronous motor etc.) of electric loading, single-phase inverter capacity is generally lower, jumbo inverter adopts three-phase form more.
Each phase topology unit of existing three-phase tri-level inverter topology mainly contains two classes, respectively: " 1 " font topological structure and " T " font topological structure.
As shown in Figure 1, be the schematic diagram of " 1 " font topological structure in prior art.
In this " 1 " font topological structure, by connecting between direct current positive and negative busbar voltage, two equal electric capacity (being capacitor C 1 and the capacitor C 2 in Fig. 1) of capacitive reactance obtain three level: positive bus-bar level, two capacitances in series contact level, negative busbar level.Single phase half bridge inverter exchanges a binding post of output and draws from the contact n of above-mentioned two series capacitances, and another ac output end a point from figure is drawn.
The course of work of every phase topology unit is as follows:
When semiconductor switch pipe T1, T2 conducting, when semiconductor switch pipe T3, T4, diode D3, D4, D5, D6 cut-off, the level of output node a equals positive bus-bar level.When outlet side electric current flows out to inductance L 1 from a point, diode D1, D2 cut-off, current circuit is T1-T2-L1-V
g-L2-C1-T1; When outlet side electric current flows to a point from L1, diode D1, D2 conducting, current circuit is D2-D1-C1-L2-V
g-L1-D2.
When semiconductor switch pipe T2, T3 conducting, when semiconductor switch pipe T1, T4, diode D1, D2, D3, D4 cut-off, the level of output node a equals two capacitances in series contact level.When outlet side electric current flows out to L1 from a point, diode D5 conducting, diode D6 cut-off, current circuit is D5-T2-L1-V
g-L2-D5; When outlet side electric current flows to a point from L1, diode D6 conducting, diode D5 cut-off, current circuit is T3-D6-L2-V
g-L1-T3.
When semiconductor switch pipe T3, T4 conducting, when semiconductor switch pipe T1, T2, diode D1, D2, D5, D6 cut-off, the level of output node a equals negative busbar level.When outlet side electric current flows out to L1 from a point, diode D3, D4 conducting, current circuit is D4-D3-L1-V
g-L2-C2-D4; When outlet side electric current flows to a point from L1, diode D3, D4 cut-off, current circuit is T3-T4-C2-L2-V
g-L1-T3.
From the above-mentioned course of work, four groups of semiconductor switch pipes (T1 and D1 of " 1 " font three-level inverter, T2 and D2, T3 and D3, T4 and D4) maximum voltage that bears is half of the total input voltage of direct current, therefore, can select the semiconductor switch pipe that rated voltage is less and then reduce its switching loss.But in this topology, need two clamping diode D5, D6, increased device number and its loss, also increased the on-state loss of semiconductor switch pipe T2, T3 simultaneously.
As shown in Figure 2, be the schematic diagram of " T " font topological structure in prior art.
In this " T " font topological structure, by connecting between direct current positive and negative busbar voltage, two equal electric capacity (being capacitor C 1 and the capacitor C 2 in Fig. 2) of capacitive reactance obtain three level: positive bus-bar level, two capacitances in series contact level, negative busbar level, single phase half bridge inverter exchanges a binding post of output and draws from the contact n of above-mentioned two series capacitances, and another ac output end a point from figure is drawn.
The course of work of every phase topology unit is as follows:
When semiconductor switch pipe T1, T2 conducting, when semiconductor switch pipe T3, T4, D2, D3, D4 cut-off, the level of output node a equals positive bus-bar level.When outlet side electric current flows out to inductance L 1 from a point, diode D1 cut-off, current circuit is T1-L1-V
g-L2-C1-T1; When outlet side electric current flows to a point from inductance L 1, diode D1 conducting, current circuit is D1-C1-L2-V
g-L1-D1.
When semiconductor switch pipe T2, T3 conducting, when semiconductor switch pipe T1, T4, D1, D4 cut-off, the level of output node a equals two capacitances in series contact level.When outlet side electric current flows out to inductance L 1 from a point, diode D3 conducting, diode D2 cut-off, current circuit is T2-D3-L1-V
g-L2-T2; When outlet side electric current flows to a point from inductance L 1, diode D2 conducting, diode D3 cut-off, current circuit is T3-D2-L2-V
g-L1-T3.
When semiconductor switch pipe T3, T4 conducting, when semiconductor switch pipe T1, T2, D1, D2, D3 cut-off, the level of output node a equals negative busbar level.When outlet side electric current flows out to inductance L 1 from a point, diode D4 conducting, current circuit is D4-L1-V
g-L2-C2-D4; When outlet side electric current flows to a point from inductance L 1, diode D4 cut-off, current circuit is T4-C2-L2-V
g-L1-T4.
From the above-mentioned course of work, the maximum voltage that in four groups of semiconductor switch pipes of " T " font three-level inverter, T1, T4 bear is the total input voltage of direct current, and the maximum voltage that T2, T3 bear is the total input voltage of half direct current.Therefore, increase the switching loss of semiconductor switch pipe T1, T4, but without two clamping diodes, avoided this part loss.
Summary of the invention
The problem that the embodiment of the present invention exists for above-mentioned prior art, provides a kind of single-phase full bridge three-level inverter and a kind of three-phase tri-level inverter, to reduce loss, improves energy conversion efficiency.
For this reason, the embodiment of the present invention provides following technical scheme:
A single-phase full bridge three-level inverter, the converting direct-current power into alternating-current power for DC power supply is exported, comprising: two brachium pontis, described two brachium pontis are connected between described DC power supply, and each brachium pontis comprises respectively following any one topology unit:
The first topology unit, comprise: four switching devices, the first switching device wherein, second switch device and the 4th switching device are connected in series between described DC power supply, wherein, the first end of the first switching device connects the anode of described DC power supply, and the second end of the 4th switching device connects the negative terminal of described DC power supply; The second end of the 3rd switching device connects the dividing potential drop mid point of described DC power supply, and the first end of the 3rd switching device connects the second end of the first switching device and the first end of second switch device; The second end of second switch device is connected with the first end of the 4th switching device and as an output of described inverter;
The second topology unit, comprise: four switching devices, the first switching device wherein, the 3rd switching device and the 4th switching device are connected in series between described DC power supply, wherein, the first end of the first switching device connects the anode of described DC power supply, and the second end of the 4th switching device connects the negative terminal of described DC power supply; The first end of second switch device connects the dividing potential drop mid point of described DC power supply, and the second end of second switch device connects the second end of the 3rd switching device and the first end of the 4th switching device; The second end of the first switching device is connected with the first end of the 3rd switching device and as an output of described inverter.
Preferably, each switching device includes: switching tube and with the antiparallel diode of described switching tube.
Preferably, the driving signal of four switching devices in described the first topology unit or the second topology unit is handed over to cut by sinusoidal modulation wave and triangular carrier and is produced, and:
At the positive half period of described sinusoidal modulation wave, second switch break-over of device, the 4th switching device turn-offs, and if the level of described triangular carrier is less than the level of described sinusoidal modulation wave, the first switching device conducting, the 3rd switching device turn-offs; If the level of described triangular carrier is greater than the level of described sinusoidal modulation wave, the first switching device turn-offs, the 3rd switching device conducting;
Negative half-cycle at described sinusoidal modulation wave, the first switching device keeps off state, and the 3rd switching device keeps conducting state, and if the level of described triangular carrier is greater than the level of described sinusoidal modulation wave after oppositely, second switch break-over of device, the 4th switching device turn-offs; If the level of described triangular carrier is less than the level of described sinusoidal modulation wave after oppositely, second switch device turn-offs, the 4th switching device conducting.
Preferably, described single-phase full bridge three-level inverter also comprises:
Two dividing potential drop electric capacity, are connected in series between described DC power supply, for described DC power supply is carried out to dividing potential drop, and the dividing potential drop mid point that the tie point of described two dividing potential drop electric capacity is described DC power supply.
Preferably, described single-phase full bridge three-level inverter also comprises:
Filter circuit, is connected between the output of described two brachium pontis, for the high fdrequency component of inverter output signal described in filtering.
A kind of three-phase tri-level inverter, for the converting direct-current power into alternating-current power that DC power supply is exported, comprise: three-phase topology unit, each the phase topology unit in described three-phase topology unit is connected between described DC power supply, and is following any one topology unit:
The first topology unit, comprise: four switching devices, the first switching device wherein, second switch device and the 4th switching device are connected in series between described DC power supply, wherein, the first end of the first switching device connects the anode of described DC power supply, and the second end of the 4th switching device connects the negative terminal of described DC power supply; The second end of the 3rd switching device connects the dividing potential drop mid point of described DC power supply, and the first end of the 3rd switching device connects the second end of the first switching device and the first end of second switch device; The second end of second switch device is connected with the first end of the 4th switching device and as an output of described inverter;
The second topology unit, comprise: four switching devices, the first switching device wherein, the 3rd switching device and the 4th switching device are connected in series between described DC power supply, wherein, the first end of the first switching device connects the anode of described DC power supply, and the second end of the 4th switching device connects the negative terminal of described DC power supply; The first end of second switch device connects the dividing potential drop mid point of described DC power supply, and the second end of second switch device connects the second end of the 3rd switching device and the first end of the 4th switching device; The second end of the first switching device is connected with the first end of the 3rd switching device and as an output of described inverter.
Preferably, each switching device includes: switching tube and with the antiparallel diode of described switching tube.
Preferably, the driving signal of four switching devices in described the first topology unit or the second topology unit is handed over and is cut generation with triangular carrier by sinusoidal wave, and:
At the positive half period of described sinusoidal modulation wave, second switch break-over of device, the 4th switching device turn-offs, and if the level of described triangular carrier is less than the level of described sinusoidal modulation wave, the first switching device conducting, the 3rd switching device turn-offs; If the level of described triangular carrier is greater than the level of described sinusoidal modulation wave, the first switching device turn-offs, the 3rd switching device conducting;
Negative half-cycle at described sinusoidal modulation wave, the first switching device keeps off state, and the 3rd switching device keeps conducting state, and if the level of described triangular carrier is greater than the level of described sinusoidal modulation wave after oppositely, second switch break-over of device, the 4th switching device turn-offs; If the level of described triangular carrier is less than the level of described sinusoidal modulation wave after oppositely, second switch device turn-offs, the 4th switching device conducting.
Alternatively, described inverter is three-phase three-wire system three-level inverter, or three-phase four-wire system three-level inverter.
Preferably, described three-phase tri-level inverter also comprises:
Two dividing potential drop electric capacity, are connected in series between described DC power supply, for described DC power supply is carried out to dividing potential drop, and the dividing potential drop mid point that the tie point of described two dividing potential drop electric capacity is described DC power supply.
Preferably, described three-phase tri-level inverter also comprises:
Filter circuit, is connected between the output of described three-phase topology unit, for the high fdrequency component of inverter output signal described in filtering.
A kind of single-phase full bridge three-level inverter that the embodiment of the present invention provides and a kind of three-phase tri-level inverter, can be when the device count that keeps three-level inverter be minimum, reduce the voltage stress of part switching tube, thereby can select small-power semiconductor switch pipe, reduce loss, improve conversion efficiency.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present application or technical scheme of the prior art, to the accompanying drawing of required use in embodiment be briefly described below, apparently, the accompanying drawing the following describes is only some embodiment that record in the present invention, for those of ordinary skills, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is each phase " 1 " font topological structure schematic diagram of three-phase tri-level inverter topology in prior art;
Fig. 2 is each phase " T " font topological structure schematic diagram of three-phase tri-level inverter topology in prior art;
Fig. 3 is the structural representation of the first topology unit in the embodiment of the present invention;
Fig. 4 is the structural representation of the second topology unit in the embodiment of the present invention;
Fig. 5, Fig. 6, Fig. 7 are respectively a kind of structural representations of embodiment of the present invention single-phase full bridge three-level inverter;
Fig. 8, Fig. 9, Figure 10, Figure 11 are respectively a kind of structural representations of embodiment of the present invention three-phase three-wire system three-level inverter;
Figure 12, Figure 13, Figure 14, Figure 15 are respectively a kind of structural representations of embodiment of the present invention three-phase four-wire system three-level inverter;
Figure 16, Figure 17, Figure 18, Figure 19, Figure 20 are respectively the another kind of structural representations of embodiment of the present invention three-phase four-wire system three-level inverter;
Figure 21 is the driving signal schematic representation of each switching device in the embodiment of the present invention;
Figure 22 is the current circuit schematic diagram of the first topology unit under the first operation mode in the embodiment of the present invention;
Figure 23 is the current circuit schematic diagram of the first topology unit under the second operation mode in the embodiment of the present invention;
Figure 24 is the current circuit schematic diagram of the first topology unit under the 3rd operation mode in the embodiment of the present invention.
Figure 25 is the current circuit schematic diagram of the second topology unit under the first operation mode in the embodiment of the present invention;
Figure 26 is the current circuit schematic diagram of the second topology unit under the second operation mode in the embodiment of the present invention;
Figure 27 is the current circuit schematic diagram of the second topology unit under the 3rd operation mode in the embodiment of the present invention.
Embodiment
In order to make those skilled in the art person understand better the scheme of the embodiment of the present invention, below in conjunction with drawings and embodiments, the embodiment of the present invention is described in further detail.
The embodiment of the present invention provides a kind of single-phase full bridge three-level inverter and a kind of three-phase tri-level inverter, and for the converting direct-current power into alternating-current power that DC power supply is exported, described DC power supply can be that photo-voltaic power supply 0 can be also energy-storage battery.
At this single-phase full bridge three-level inverter, comprise: two brachium pontis, described two brachium pontis are connected between described DC power supply, and each brachium pontis comprises respectively following any one topology unit: the first topology unit, the second topology unit.
Equally, at this three-phase tri-level inverter, comprise: three-phase topology unit, each phase topology unit in described three-phase topology unit is connected between described DC power supply, and is following any one topology unit: the first topology unit, the second topology unit.
It should be noted that, the three-phase tri-level inverter of the embodiment of the present invention can be three-phase three-wire system three-level inverter, can be also three-phase four-wire system three-level inverter.
Owing to including above-mentioned the first topology unit and/or the second topology unit in described single-phase full bridge three-level inverter and described three-phase tri-level inverter, therefore, first these two topology unit are elaborated below.
For convenience, by above-mentioned the first topology unit, referred to as M1, the second topology unit is referred to as M2.
As shown in Figure 3, be a kind of structural representation and the corresponding simplified block diagram thereof of the first topology unit in the embodiment of the present invention.
This first topology unit comprises: four switching devices, the first switching device wherein, second switch device and the 4th switching device are connected in series between described DC power supply, wherein, the first end of the first switching device connects the anode of described DC power supply, and the second end of the 4th switching device connects the negative terminal of described DC power supply; The second end of the 3rd switching device connects the dividing potential drop mid point of described DC power supply, and the first end of the 3rd switching device connects the second end of the first switching device and the first end of second switch device; The second end of second switch device is connected with the first end of the 4th switching device and as an output of described inverter.
As shown in Figure 4, be a kind of structural representation and the corresponding simplified block diagram thereof of the second topology unit in the embodiment of the present invention.
This second topology unit comprises: four switching devices, the first switching device wherein, the 3rd switching device and the 4th switching device are connected in series between described DC power supply, wherein, the first end of the first switching device connects the anode of described DC power supply, and the second end of the 4th switching device connects the negative terminal of described DC power supply; The first end of second switch device connects the dividing potential drop mid point of described DC power supply, and the second end of second switch device connects the second end of the 3rd switching device and the first end of the 4th switching device; The second end of the first switching device is connected with the first end of the 3rd switching device and as an output of described inverter.
It should be noted that, in actual applications, the dividing potential drop mid point of above-mentioned DC power supply can be formed by two dividing potential drop electric capacity that are connected in series between described DC power supply, the dividing potential drop mid point that tie point of described two dividing potential drop electric capacity is described DC power supply.
Each switching device in above-mentioned Fig. 3 and Fig. 4 comprises: switching tube and with the antiparallel diode of described switching tube, described switching tube can be semiconductor switch pipe, such as MOSFET (high voltage metal oxide silicon field effect transistor), IGBT (igbt), IGCT (integrated gate commutated thyristor), IEGT (strengthening injection grid transistor) etc.Described diode can be the anti-paralleled diode that separate diode or described switching tube inside carry.Correspondingly, the drain electrode of described switching tube or collector electrode are connected and form the first end of described switching device with the negative electrode of described diode, and the source electrode of described switching tube or emitter are connected with the anode of described diode and form the second end of described switching device.Certainly, the embodiment of the present invention does not limit the type of above-mentioned switching tube, can also be the switching tube of other type.
As shown in Figure 3 and Figure 4, the first switching device is comprised of the first switch transistor T 1 and the first diode D1, second switch device is comprised of second switch pipe T2 and the second diode D2, the 3rd switching device is comprised of the 3rd switch transistor T 3 and the 3rd diode D3, and the 4th switching device is comprised of the 4th switch transistor T 4 and the 4th diode D4.
Based on above-mentioned the first topology unit M1 and the second topology unit M2, the single-phase full bridge three-level inverter that the embodiment of the present invention provides can have various deformation structure.
Fig. 5, Fig. 6, Fig. 7 are respectively a kind of structural representations of embodiment of the present invention single-phase full bridge three-level inverter.
As shown in Figure 5, two dividing potential drop capacitor C 1, C2 are connected in series between DC power supply, and the capacitive reactance of two dividing potential drop capacitor C 1, C2 is identical, for described DC power supply is carried out to dividing potential drop; Two brachium pontis are the first topology unit M1, and these two first topology unit are connected between described DC power supply.
In this embodiment, described single-phase full bridge three-level inverter also can further comprise: be connected to the filter circuit between the output of described two brachium pontis, for the high fdrequency component of inverter output signal described in filtering.This filter circuit can be L-type, LC type, LCL type etc.As shown in Figure 5, in this embodiment, described filter circuit comprises: respectively with output and AC load or the electrical network V of one of them brachium pontis
gconnected inductance L 1, respectively with output and AC load or the electrical network V of another brachium pontis
gconnected inductance L 2, is connected to the filter capacitor C at AC load or electrical network two ends.
Shown in Fig. 6 and Fig. 7, single-phase full bridge three-level inverter and Fig. 5 are similar, and just two brachium pontis in Fig. 6 are respectively the first topology unit M1 and the second topology unit M2, and two brachium pontis in Fig. 7 are the second topology unit M2.
Fig. 8, Fig. 9, Figure 10, Figure 11 are respectively a kind of structural representations of embodiment of the present invention three-phase three-wire system three-level inverter.
As shown in Figure 8, two dividing potential drop capacitor C 11, C12 are connected in series between DC power supply, and the capacitive reactance of two dividing potential drop capacitor C 11, C12 is identical, for DC power supply is carried out to dividing potential drop; Three-phase topology unit is the first topology unit M1, is connected between described DC power supply.
In this embodiment, described three-phase three-wire system three-level inverter also can further comprise: be connected to the filter circuit between the output of described three-phase topology unit, for the high fdrequency component of inverter output signal described in filtering.This filter circuit can be L-type, LC type, LCL type etc.As shown in Figure 8, in this embodiment, described filter circuit comprises: the one group of LC mode filter being connected with the output of every phase topology unit, as shown in Figure 8, the inductance L 1 being connected with the output of first-phase topology unit and the capacitor C 1 being connected with inductance L 1, the inductance L 2 being connected with the output of second-phase topology unit and the capacitor C 2 being connected with inductance L 2, the other end outside the inductance L 3 being connected with the output of third phase topology unit and 3, three capacitor C 1 of capacitor C, C2, the C3 that are connected with inductance L 3 are connected with inductance interconnects.
Shown in Fig. 9, Figure 10, Figure 11, three-phase three-wire system three-level inverter and Fig. 8 are similar, and just the three-phase topology unit in Fig. 9 is respectively the first topology unit M1, the first topology unit M1 and the second topology unit M2; Three-phase topology unit in Figure 10 is respectively the first topology unit M1, the second topology unit M2 and the second topology unit M2; Three-phase topology unit in Figure 11 is the second topology unit M2.
It should be noted that, the three-phase phase-sequence of each three-phase three-wire system three-level inverter output shown in above-mentioned Fig. 8 to Figure 11 can be arbitrarily, and this embodiment of the present invention is not limited.
Figure 12, Figure 13, Figure 14, Figure 15 are respectively a kind of structural representations of embodiment of the present invention three-phase four-wire system three-level inverter.
As shown in figure 12, two dividing potential drop capacitor C 11, C12 are connected in series between DC power supply, and the capacitive reactance of two dividing potential drop capacitor C 11, C12 is identical, for DC power supply is carried out to dividing potential drop; Three-phase topology unit is the first topology unit M1, is connected between described DC power supply.
In this embodiment, described three-phase four-wire system three-level inverter also can further comprise: be connected to the filter circuit between the output of described three-phase topology unit, for the high fdrequency component of inverter output signal described in filtering.This filter circuit can be L-type, LC type, LCL type etc.As shown in figure 12, in this embodiment, described filter circuit comprises: the one group of LC mode filter being connected with the output of every phase topology unit, as shown in figure 12, the inductance L 1 being connected with the output of first-phase topology unit and the capacitor C 1 being connected with inductance L 1, the inductance L 2 being connected with the output of second-phase topology unit and the capacitor C 2 being connected with inductance L 2, the inductance L 3 being connected with the output of third phase topology unit and the capacitor C 3 being connected with inductance L 3, three capacitor C 1, C2, the other end outside C3 is connected with inductance is all connected to the tie point of dividing potential drop capacitor C 11 and C22.
Shown in Figure 13, Figure 14, Figure 15, three-phase four-wire system three-level inverter and Figure 12 are similar, and just the three-phase topology unit in Figure 13 is respectively the first topology unit M1, the first topology unit M1 and the second topology unit M2; Three-phase topology unit in Figure 14 is respectively the first topology unit M1, the second topology unit M2 and the second topology unit M2; Three-phase topology unit in Figure 15 is the second topology unit M2.
It should be noted that, the three-phase phase-sequence of each three-phase four-wire system three-level inverter output shown in above-mentioned Figure 12 to Figure 15 can be arbitrarily, and this embodiment of the present invention is not limited.
In each three-phase four-wire system three-level inverter shown in above-mentioned Figure 12 to Figure 15, by the tie point of two dividing potential drop capacitor C 11, C12, draw zero line, three-phase topology unit is drawn respectively three live wires.
Figure 16, Figure 17, Figure 18, Figure 19, Figure 20 are respectively the another kind of structural representations of embodiment of the present invention three-phase four-wire system three-level inverter.
Different from each three-phase four-wire system three-level inverter shown in above-mentioned Figure 12 to Figure 15 is, in these embodiment, zero line be also by one independently topology unit (the first topology unit M1 or the second topology unit M2) provide, each three-phase four-wire system three-level inverter shown in other structure and above-mentioned Figure 12 to Figure 15 is similar, at this, is not described in detail.
It should be noted that, in each three-phase four-wire system three-level inverter shown in Figure 16 to Figure 20, in the output of four topology unit, can select that wherein any one is as zero line, the output of other other three topology unit is as live wire.
Continuation below describes the course of work of each topology unit in the embodiment of the present invention in detail in conjunction with Fig. 3 and Fig. 4.
In the embodiment of the present invention, in the first topology unit and the second topology unit, the driving signal of four switching devices is handed over and is cut generation by sinusoidal modulation wave (being modulation signal) and triangular carrier (being carrier signal), as shown in figure 21.
Wherein, Ug is sinusoidal wave, and such as 50Hz, Uc is triangular carrier, as 20KHz.S1, S2, S3 and S4 represent respectively the driving signal of the first switching device, second switch device, the 3rd switching device and the 4th switching device, V
anthe output signal that represents corresponding topology unit.
At the positive half period of described sinusoidal modulation wave Ug, second switch device and the 4th switching device drive with power frequency component, and the first switching device and the 3rd switching device drive with high-frequency pulse signal.Particularly, as shown in figure 21, second switch break-over of device, the 4th switching device turn-offs, and if the level of described triangular carrier is less than the level of described sinusoidal modulation wave, i.e. and Uc < Ug, the first switching device conducting, the 3rd switching device turn-offs; If the level of described triangular carrier is greater than the level of described sinusoidal modulation wave, i.e. Uc > Ug, the first switching device turn-offs, the 3rd switching device conducting;
At the negative half-cycle of described sinusoidal modulation wave Ug, the first switching device and the 3rd switching device drive with power frequency component, and second switch device and the 4th switching device drive with high-frequency pulse signal.Particularly, as shown in figure 21, the first switching device keeps off state, the 3rd switching device keeps conducting state, and if the level of described triangular carrier is greater than the level of described sinusoidal modulation wave after oppositely, be Uc >-Ug, second switch break-over of device, the 4th switching device turn-offs; If the level of described triangular carrier is less than the level of described sinusoidal modulation wave after oppositely, i.e. Uc <-Ug, second switch device turn-offs, the 4th switching device conducting.
It should be noted that, above-mentioned high-frequency pulse signal is pwm pulse signal, such as being pulse signal within the scope of KHz.
The first topology unit M1 in the embodiment of the present invention and the second topology unit M2 are all operated in the operation mode of three level, below this are elaborated respectively.
Figure 22, Figure 23 and Figure 24 show respectively three operation modes of the first topology unit M1, wherein:
As shown in figure 22, when the first switch transistor T 1, second switch pipe T2 conducting, when the 3rd switch transistor T 3, the 4th switch transistor T 4, the 3rd diode D3, the 4th diode D4 cut-off, the level of output node a equals positive bus-bar level.When outlet side electric current flows out to inductance L from node a, the first diode D1, the second diode D2 cut-off, current circuit is T1-T2-L-V
g-C1-T1; Outlet side electric current is during from inductance L flows into node a, the first diode D1 and the second diode D2 conducting, and current circuit is D2-D1-C1-V
g-L-D2.
As shown in figure 23, when second switch pipe T2, the 3rd switch transistor T 3 conductings, when the first switch transistor T 1, the 4th switch transistor T 4, the first diode D1, the 4th diode D4 cut-off, the level of output node a equals the level of two dividing potential drop capacitances in series contact n, i.e. V
dc/ 2, wherein, V
dclevel for DC power supply.When outlet side electric current flows out to inductance L from node a, the 3rd diode D3 conducting, the second diode D2 cut-off, current circuit is D3-T2-L-V
g-D3; Outlet side electric current is during from the first inductance L 1 flows into node a, the second diode D2 conducting, and the 3rd diode D3 cut-off, current circuit is D2-T3-V
g-L-D2.
As shown in figure 24, when the 3rd switch transistor T 3, the 4th switch transistor T 4 conductings, when the first switch transistor T 1, second switch pipe T2, the first diode D1, the second diode D2, the 3rd diode D3 cut-off, the level of output node a equals negative busbar level.When outlet side electric current flows out to inductance L from node a, the 4th diode D4 conducting, current circuit is D4-L-V
g-C2-D4; Outlet side electric current is during from inductance L flows into node a, the 4th diode D4 cut-off, and current circuit is T4-C2-V
g-L-T4.
By the above-mentioned course of work, can be found out, the first topology unit in the embodiment of the present invention, compares with existing " 1 " font topology, without two clamping diodes, has reduced the on-state loss of a switching tube; Compare with existing " T " font topology, device count is identical, and wherein the voltage stress of two groups of switching tubes reduces half, therefore can select small-power semiconductor switch pipe, reduces loss, improves conversion efficiency.
Figure 25, Figure 26 and Figure 27 show respectively three operation modes of the first topology unit M1, wherein:
As shown in figure 25, when the first switch transistor T 1, second switch pipe T2 conducting, when the 3rd switch transistor T 3, the 4th switch transistor T 4, the second diode D2, the 3rd diode D3, the 4th diode D4 cut-off, the level of output node a equals positive bus-bar level.When outlet side electric current flows out to inductance L from node a, the first diode D1 cut-off, current circuit is T1-L-V
g-C1-T1; When outlet side electric current flows to a point from inductance L, the first diode D1 conducting, current circuit is D1-C1-V
g-L-D1.
As shown in figure 26, when second switch pipe T2, the 3rd switch transistor T 3 conductings, when the first switch transistor T 1, the 4th switch transistor T 4, the first diode D1, the 4th diode D4 cut-off, the level of output node a equals the level of two dividing potential drop capacitances in series contact n, i.e. V
dc/ 2, wherein, V
dclevel for DC power supply.When outlet side electric current flows out to L from node a, the 3rd diode D3 conducting, the second diode D2 cut-off, current circuit is T2-D3-L-V
g-T2; Outlet side electric current is during from inductance L flows into node a, the second diode D2 conducting, and the 3rd diode D3 cut-off, current circuit is T3-D2-V
g-L-T3.
As shown in figure 27, when second switch pipe T2, the 3rd switch transistor T 3 conductings, when the first switch transistor T 1, the 4th switch transistor T 4, the first diode D1, the 4th diode D4 cut-off, the level of output node a equals the level of two dividing potential drop capacitances in series contact n, i.e. V
dc/ 2, wherein, V
dclevel for DC power supply.When outlet side electric current flows out to inductance L from node a, the 3rd diode D3 conducting, the second diode D2 cut-off, current circuit is T2-D3-L-V
g-T2; Outlet side electric current is during from inductance L flows into node a, the second diode D2 conducting, and the 3rd diode D3 cut-off, current circuit is T3-D2-V
g-L-T3.
By the above-mentioned course of work, can be found out, the second topology unit in the embodiment of the present invention, compares with existing " 1 " font topology, without two clamping diodes, has reduced the on-state loss of a switching tube; Compare with existing " T " font topology, device count is identical, and wherein the voltage stress of two groups of switching tubes reduces half, therefore can select small-power semiconductor switch pipe, reduces loss, improves conversion efficiency.
It should be noted that, in actual applications, in the single-phase full bridge three-level inverter shown in above-mentioned Fig. 5 to Fig. 7, in the different topology unit that two brachium pontis comprise, the driving signal phase of each corresponding switching device differs 180 degree.In three-phase four-wire system three-level inverter shown in three-phase three-wire system three-level inverter shown in Fig. 8 to Figure 11 and Figure 12 to Figure 15, mutual 120 degree of the driving signal phase of each corresponding switching device in three-phase topology unit.
In three-phase four-wire system three-level inverter shown in Figure 16 to Figure 20, driving signal phase mutual deviation 120 degree of each corresponding switching device in three topology unit corresponding to three live wires.
Above the embodiment of the present invention is described in detail, has applied embodiment herein the present invention is set forth, the explanation of above embodiment is just for helping to understand equipment of the present invention; , for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention meanwhile.
Claims (9)
1. a single-phase full bridge three-level inverter, for by the converting direct-current power into alternating-current power of DC power supply output, it is characterized in that, comprising: two brachium pontis, described two brachium pontis are connected between described DC power supply, and each brachium pontis comprises respectively following any one topology unit:
The first topology unit, comprise: four switching devices, the first switching device wherein, second switch device and the 4th switching device are connected in series between described DC power supply, wherein, the first end of the first switching device connects the anode of described DC power supply, and the second end of the 4th switching device connects the negative terminal of described DC power supply; The second end of the 3rd switching device connects the dividing potential drop mid point of described DC power supply, and the first end of the 3rd switching device connects the second end of the first switching device and the first end of second switch device; The second end of second switch device is connected with the first end of the 4th switching device and as an output of described inverter;
The second topology unit, comprise: four switching devices, the first switching device wherein, the 3rd switching device and the 4th switching device are connected in series between described DC power supply, wherein, the first end of the first switching device connects the anode of described DC power supply, and the second end of the 4th switching device connects the negative terminal of described DC power supply; The first end of second switch device connects the dividing potential drop mid point of described DC power supply, and the second end of second switch device connects the second end of the 3rd switching device and the first end of the 4th switching device; The second end of the first switching device is connected with the first end of the 3rd switching device and as an output of described inverter;
The driving signal of four switching devices in described the first topology unit or the second topology unit is handed over to cut by sinusoidal modulation wave and triangular carrier and is produced, and:
At the positive half period of described sinusoidal modulation wave, second switch break-over of device, the 4th switching device turn-offs, and if the level of described triangular carrier is less than the level of described sinusoidal modulation wave, the first switching device conducting, the 3rd switching device turn-offs; If the level of described triangular carrier is greater than the level of described sinusoidal modulation wave, the first switching device turn-offs, the 3rd switching device conducting;
Negative half-cycle at described sinusoidal modulation wave, the first switching device keeps off state, and the 3rd switching device keeps conducting state, and if the level of described triangular carrier is greater than the level of described sinusoidal modulation wave after oppositely, second switch break-over of device, the 4th switching device turn-offs; If the level of described triangular carrier is less than the level of described sinusoidal modulation wave after oppositely, second switch device turn-offs, the 4th switching device conducting.
2. single-phase full bridge three-level inverter according to claim 1, is characterized in that, each switching device includes: switching tube and with the antiparallel diode of described switching tube.
3. single-phase full bridge three-level inverter according to claim 1 and 2, is characterized in that, also comprises:
Two dividing potential drop electric capacity, are connected in series between described DC power supply, for described DC power supply is carried out to dividing potential drop, and the dividing potential drop mid point that the tie point of described two dividing potential drop electric capacity is described DC power supply.
4. single-phase full bridge three-level inverter according to claim 1 and 2, is characterized in that, also comprises:
Filter circuit, is connected between the output of described two brachium pontis, for the high fdrequency component of inverter output signal described in filtering.
5. a three-phase tri-level inverter, for the converting direct-current power into alternating-current power that DC power supply is exported, it is characterized in that, comprise: three-phase topology unit, each phase topology unit in described three-phase topology unit is connected between described DC power supply, and is following any one topology unit:
The first topology unit, comprise: four switching devices, the first switching device wherein, second switch device and the 4th switching device are connected in series between described DC power supply, wherein, the first end of the first switching device connects the anode of described DC power supply, and the second end of the 4th switching device connects the negative terminal of described DC power supply; The second end of the 3rd switching device connects the dividing potential drop mid point of described DC power supply, and the first end of the 3rd switching device connects the second end of the first switching device and the first end of second switch device; The second end of second switch device is connected with the first end of the 4th switching device and as an output of described inverter;
The second topology unit, comprise: four switching devices, the first switching device wherein, the 3rd switching device and the 4th switching device are connected in series between described DC power supply, wherein, the first end of the first switching device connects the anode of described DC power supply, and the second end of the 4th switching device connects the negative terminal of described DC power supply; The first end of second switch device connects the dividing potential drop mid point of described DC power supply, and the second end of second switch device connects the second end of the 3rd switching device and the first end of the 4th switching device; The second end of the first switching device is connected with the first end of the 3rd switching device and as an output of described inverter;
The driving signal of four switching devices in described the first topology unit or the second topology unit is handed over and is cut generation with triangular carrier by sinusoidal wave, and:
At the positive half period of described sinusoidal modulation wave, second switch break-over of device, the 4th switching device turn-offs, and if the level of described triangular carrier is less than the level of described sinusoidal modulation wave, the first switching device conducting, the 3rd switching device turn-offs; If the level of described triangular carrier is greater than the level of described sinusoidal modulation wave, the first switching device turn-offs, the 3rd switching device conducting;
Negative half-cycle at described sinusoidal modulation wave, the first switching device keeps off state, and the 3rd switching device keeps conducting state, and if the level of described triangular carrier is greater than the level of described sinusoidal modulation wave after oppositely, second switch break-over of device, the 4th switching device turn-offs; If the level of described triangular carrier is less than the level of described sinusoidal modulation wave after oppositely, second switch device turn-offs, the 4th switching device conducting.
6. three-phase tri-level inverter according to claim 5, is characterized in that, each switching device includes: switching tube and with the antiparallel diode of described switching tube.
7. according to the three-phase tri-level inverter described in claim 5 or 6, it is characterized in that, described inverter is three-phase three-wire system three-level inverter, or three-phase four-wire system three-level inverter.
8. according to the three-phase tri-level inverter described in claim 5 or 6, it is characterized in that, also comprise:
Two dividing potential drop electric capacity, are connected in series between described DC power supply, for described DC power supply is carried out to dividing potential drop, and the dividing potential drop mid point that the tie point of described two dividing potential drop electric capacity is described DC power supply.
9. according to the three-phase tri-level inverter described in claim 5 or 6, it is characterized in that, also comprise:
Filter circuit, is connected between the output of described three-phase topology unit, for the high fdrequency component of inverter output signal described in filtering.
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| CN102769405B (en) * | 2012-06-29 | 2015-04-15 | 阳光电源（上海）有限公司 | Single-phase half-bridge three-level circuit and three-level converter |
| CN102780412B (en) * | 2012-06-29 | 2015-02-18 | 阳光电源（上海）有限公司 | Single-phase half-bridge three-level circuit and inverter |
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| CN1969437A (en) * | 2004-06-18 | 2007-05-23 | Abb瑞士有限公司 | Method for error handling in a converter circuit for wiring of three voltage levels |
| JP4599959B2 (en) * | 2004-09-17 | 2010-12-15 | 富士電機ホールディングス株式会社 | Multi-level converter and control method thereof |
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| CN1969437A (en) * | 2004-06-18 | 2007-05-23 | Abb瑞士有限公司 | Method for error handling in a converter circuit for wiring of three voltage levels |
| JP4599959B2 (en) * | 2004-09-17 | 2010-12-15 | 富士電機ホールディングス株式会社 | Multi-level converter and control method thereof |
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