JP4491718B2 - 3-level converter - Google Patents

Description

  The present invention is a power conversion device that converts direct current power into alternating current power or converts alternating current power into direct current power. Specifically, the power conversion device has a ternary voltage of positive value, negative value, and zero value on the alternating current side. It relates to a level converter, ie a three-level inverter or a three-level rectifier.

FIG. 7 shows a minimum unit (hereinafter referred to as a unit) of a three-level converter using an IGBT as a controllable semiconductor switching element having an on / off function (synonymous with a self-extinguishing semiconductor switching element, hereinafter simply referred to as a controllable device). Circuit diagram).
In the figure, P is a positive electrode of a DC power source, N is a negative electrode, and a neutral point M has a potential approximately halfway between the potential of the positive electrode P and the potential of the negative electrode N. A capacitor C1 is connected between the positive electrode P and the neutral point M, and a capacitor C2 is connected between the neutral point M and the negative electrode N.

IGBTs Q1, Q2, Q3, and Q4 are sequentially connected in series between the positive electrode P and the negative electrode N, and the connection point of the IGBTs Q2 and Q3 is an AC input / output terminal AC. IGBT Q5 is connected between the connection point of IGBTs Q1 and Q2 and neutral point M, and IGBT Q6 is connected between the connection point of IGBTs Q3 and Q4 and neutral point M. Furthermore, diodes D1 to D6 are connected in reverse parallel to the IGBTs Q1 to Q6, respectively.
Hereinafter, for convenience of explanation, IGBTs Q1 and Q4 are referred to as outer switches, IGBTs Q2 and Q3 are also referred to as inner switches, IGBTs Q5 and Q6 are also referred to as clamp switches, and diodes, for example, D1 and D4 are referred to as outer diodes. We call it according to IGBT.

In explaining the prior art, since the operating principle of the inverter and the rectifier does not change, the inverter will be described below.
FIG. 8 is a configuration diagram of a single-phase three-level inverter configured using two sets of the unit converters (hereinafter also referred to as unit inverters), and FIG. 9 is a configuration diagram of 3 configured using three unit inverters. It is a block diagram of a phase 3 level inverter. A single-phase three-level inverter similar to FIG. 8 is described in FIG. 1 of Patent Document 1 described later, and a three-phase three-level inverter similar to FIG. 9 is described in FIG.

8 and 9, INV is a unit inverter having the same configuration as that in FIG. 7, Load indicates an AC load, two unit inverters INV in FIG. 8, and three unit inverters INV in FIG. A neutral point M is commonly connected between P and the negative electrode N in parallel. The AC input / output terminal AC of each unit inverter INV is connected to an AC load Load.
Since the number of phases of the inverter is not related to the operating principle, the unit three-level inverter of FIG. 7 will be described below.

When using the above-described clamp switch, in order to match the characteristics of the outer and inner diodes and the clamp diode, an IGBT module in which the IGBT and the diode are integrated is used. A common method is used to average the voltage sharing between the connected outer and inner switches.
However, in order to use the clamp switch more effectively, the following proposals have been made.

  In Patent Document 1 described later, the outer switch and the clamp switch are switched in synchronization with the output voltage command of the inverter, and the two inner switches are alternately turned on and off at a predetermined switching frequency by PWM control. Accordingly, a target output voltage can be obtained without PWM control of the outer switch and the clamp switch. Therefore, the outer switch and the clamp switch have an advantage that an inexpensive and low speed controllable device can be used.

  In Patent Document 2, the clamp switch is turned on when the inner switch is turned off. Thereby, the overvoltage generated when the inner switch is turned off is absorbed by the filter capacitor, and the voltage across the inner switch is clamped by the voltage of the filter capacitor.

  In Patent Document 3, the output limit of the three-level converter is expanded by controlling the gate signal of each controllable device so as to equalize the loss generated by each controllable device and diode.

  Further, in Patent Document 4, for example, the inductance of the commutation loop is controlled by conducting the switches corresponding to the inner switch Q3 and the clamp switch Q5 and the inner switch Q2 and the clamp switch Q6 in FIG. This reduces the overvoltage that occurs when the inner switches Q2, Q3 are turned off.

JP-A-5-211776 (paragraphs [0009] to [0011], FIGS. 1 to 3 etc.) JP-A-6-165511 (paragraphs [0008], [0009], [0014], FIG. 1 etc.) US Patent Application Publication No. 2003/0165071 (paragraphs [0012] to [0018], FIG. 4 to FIG. 6 etc.) JP 2003-88138 A (paragraphs [0038] to [0061], FIGS. 1 to 3 etc.)

  When the controllable device is turned off, a large current change occurs, and a voltage obtained by adding the transient voltage corresponding to the wiring inductance and current change rate of the commutation circuit and the voltage of the capacitor C1 or C2 in FIG. Is applied to the controllable device. If this surge voltage is excessive, the controllable device may be damaged.

FIG. 1 shows an example of a typical commutation loop in the three-level unit converter of FIG.
In FIG. 1, the solid-line loop is a path that returns to the outer switch Q1 through the outer switch Q1, the capacitor C1, and the diode D5, and this path causes current to flow from the outer switch Q1 to the diode D5 when the outer switch Q1 turns off. Acts as wiring inductance when commutating.
The dashed loop is a path that returns to the inner switch Q2 through the inner switch Q2, the clamp switch Q5, the capacitor C2, the diodes D4 and D3, and this path causes a current to flow from the inner switch Q2 to the diode when the inner switch Q2 is turned off. Acts as wiring inductance when commutating to D4 and D3.

In the broken-line loop described above, the number of devices passing therethrough is larger than that of the solid-line loop and the path itself is longer, so that the wiring inductance is increased. For this reason, the surge voltage when the inner switch Q2 is turned off becomes larger than the surge voltage when the outer switch Q1 is turned off. This relationship is the same for the other switches Q4 and Q3, and the surge voltage when the inner switch Q3 is turned off is larger than the surge voltage when the outer switch Q4 is turned off.
Hereinafter, a commutation loop such as a solid line having a small wiring inductance is referred to as a short loop, and a commutation loop such as a broken line having a large wiring inductance is referred to as a Lon group.
Here, since the commutation loop of the clamp switch is a short loop, the surge voltage when the clamp switch is turned off becomes as small as that of the outer switch.

  When designing the inverter, it is necessary to consider the largest surge voltage. If the surge voltage when the inner switch is turned off can be made equal to the surge voltage when the outer switch is turned off, the withstand voltage of the controllable device is reduced. Thus, the inverter can be miniaturized and the cost can be reduced. Or since this can reduce a surge voltage conventionally, it is possible to reduce the danger that an inverter will be damaged by a surge voltage.

  Patent Documents 2 and 4 described above are intended to reduce overvoltage when the inner switch is turned off. However, since the commutation loop proposed by Patent Document 2 is a Lon group, the effect of reducing surge voltage is small. it is conceivable that. In Patent Document 4, the commutation operation is performed twice in order to reduce the surge voltage of the inner switch. However, it takes a lot of time for commutation, and it is difficult to perform voltage control at high speed. There was a problem that the turn-off loss of the control device was large.

  Therefore, the problem to be solved by the present invention is basically to turn off the outer switch and the inner switch at the same time, and reduce the surge voltage applied to the controllable device by making the commutation loop a short loop, and at a higher speed. It is an object of the present invention to provide a three-level converter that enables voltage control and loss reduction.

In general, in a circuit in which a plurality of controllable devices are connected in series, when each controllable device connected in series is simultaneously switched, the voltage sharing of each device is due to factors such as individual characteristic differences and temperature differences of each device. Become unequal. For this reason, an excessive voltage is applied to a specific device, and the device may be damaged.
Normally, in the three-level inverter, if the outer switch and the inner switch connected in series are individually switched in an appropriate order, the voltage sharing problem at the time of series connection of both switches does not occur due to the action of the clamp diode, It has the feature that it can output ternary voltage of positive value, negative value, and zero value. On the other hand, if the outer switch and the inner switch are switched at the same time, a specific switch may be damaged due to the non-uniformity of the voltage sharing. Therefore, in a three-level inverter, a control device connected in series is conventionally used. It is said that switching should not be done at the same time.

Therefore, in the present invention, by using the action of the clamp switch, it is possible to simultaneously switch the outer switch and the inner switch without causing the problem of voltage sharing, thereby reducing the surge voltage at the time of turning off the inner switch from the conventional one. Is also reduced.
This principle will be described below.

2 and 3, the output current I _o of the unit inverters are is a positive value, in a state in which current flows from the inverter to the direction of the load, in the present invention when the output voltage changes from positive value to a zero value FIG. 2 is an explanatory diagram of the commutation principle. FIG. 2 shows a case where the output voltage is a positive value and FIG. 3 shows a case where the output voltage is a zero value.
In these drawings, a solid line indicates a portion where current flows, and a broken line indicates a portion where current does not flow. The device represented by a solid line is an IGBT that is turned on with an IGBT to which an on-gate command is given, and the device represented by a broken line is a diode that is turned off with respect to an IGBT that is given an off-gate command.

  In FIG. 2, an on-gate command is given to the outer switch Q1, the inner switch Q2, and the clamp switch Q6, and the switches Q1 and Q2 are in the on state. When the switches Q1 and Q2 are simultaneously turned off in this state, an on-gate command is given to the clamp switch Q6, so the route through which the load current flows is shown in FIG. 3 from the route via the switches Q1 and Q2 in FIG. Thus, the route changes through the capacitor C1, the clamp switch Q6, and the diode D3. At this time, the output voltage changes from a positive value to a zero value.

The commutation loop at this time is a Ron group passing through the outer switch Q1, the capacitor C1, the clamp switch Q6, and the diode D3, but the surge voltage accompanying the turn-off of the switches Q1 and Q2 is the two switches Q1 and Q2 that are turned off. Share by Q2.
This is a basic feature of the present invention, and the voltages applied individually to the switches Q1, Q2 are clearly reduced. For example, if the voltage sharing of the switches Q1 and Q2 is equal, the surge voltage is halved compared to the conventional case.

Next, it is assumed that the voltage sharing between the switches Q1 and Q2 is unbalanced, for example, one is 2/3 and the other is 1/3. Since the surge voltage in the Ron group is about 1.5 times the voltage of the capacitor C1, the surge voltage applied to one of the switches sharing the large voltage is 1 taking the product of 2/3 and 1.5. . This means that the surge voltage when the switches Q1 and Q2 are simultaneously turned off with the on-gate applied to the clamp switch Q6 is almost equal to the capacitor voltage, that is, the voltage constantly applied to one switch. It shows that it does not occur at all.
Further, since the surge voltage in the short loop is about 1.3 times the capacitor voltage, the problem of the surge voltage does not clearly occur.
Therefore, according to the present invention, if the voltage is evenly shared by the two controllable devices, the surge voltage is ½ of the conventional voltage. Since the surge voltage, which was about 5 times, can be reduced to 1 time, it becomes 2/3 of the conventional one.

  When the output voltage is changed from a negative value to a zero value, the inner switch Q3 and the outer switch Q4 are turned off at the same time with the other clamp switch Q5 being turned on. The action of reducing the surge voltage in this case is the same as that in the case where the output voltage changes from a positive value to a zero value, and the description thereof is omitted.

As described above, the present invention is characterized in that the outer switch Q1 and the inner switch Q2 or the inner switch Q3 and the outer switch Q4 are turned off at the same time. It may be difficult to achieve.
However, in the present invention, as described above, strictness is not necessarily required for the voltage sharing of each switch when the switches Q1, Q2, and Q3, Q4 are turned off (one switch shares a voltage of 2/3). Even in such a case, only a surge voltage equivalent to the capacitor voltage that is constantly applied to one switch is applied), and therefore, strict control for ensuring the turn-off simultaneity is unnecessary.

That is, the invention described in claim 1 based on the above-described commutation principle has a neutral point having a substantially intermediate potential between a positive electrode and a negative electrode of a DC power source, and between the positive electrode and the neutral point, and Capacitors are respectively connected between the neutral point and the negative electrode, and first to fourth controllable devices are sequentially connected in series between the positive electrode and the negative electrode, A connection point with the third controllable device is an AC input / output terminal, and a fifth controllable device is provided between the connection point between the first controllable device and the second controllable device and the neutral point. Is connected, a sixth controllable device is connected between the connection point between the third controllable device and the fourth controllable device and the neutral point, and the first to sixth controllable devices In a three-level converter in which diodes are connected in reverse parallel to the device ,
The first and second controllable devices are turned off almost simultaneously, and at least the sixth controllable device is given an ON command at the time of turning off,
The third and fourth controllable devices are turned off almost simultaneously, and the control pattern is such that an on command is given to at least the fifth controllable device at the time of turning off.

According to a second aspect of the present invention, in the three-level converter,
The commutation operation of the three-level converter is determined based on the first or second modulation mode command that determines the positive / negative value and zero value of the AC voltage of the three-level converter,
When changing the AC voltage of the three-level converter from a negative value to a zero value, if the first modulation mode command is given, the third and fourth controllable devices are turned off almost simultaneously, and this An ON command is given to at least the fifth controllable device at the time of OFF,
When the second modulation mode command is given to the three-level converter, the fourth and fifth controllable devices are turned off almost simultaneously, and at least the third controllable device is turned on at this time. Has a control pattern as given by.

According to a third aspect of the present invention, in the three-level converter,
The commutation operation of the three-level converter is determined based on the first or second modulation mode command that determines the positive / negative value and zero value of the AC voltage of the three-level converter,
When changing the AC voltage of the three-level converter from a positive value to a zero value, when the first modulation mode command is given, the first and second controllable devices are turned off almost simultaneously, and this An ON command is given to at least the sixth controllable device at the OFF time,
When the second modulation mode command is given to the three-level converter, the first and sixth controllable devices are turned off almost simultaneously, and at least the second controllable device is turned on at this time. Has a control pattern as given by.

The invention described in claim 4 is the invention according to claim 2 or 3,
The first modulation mode command is a dipolar modulation mode command, and the second modulation mode command is a unipolar modulation mode command.

The invention described in claim 5 is any one of claims 1 to 4,
The controllable device is configured by a series connection circuit of a plurality of unit controllable devices.

  According to a sixth aspect of the present invention, a plurality of three-level converters according to any one of the first to fifth aspects are connected as a unit converter in parallel between a positive electrode and a negative electrode of a DC power source, and each unit converter is connected. Are connected in common, and the AC input / output terminals of the unit converters are connected to an AC load or an AC power source.

According to the first aspect of the present invention, when the output voltage is changed from a positive value to a zero value, an outer switch on one side and an inner side in a state where an ON command is given to at least one clamp switch (for example, Q6 in FIG. 1). When the switch (also Q1, Q2) is turned off almost simultaneously and the output voltage is changed from a negative value to a zero value, the other side outer switch and the inner side are turned on with at least an on command given to the other clamp switch (also Q5). By turning off the switches (also Q3 and Q4) almost simultaneously, the surge voltage generated when the controllable device is turned off can be reduced to prevent the controllable device from being damaged by overvoltage.
Thereby, the withstand voltage of the controllable device can be reduced, and a low-cost and small three-level inverter or three-level rectifier can be realized.
According to the invention described in claims 2 to 4, when the output voltage commutates from a positive value or a negative value to a zero value in accordance with the modulation mode command, by selecting and switching the controllable device of the commutation destination In the unipolar modulation, all the commutation occurs in a short loop, and coupled with the invention described in claim 1, the surge voltage generated when the controllable device is turned off can be reduced regardless of the modulation mode.
In the present invention, the surge voltage can be reduced by one commutation, and the voltage control can be speeded up to reduce the turn-off loss.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a first embodiment of the present invention corresponding to claim 1 will be described with reference to FIG. FIG 4 is a target unit converter 7, and the output voltage command V _o, is an explanatory view of a control pattern showing a gate signal G1~G6 each controllable device Q1 to Q6.
The output voltage command V _o, "1" when the output voltage is positive value, "0" if the zero value, Yes expressed by "-1" in the case of a negative value, as shown, positive → Zero → Negative → Zero and then return to positive value again. As for the gate signals G1 to G6, an on-gate command is given when the level is high, and an off-gate command is given when the level is low.

Period in FIG. 4 (1), the outer switch Q1, the on-gate command is given to the inner switch Q2 and the clamp switch Q6, the output voltage command _{V o} is "1" (positive value). When the output voltage command V _o changes from “1” to “0”, an off-gate command is simultaneously applied to the switches Q1 and Q2.
When the output current is a positive value, commutation from the switches Q1 and Q2 to the switch Q6 and the diode D3 occurs, and the output voltage changes from a positive value to a zero value. As described above, the surge voltage applied to the switches Q1 and Q2 can be reduced by simultaneously turning off the switches Q1 and Q2 while the clamp switch Q6 is turned on.

In the period (2), after a predetermined delay time Td has elapsed, an on-gate command is given to the inner switch Q3. When the output current is a negative value, commutation from the diodes D1 and D2 to the switch Q3 and the diode D6 occurs at this time, and the output voltage changes from a positive value to a zero value.
Then, at the time of changing to "-1" from the output voltage command _{V o} "0", the off-gate command is given to the clamp switch Q6. When the output current is a positive value, commutation from the switch Q6 to the diode D4 is performed, and the output voltage changes from a zero value to a negative value. At this time, since the commutation loop from the switch Q6 to the diode D4 is a short loop, the surge voltage is small.

In the period (3), after a predetermined delay time Td has elapsed, an on-gate command is given to the outer switch Q4 and the clamp switch Q5. When the output current is a negative value, commutation from the diode D6 to the switch Q4 occurs, and at this time, the output voltage changes from a zero value to a negative value.
When the output voltage command V _o changes from “−1” to “0”, an off-gate command is simultaneously applied to the inner switch Q3 and the outer switch Q4. When the output current is a negative value, commutation from the switches Q3 and Q4 to the diode D2 and the switch Q5 is performed, and the output voltage changes from a negative value to a zero value. Thus, by simultaneously turning off the switches Q3 and Q4 with the clamp switch Q5 turned on, the surge voltage applied to the switches Q3 and Q4 can be reduced as described above.

In period (4), after a predetermined delay time Td has elapsed, an on-gate command is given to the inner switch Q2. When the output current is a positive value, commutation from the diodes D4 and D3 to the diode D5 and the switch Q2 is performed, and at this time, the output voltage changes from a negative value to a zero value.
When the changes to "1" from the output voltage command V _o is "0", the off-gate command is given to the clamp switch Q5. When the output current is a negative value, commutation from the switch Q5 to the diode D1 is performed, and the output voltage changes from a zero value to a positive value. At this time, since the commutation loop from the switch Q5 to the diode D1 is a short loop, the surge voltage is small.

In the period (5), after a predetermined delay time Td has elapsed, an on-gate command is given to the outer switch Q1 and the clamp switch Q6. When the output current is a positive value, commutation from the diode D5 to the switch Q1 occurs at this point, and the output voltage changes from a zero value to a positive value.
As described above, by controlling the gate with the pattern shown in FIG. 4, the surge voltage at the turn-off time of the controllable device can be reduced at any commutation.

Next, a second embodiment of the present invention corresponding to claims 2 and 4 will be described with reference to FIG.
As in the first embodiment, PWM control that outputs a positive value and a negative value before and after the zero value of the output voltage is called dipolar modulation. This modulation method has an advantage that the average value of the output voltage can be controlled to zero or a very small value, but has a disadvantage that a large output voltage cannot be obtained. It is known that this drawback can be solved by unipolar modulation. In unipolar modulation, the output voltage can be output by repeating positive, zero, and positive values, or repeating negative, zero, and negative values. The average value can be increased.
Note that a modulation method in which dipolar modulation and unipolar modulation are mixed in the output half cycle of the inverter is generally called partial dipolar modulation. However, since it is partially dipolar modulation or unipolar modulation, both modulations are mixed. Even in some cases, this is called dipolar modulation or unipolar modulation.

In FIG. 5, “Mode” is a modulation mode command corresponding to a dipolar modulation mode command when it is at a low level, and a unipolar modulation mode command when it is at a high level. Note that the period (1) to the period (3), because the state of the output voltage command V _o and the gate signal G1~G6 is the same and 4 both, the description thereof is omitted.

During the period (3), “Mode” is switched from low level to high level, and a command to switch from dipolar modulation to unipolar modulation is issued. The following control is performed in response to this modulation mode command.
When the output voltage command V _o changes from “−1” to “0”, an off-gate command is simultaneously applied to the outer switch Q4 and the clamp switch Q5. When the output current is a negative value, commutation from the switch Q4 to the diode D6 occurs, and the output voltage changes from a negative value to a zero value. The commutation loop in this case is a short loop.

In the period (4), an on-gate command is given to the clamp switch Q6 after a predetermined delay time Td has elapsed. When the output current is a positive value, commutation from the diode D4 to the switch Q6 is performed, and at this time, the output voltage changes from a negative value to a zero value. When the changes to "-1" from the output voltage command _{V o} is "0", the off-gate command is given to switch Q6. When the output current is a positive value, commutation from the switch Q6 to the diode D4 occurs, and the output voltage changes from a zero value to a negative value. The commutation loop in this case is a short loop.

In the period (5), after a predetermined delay time Td has elapsed, an on-gate command is given simultaneously to the outer switch Q4 and the clamp switch Q5. When the output current is a negative value, commutation from the diode D6 to the switch Q4 is performed, and at this time, the output voltage changes from a zero value to a negative value.
As described above, by controlling the gate with the pattern shown in FIG. 5, all the commutation loops during unipolar modulation become short loops, and the surge voltage when the controllable device is turned off becomes small.

Next, a third embodiment of the present invention corresponding to claims 3 and 4 will be described with reference to FIG.
This embodiment is an example when the output voltage of the inverter repeats a positive value and a zero value when unipolar modulation is selected. In FIG. 6, the period from the middle of the period (3) to the period (5) is the same as the periods (3) to (5) in FIG. 4 and will not be described. In the following, the period (5) in FIG. A description will be given after the end point of.

In FIG. 6, during the period (5), “Mode” is switched from the low level to the high level, and a switching command from the dipolar modulation to the unipolar modulation is issued. The following control is performed in response to this modulation mode command.
That is, when the output voltage command V _o changes from “1” to “0”, an off-gate command is simultaneously applied to the outer switch Q1 and the clamp switch Q6. When the output current is a positive value, commutation from the switch Q1 to the diode D5 occurs, and the output voltage changes from a positive value to a zero value. The commutation loop in this case is a short loop.

In the period (6), an on-gate command is given to the clamp switch Q5 after a predetermined delay time Td has elapsed. When the output current is a negative value, commutation from the diode D1 to the switch Q5 is performed, and at this time, the output voltage changes from a positive value to a zero value. Output voltage command V _o off-gate command is given to the switch Q5 when the change from "0" to "1". When the output current is a negative value, commutation from the switch Q5 to the diode D1 occurs, and the output voltage changes from a zero value to a positive value. The commutation loop in this case is a short loop.

In the period (7), after a predetermined delay time Td has elapsed, an on-gate command is given simultaneously to the outer switch Q1 and the clamp switch Q6. When the output current is a positive value, commutation from the diode D5 to the switch Q1 is performed, and at this time, the output voltage changes from a zero value to a positive value.
As described above, by controlling the gate with the pattern shown in FIG. 6, the commutation loop at the time of unipolar modulation becomes a short loop as in the case of FIG. 5, and the surge voltage at the turn-off time of the controllable device is Get smaller.

Each of the above embodiments is an example in which the controllable devices Q1 to Q6 and the diodes D1 to D6 are each configured by a single device, but when these devices are each configured by a series connection circuit of a plurality of devices. The same effect can be obtained.
That is, as in the fourth embodiment of FIG. 10 corresponding to claim 5, each of the controllable devices Q1 to Q6 is constituted by a series circuit of two IGBTs (for convenience, these IGBTs are referred to as unit controllable devices). The diodes D1 to D6 may each be constituted by a series circuit of two diodes.
In addition, as described in claim 6, a plurality of the three-level converters of the above-described embodiments as unit converters are connected in parallel between the positive electrode P and the negative electrode N of the DC power supply, and the neutral point of each unit converter A single-phase three-level converter in FIG. 8 and a three-phase three-level converter in FIG. 9 can be configured by connecting M in common and connecting the AC input / output terminal AC of each unit converter to an AC load Load.

  As the controllable device, a controllable device such as a power transistor or MOSFET may be used in addition to the IGBT.

It is a figure which shows the typical commutation loop in a 3 level unit converter. It is explanatory drawing of the commutation principle in this invention. It is explanatory drawing of the commutation principle in this invention. It is explanatory drawing of the control pattern concerning 1st Embodiment of this invention. It is explanatory drawing of the control pattern concerning 2nd Embodiment of this invention. It is explanatory drawing of the control pattern concerning 3rd Embodiment of this invention. It is a circuit diagram of a 3 level unit converter used for the present invention. It is a circuit diagram of the single phase 3 level inverter used for this invention. It is a circuit diagram of a three-phase three-level inverter used in the present invention. It is a circuit diagram which shows 4th Embodiment of this invention.

Explanation of symbols

Q1-Q6: Controllable device (IGBT)
D1 to D6: Diodes C1, C2: Capacitors P: Positive electrode N: Negative electrode M: Neutral point AC: AC input / output terminal INV: Unit inverter
Load: AC load

Claims (6)

A neutral point having a substantially intermediate potential between a positive electrode and a negative electrode of a DC power source, and a capacitor is connected between the positive electrode and the neutral point, and between the neutral point and the negative electrode, The first to fourth controllable devices are sequentially connected in series between the positive electrode and the negative electrode, and the connection point between the second controllable device and the third controllable device is the AC input / output terminal, A fifth controllable device is connected between a connection point between the first controllable device and the second controllable device and the neutral point, and the third controllable device and the fourth controllable device In a three-level converter in which a sixth controllable device is connected between the connection point of the first and the neutral point, and a diode is connected in antiparallel to each of the first to sixth controllable devices,
The first and second controllable devices are turned off almost simultaneously, and at least the sixth controllable device is given an ON command at the time of turning off,
A three-level converter characterized by having a control pattern in which the third and fourth controllable devices are turned off almost simultaneously and an on command is given to at least the fifth controllable device at the time of turning off. . A neutral point having a substantially intermediate potential between a positive electrode and a negative electrode of a DC power source, and a capacitor is connected between the positive electrode and the neutral point, and between the neutral point and the negative electrode, The first to fourth controllable devices are sequentially connected in series between the positive electrode and the negative electrode, and the connection point between the second controllable device and the third controllable device is the AC input / output terminal, A fifth controllable device is connected between a connection point between the first controllable device and the second controllable device and the neutral point, and the third controllable device and the fourth controllable device In a three-level converter in which a sixth controllable device is connected between the connection point of the first and the neutral point, and a diode is connected in antiparallel to each of the first to sixth controllable devices,
The commutation operation of the three-level converter is determined based on the first or second modulation mode command that determines the positive / negative value and zero value of the AC voltage of the three-level converter,
When changing the AC voltage of the three-level converter from a negative value to a zero value, if the first modulation mode command is given, the third and fourth controllable devices are turned off almost simultaneously, and this An ON command is given to at least the fifth controllable device at the time of OFF,
When the second modulation mode command is given to the three-level converter, the fourth and fifth controllable devices are turned off almost simultaneously, and at least the third controllable device is turned on at this time. 3 level converter characterized by having a control pattern as given by A neutral point having a substantially intermediate potential between a positive electrode and a negative electrode of a DC power source, and a capacitor is connected between the positive electrode and the neutral point, and between the neutral point and the negative electrode, The first to fourth controllable devices are sequentially connected in series between the positive electrode and the negative electrode, and the connection point between the second controllable device and the third controllable device is the AC input / output terminal, A fifth controllable device is connected between a connection point between the first controllable device and the second controllable device and the neutral point, and the third controllable device and the fourth controllable device In a three-level converter in which a sixth controllable device is connected between the connection point of the first and the neutral point, and a diode is connected in antiparallel to each of the first to sixth controllable devices,
The commutation operation of the three-level converter is determined based on the first or second modulation mode command that determines the positive / negative value and zero value of the AC voltage of the three-level converter,
When changing the AC voltage of the three-level converter from a positive value to a zero value, when the first modulation mode command is given, the first and second controllable devices are turned off almost simultaneously, and this An ON command is given to at least the sixth controllable device at the OFF time,
When the second modulation mode command is given to the three-level converter, the first and sixth controllable devices are turned off almost simultaneously, and at least the second controllable device is turned on at this time. 3 level converter characterized by having a control pattern as given by The three-level converter according to claim 2 or 3,
The three-level converter characterized in that the first modulation mode command is a dipolar modulation mode command and the second modulation mode command is a unipolar modulation mode command. In the 3 level converter as described in any one of Claims 1-4,
A three-level converter, wherein the controllable device is configured by a series connection circuit of a plurality of unit controllable devices. A plurality of three-level converters according to any one of claims 1 to 5 as unit converters are connected in parallel between a positive electrode and a negative electrode of a DC power source, and the neutral points of the unit converters are commonly connected. In addition, the AC input / output terminal of each unit converter is connected to an AC load or an AC power supply.

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