TWI666863B - High boost DC converter - Google Patents

Abstract

A high-boost DC converter includes a first winding, a main switch, an auxiliary switch, a clamp capacitor, a voltage lifting unit, a voltage superimposing unit, an output diode, and an output capacitor. The main switch and the auxiliary switch are respectively controlled to switch between a conducting state and a non-conducting state, and the auxiliary switch and the clamping capacitor form an active clamping circuit, so that the main switch and the auxiliary switch reach a zero voltage switching softness. Cutting performance, the voltage lifting unit charges the output capacitor when the output diode is turned on to generate a capacitor voltage proportional to a lift voltage, the voltage superimposing unit is performed by an induced voltage from the first winding Boost to generate a superimposed voltage on the output side to increase the output voltage to achieve a high boost ratio.

Description

High boost DC converter

The present invention relates to a DC converter, and more particularly to a high boost DC converter.

Referring to FIG. 1, a conventional boost converter, if the influence of parasitic resistance is not considered, the voltage gain is related to an output voltage V _O , an input voltage V _in , and a switch-on ratio D, wherein The conduction ratio D is a real number greater than 0 and less than 1.

It can be seen that the traditional boost converter must operate at a very high switching turn-on ratio in order to obtain a high boost ratio. However, a very high turn-on ratio will generate large current ripple and severe diode inversion. The recovery current problem causes the converter to generate power loss. In addition, the switch of the conventional boost converter is hard switching. Furthermore, the voltage of the switch and the diode of the conventional boost converter is The high voltage output voltage has a large on-resistance, resulting in a problem of higher power loss.

Accordingly, it is an object of the present invention to provide a high boost DC converter that achieves high voltage gain without requiring a very high turn-on ratio.

Therefore, the high-boost DC converter of the present invention comprises: a first winding, a main switch, an auxiliary switch, a clamp capacitor, a voltage boosting unit, an output diode, an output capacitor, and a voltage superposition unit.

The first winding has a first end electrically connected to an anode of an input voltage and a second end electrically connected to a first common contact, the main switch having a first end electrically connected to the first common contact and a grounded second end, and the main switch is controlled to switch between a conducting state and a non-conducting state. The auxiliary switch has a first end and a second end electrically connected to the first common contact, and the auxiliary switch is controlled to switch between an on state and a non-conduction state.

The clamp capacitor has a first end electrically connected to the first end of the auxiliary switch, and a second end electrically connected to the anode of the input voltage. The voltage lifting unit has a lifting input electrically connected to the first common contact, and a lifting output for boosting an induced voltage from the first winding to generate a lifting voltage from the Lift the output output.

The voltage lifting unit includes a first lifting capacitor, a second lifting capacitor, a second winding, a first lifting diode, and a second lifting diode. The first lifting capacitor has a first end and a second end electrically connected to the lifting input end, and the second winding has a first end and a second end electrically connected to the second end of the first lifting capacitor The second lift capacitor has a first end electrically connected to the second end of the second winding, and a second end electrically connected to the lift output end, the first lift diode having an electrical connection An anode of the first end of the two windings, and a cathode electrically connected to the lift output, the second lift diode has an anode electrically connected to the lift input terminal, and a second electrically connected to the second winding The cathode of the end.

The output diode has an anode electrically connected to the lift output and a cathode electrically connected to a second common contact. The output capacitor has a first end electrically connected to the second common contact, and a grounded second end. When the output diode is turned on, receiving charging from the lift voltage generates a proportional increase The voltage of the capacitor. The voltage superimposing unit is electrically connected to the second common contact to be connected in series to the output capacitor, and is configured to boost the induced voltage from the first winding to generate a superimposed voltage, and the superimposed voltage and the capacitor voltage are added. In total, an output voltage is generated.

The voltage superimposing unit includes a first superimposing diode, a second superimposing diode, a third winding, a first superimposing capacitor, and a second superposing capacitor. The first superimposed diode has an anode electrically connected to the second common contact and a cathode, and the third winding has a first end and a second end electrically connected to the cathode of the first superimposed diode. The first superposed capacitor has a first end electrically connected to the second end of the third winding, and a second end electrically connected to the second common contact, the second superposed diode having an electrical connection Superposing an anode of the cathode of the diode and a cathode, the second superposed capacitor has a first end electrically connected to the cathode of the second superimposed diode, and a first end electrically connected to the first end of the first superposed capacitor Two ends.

The effect of the present invention is that the voltage lifting unit and the voltage superimposing unit effectively increase the overall boost ratio without requiring the switching operation to be at a high conduction ratio.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.

Referring to FIG. 2, an embodiment of the high-boost DC converter of the present invention includes a first winding N ₁ , a main switch S ₁ , an auxiliary switch S ₂ , a clamp capacitor C _c , and a voltage of a coupled inductor. The lifting unit 2, an output diode D ₀ , an output capacitor C ₀ , a voltage superimposing unit 3 , and a control unit 4 .

The first winding N ₁ has a first end and a second end of a dot, the main switch S ₁ has a first end electrically connected to a first common contact and a second end connected to the ground, and the control unit 4 controlling the main switch to switch between an on state and a non-conduction state through a first pulse modulation signal. When the main switch S _{1 is} in the conducting state, the first winding N ₁ receives a charging current i _In from an input voltage V _in , so that the first winding N ₁ generates a proportional magnetization inductance L _{m .} A first induced voltage V _Lm of a size. The main switch S ₁ is an N-type power semiconductor transistor, and a first terminal of the primary switch S ₁ is a drain, the second terminal of the primary switch S ₁ is a source.

The auxiliary switch S ₂ has a first end electrically connected to the first end of the clamping capacitor C _c , and a second end electrically connected to the first common contact, and the control unit 4 transmits a second pulse signal controlling the auxiliary switch S ₂ between a conducting state and a nonconductive state switching, when the main switch S ₁ is in the non-conducting state and the auxiliary switch S ₂ in the conductive state. The auxiliary switch S ₂ is an N-type power semiconductor transistor, and the first auxiliary switch S ₂ is a drain terminal, the second terminal of the auxiliary switch S ₂ is a source.

The clamping capacitor C _c having a terminal electrically connected to the second input voltage V _in the anode.

The voltage lifting unit 2 has a lifting input terminal and a lifting output terminal, and the voltage lifting unit 2 includes a first lifting capacitor C ₃ , a second winding N _{2 of} the coupled inductor, and a second lifting The capacitor C ₄ , a first lift diode D ₃ , and a second lift diode D ₄ . The capacitor C ₃ having a first lifting a first electrical terminal, and a common contact electrically connected to the first (the lift input terminal) is connected to a second terminal of the second winding N ₂ of the first end. The second winding N ₂ has a first end electrically connected to the second end of the first lifting capacitor C ₃ and a second end electrically connected to the first end of the second lifting capacitor C ₄ . The second lifting capacitor C ₄ has a first end electrically connected to the second end of the second winding N ₂ and a second end electrically connected to the anode of the output diode D ₀ (the lifting output end) . The first lift diode D ₃ has an anode electrically connected to the first end of the second winding N ₂ and a cathode electrically connected to the anode of the output diode D ₀ . The second lift diode D ₄ has an anode electrically connected to the first common contact and a cathode electrically connected to the second end of the second winding N ₂ .

The voltage superimposing unit 3 includes a first superimposing diode D ₁ , a third winding N _{3 of} the coupled inductor, a first superimposing capacitor C ₁ , a second superimposing diode D ₂ , and a second superposition Capacitor C ₂ . The first superimposed diode D ₁ has an anode electrically connected to a second common contact and a cathode electrically connected to the first end of the third winding N ₃ . The third winding N ₃ has a first end electrically connected to the cathode of the first superimposed diode D ₁ and a second end electrically connected to the first end of the first superposed capacitor C ₁ . The first superposing capacitor C ₁ has a first end electrically connected to the second end of the third winding N ₃ and a second end electrically connected to the second common contact. The second superposed diode D ₂ has a cathode electrically connected to the anode of the first superimposed diode D ₁ and a cathode electrically connected to the first end of the second superposed capacitor C ₂ . The second superposing capacitor C ₂ has a first end electrically connected to the cathode of the second superimposing diode D ₂ and a second end electrically connected to the first end of the first superposing capacitor C ₁ .

The control unit 4 of the main switch S generates a first pulse of _a modulation signal and a second pulse modulation signal to a switching of the auxiliary switch S ₂ is switched, the following will further illustrate eleven stages of the main switch S ₁ and the auxiliary switch S ₂ switch to generate a timing diagram of one of the high boost DC converters of the present invention.

Referring to FIG. 3, an equivalent circuit diagram of the present embodiment is used to illustrate the magnetizing inductance L _m , a leakage inductance L _k , and the parasitic capacitance C of a main switch in the non-ideal equivalent circuit of the first winding N ₁ . _r , wherein the voltage and the voltage across the components are: the input voltage V _in , the voltage across a first winding V _N1 , the voltage across a second winding V _N2 , the voltage across a third winding V _N3 , an output voltage V _o, a voltage across the parasitic capacitance V _Cr, a clamp capacitor voltage across V _Cc, a second superimposed voltage V ₂ across the capacitor C of _C2, a first superimposed voltage across capacitor V _C1, a The cross-voltage V _{C0 of the} output capacitor, the cross-voltage V _C3 of the first lift capacitor, the cross-voltage V _{C4 of the} second lift capacitor, the cross-voltage V _{D3 of the} first lift diode, and the second lift The voltage across the voltage of the rising diode V _D4 , the voltage across the second superimposed diode V _D2 , the voltage across the first superimposed diode V _D1 , the voltage across the output diode V _D0 , and a magnetization The voltage across the inductor is V _Lm . The currents when the components are turned on are: an input current i _In , a conduction current i _{S1 of} a main switch, an on-current i _{S2 of} an auxiliary switch, a conduction current i _{D3 of} a first lift diode, and a second The conduction current i _{D4 of the} lift diode, the conduction current i _D2 of a second superimposed diode, the conduction current i _{D1 of} a first superimposed diode, the conduction current i _{D0 of} an output diode, and a magnetization The current i _{Lm of the} inductor and the current i _{Lk of} a leakage inductor.

The following is a circuit diagram of the eleventh stage of the present embodiment, in which the conductive elements are indicated by solid lines, the non-conducting elements are indicated by broken lines, and the following analysis is based on five assumptions:

Hypothesis 1: The conduction voltage drop of all power switches and diodes is zero.

Hypothesis 2: the second superimposing capacitor C ₂ , the first superposing capacitor C ₁ , and the output capacitor C ₀ are large enough to ignore the capacitor voltage chopping, the crossover voltage V _{C2 of} the second superposing capacitor C ₂ , the first The voltage across the voltage V _{C 1 of the} superimposed capacitor C _{1 and} the voltage across the output capacitor C ₀ V _{C 0} can be regarded as constant.

Three assumptions: There is a number of turns of the first winding n _1, a second number of turns of winding turns n _2, and a third winding n _3. Then, the turns ratio N _{12 of the} first winding and the second winding is equal to a turns ratio N _{13 of the} first winding and the third winding is equal to a coupled inductor turns ratio n, where n is a real number greater than or equal to 1 (in other words , And the magnetizing inductance L _{m is} much larger than the leakage inductance L _k , that is, a coupling coefficient .

Hypothesis 4: The magnetizing inductor current i _{Lm of} the coupled inductor operates in a continuous conduction mode (CCM).

Hypothesis 5: The main switch S ₁ and the auxiliary switch S ₂ are complementary driving, and there is a very short dead time between the two, since the blind time is extremely short, if the main switch S ₁ has a conduction ratio D, the conduction ratio of the auxiliary switch can be regarded as 1 minus the conduction ratio D (in other words, 1-D).

Based on the above five assumptions, each phase is described in the following content, wherein the time t corresponds to the start time of each phase is a first start time t0 to an eleventh start time t10, respectively. The time t reaches an eleventh end time t11, and the entire converter completes eleven stages of a cycle.

The first stage [t: t0~t1]:

Referring to FIG. 4 and FIG. 5, the main switch S ₁ will be turned from non-conducting to non-conducting, and the auxiliary switch S ₂ is non-conducting. The first lifting diode D ₃ and the second lifting diode D _{4 are} The second superimposed diode D ₂ is turned on, and the first superimposed diode D ₁ and the output diode D ₀ are both non-conductive.

The time t at the beginning of this phase is equal to the sixth start time t0, the main switch S _{1 is} turned on, and the auxiliary switch S ₂ is non-conductive. The input voltage V _{in is} across the magnetizing inductance L _m and the leakage inductance L _k , and the current i _{Lm of} the magnetizing inductance and the current i _Lk of the leakage inductance rise linearly. The first lifting capacitor C ₃ and the second lifting by the second winding N _{2 of} the coupled inductor, the first lifting diode D ₃ , and the second lifting diode D ₄ Capacitor C _{4 is} in a charged state. The current of the coupled inductor third winding N ₃ charges the second superposed capacitor C ₂ by switching the second superimposed diode D ₂ . The output capacitor C ₀ , the first superposition capacitor C ₁ , and the first superposition capacitor C ₂ supply an output load R _o energy. In this phase,

Formula 1

When the time t is equal to the second start time t1, the main switch S ₁ is switched to non-conducting state, for the end of this phase.

The second stage [t: t1~t2]:

Referring to FIG. 4 and FIG. 6 , the main switch S ₁ is non-conducting, the auxiliary switch S ₂ is non-conducting, the first lifting diode D ₃ , the second lifting diode D ₄ , and the first The two superposed diodes D ₂ are turned on, and the first superimposed diode D ₁ and the output diode D ₀ are both non-conducting.

The time t at the beginning of this phase is equal to the second start time t1, and the leakage inductance current i _Lk starts to charge the parasitic capacitance C _r of the main switch S ₁ . The voltage across the parasitic capacitance V _Cr is increased from zero by resonance to the input voltage V _in plus the voltage across the clamping capacitor V _Cc (in other words, V _Cr =V _in + V _Cc ). The first lift diode D ₃ , the second lift diode D ₄ , and the second stacked diode D ₂ remain in an on state. Since the parasitic capacitance C _{r of} the main switch S ₁ is very small, the cross-over voltage v _{ds1 of} a main switch can be approximated as:

Formula 2

When the time t is equal to the third start time t2, the voltage across the parasitic capacitance V _{Cr is} charged equal to the input voltage V _in plus the voltage across the clamping capacitor V _Cc (in other words, V _Cr =V _in + V _Cc When the body diode of the auxiliary switch S ₂ is turned from non-conducting to conducting, this stage ends.

The third stage [t:t2~t3]:

Referring to FIG. 4 and FIG. 7 , the main switch S ₁ is non-conducting, and the auxiliary switch S ₂ will be turned from non-conducting to conducting, the first lifting diode D ₃ and the second lifting diode D ₄ , The second superimposed diode D ₂ is turned on, and the first superimposed diode D ₁ and the output diode D ₀ are both non-conductive.

The time t at the beginning of this phase is equal to the third start time t2, and the parasitic capacitance C _{r is} charged across the voltage V _Cr to be equal to the input voltage V _in plus the cross-voltage V _{Cc of} the clamp capacitor (in other words, V _Cr =V _in + V _Cc ), the body diode of the auxiliary switch S ₂ starts to conduct, and the leakage inductor current i _Lk starts to charge the clamp capacitor C _c via the body diode of the auxiliary switch S ₂ . And the voltage across the leakage inductance is a negative voltage:

...three

The current i _{Lk of} the leakage inductance begins to decrease, and the current of the second winding N ₂ and the third winding N ₃ of the coupled inductor also begins to decrease, so the conduction current i _{D3 of} the first lift diode, the first The conduction current i _D4 of the second lift diode and the conduction current i _{D2 of} the second superimposed diode also decrease. At this stage, the voltage across the auxiliary switch S ₂ is zero, and the condition of zero voltage switching (ZVS) is provided. In order to achieve the soft switching of the auxiliary voltage switch S ₂ , The auxiliary switch S ₂ must be switched to be turned on before the current i _{Lk of} the leakage inductance is reversed.

When the time t is equal to the third start time t3, the auxiliary switch S2 is switched from non-conducting to conducting, and the soft-cut performance of the zero-voltage switching performance is achieved, and the phase ends.

The fourth stage [t: t3~t4]:

Referring to FIG. 4 and FIG. 8 , the main switch S ₁ is non-conducting, and the auxiliary switch S ₂ is turned on in a state of zero voltage switching. The first lift diode D ₃ and the second lift diode D ₄ , and the second superimposed diode D ₂ will be switched from conduction to non-conduction, the first superimposed diode D _{1 is} maintained to be non-conducting, and the output diode D ₀ will be switched from non-conducting to conduction.

The time t at the beginning of this phase is equal to the fourth start time t3, and the auxiliary switch S _{2 is} switched to be turned on to achieve zero voltage switching. Since the leakage voltage V _Lk of the leakage inductance is a negative voltage, the current i _{Lk of} the leakage inductance continues to decrease, the conduction current i _{D3 of} the first lift diode, and the conduction current i of the second lift diode _D4 , and the conduction current i _{D2 of} the second superimposed diode continuously decreases. Because the coupled inductor has the leakage inductance L _k , the conduction current i _D3 of the first lift diode, the conduction current i _{D4 of} the second lift diode, and the second superimposed diode The rate at which the conduction current i _D2 falls is limited by the leakage inductance L _k , mitigating the first lift diode D ₃ , the second lift diode D ₄ , and the second superimposed diode D ₂ Reverse recovery problem.

When the time t is equal to the fifth start time t4, the conduction current i _D3 of the first lift diode, the conduction current i _{D4 of} the second lift diode, and the conduction current of the second superimposed diode i _D2 falls to zero, and the first lift diode D ₃ , the second lift diode D ₄ , and the second superimposed diode D _{2 are} naturally switched to be non-conductive. At the same time, the current direction of the second winding N ₂ of the coupled inductor changes, and the output diode D ₀ transitions to be turned on, and the phase ends.

The fifth stage [t: t4~t5]:

Referring to FIG. 4 and FIG. 9 , the main switch S ₁ is non-conductive, the auxiliary switch S ₂ is conductive, the first lift diode D ₃ , the second lift diode D ₄ , and the second The superimposed diode D ₂ is non-conducting, the first superimposing diode D ₁ will be switched from non-conducting to conducting, and the output diode D ₀ is conducting.

The time t at the beginning of this phase is equal to the fifth start time t4, and the first lift capacitor C ₃ and the second lift capacitor C ₄ start to discharge, and the energy is supplied to the output capacitor C ₀ . The voltage of the leakage inductance L _k and the magnetizing inductance L _m is equal to the voltage across the voltage V _Cc of the clamping capacitor, and thus the current i _{Lk of} the leakage inductance continues to decrease. In this stage, the current i _{Lk of} the leakage inductance drops to a change in the flow direction of the current, and the current i _{Lk of} the leakage inductance discharges the clamp capacitance C _c . When the clamp capacitor C _{c is} discharged, the voltage across the C _{Cc of} the clamp capacitor C _c decreases, so that the voltage of the first winding N ₁ decreases and the voltage across the third winding N ₃ V _N3 also drops to equal When the first superimposed capacitor crosses the voltage V _{C 1} , the first superimposed diode D ₁ is switched to be turned on.

When the time t is equal to the sixth start time t5, when the cross voltage V _{N3 of} the third winding is equal to the cross voltage V _{C 1 of} the first superposed capacitor, the first superimposed diode D ₁ is switched to be turned on. This phase ends.

The sixth stage [t: t5~t6]:

Referring to FIG. 4 and FIG. 10, the main switch S ₁ is non-conductive, the auxiliary switch S ₂ is conductive, the first lift diode D ₃ , the second lift diode D ₄ , and the second The superimposed diode D ₂ is non-conducting, the first superimposed diode D ₁ is turned on, and the output diode D ₀ will be switched from conductive to non-conducting.

The time t at the beginning of this phase is equal to the sixth start time t5, the first superimposed diode D ₁ is switched to be turned on, and the on-current i _{D1 of} the first superimposed diode starts to increase, and the current of the leakage inductance i _Lk continues to decrease, and the on-current i _{D0 of} the output diode begins to decrease.

When the time t is equal to the seventh start time t6, the on-current i _{D0 of} the output diode drops to zero, and the output diode D ₀ transitions to non-conduction, and the phase ends.

The seventh stage [t: t6~t7]:

Referring to FIG. 4 and FIG. 11 , the main switch S ₁ is non-conducting, and the auxiliary switch S ₂ will be turned from non-conducting to non-conducting, the first lifting diode D ₃ and the second lifting diode D ₄ , And the second superimposed diode D ₂ is non-conducting, the first superimposed diode D ₁ is turned on, and the output diode D ₀ is non-conducting.

The time t at the beginning of this phase is equal to the seventh start time t6, the output diode D ₀ is non-conductive, and the energy stored in the magnetizing inductance L _m is transmitted to the third winding N ₃ through the coupled inductor. The first superposition capacitor C _{1 is} charged.

When the time t is equal to the eighth start time t7 and the auxiliary switch S ₂ is switched from on to off, the phase ends.

The eighth stage [t: t7~t8]:

Referring to FIG. 4 and FIG. 12, the main switch S ₁ is non-conductive, the auxiliary switch S ₂ is non-conductive, the first lift diode D ₃ , the second lift diode D ₄ , and the first The two superposed diodes D ₂ are non-conducting, the first superimposed diode D ₁ is turned on, and the output diode D ₀ is non-conducting.

The time t at the beginning of this phase is equal to the eighth start time t7. Since the auxiliary switch S ₂ is non-conducting, the leakage inductance L _k and the parasitic capacitance Cr form a new resonant circuit and start to release the energy of the parasitic capacitance C _r . Since the parasitic capacitance C _{r is} small, the cross-voltage V _{Cr of} the parasitic capacitance drops rapidly. Since the voltage across the parasitic capacitance V _Cr continues to decrease, when the voltage across the leakage inductance L _k is a positive voltage, the current i _{Lk of} the leakage inductance begins to rise.

When the time t is equal to the ninth start time t8, since the voltage across the parasitic capacitance V _Cr drops to zero, the body diode of the main switch S ₁ is turned on, and this phase ends.

The ninth stage [t: t8~t9]:

Referring to FIG. 4 and FIG. 13 , the main switch S ₁ will be turned from non-conducting to conducting, the auxiliary switch S ₂ is non-conducting, the first lifting diode D ₃ and the second lifting diode D ₄ , And the second superimposed diode D ₂ is non-conducting, the first superimposed diode D ₁ is turned on, and the output diode D ₀ is non-conducting.

Start time t equal to the ninth stage of this start time T8, the main body ₁ of the switch S diode conducting, the voltage across the primary switch S ₁ of zero, the main switch S ₁ includes a condition of zero-voltage switching, in order for the main switch S ₁ is to achieve zero voltage switching of the soft cut performance, the direction of the current i _Lk leakage inductance from negative to positive before the master switch S ₁ is to be switched on.

When the time t is equal to a tenth of the start time T9, the main switch S ₁ is switched from the non-conducting to a conducting, to reach zero voltage switching, the end of this phase.

The tenth stage [t: t9~t10]:

Referring to FIG. 4 and FIG. 14 , the main switch S ₁ is turned on, the auxiliary switch S ₂ is non-conductive, and the first lift diode D ₃ and the second lift diode D ₄ will be turned into non-conducting. Turning on, the second superimposed diode D ₂ is non-conducting, the first superimposing diode D ₁ will be turned from non-conducting to non-conducting, and the output diode D ₀ is non-conducting.

Time start of the period t is equal to a tenth of the start time T9, the main switch S ₁ is switched from the non-conducting to a conducting, to reach zero voltage switching. The current i _{Lk of} the leakage inductance continues to rise. Due to the transformer current relationship of the coupled inductor, the conduction current i _{D1 of} the first superimposed diode continues to decrease.

When the time t is equal to the eleventh start time t10, when the current i _{Lk of} the leakage inductance rises to a current i _Lm equal to the magnetizing inductance (in other words, i _Lk =i _Lm ), then a first of the coupled inductor The current i _{N1 of the} winding is equal to zero, such that the current i _N3 of the third winding of the coupled inductor is equal to zero, and the first superimposed diode D ₁ is switched to be non-conducting, and the phase ends.

The eleventh stage [t: t10~t11]:

Referring to FIG. 4 and FIG. 15 , the main switch S ₁ is turned on, the auxiliary switch S ₂ is non-conductive, and the first lift diode D ₃ and the second lift diode D ₄ are turned on. The two superimposed diodes D ₂ will be turned from non-conducting to conducting, and the first superimposing diode D ₁ and the output diode D ₀ are non-conducting.

The time t at the beginning of this phase is equal to the eleventh start time t10, and the current i _{Lk of} the leakage inductance continues to rise, so that the current i _{Lk of} the leakage inductance rises to a current i _Lm greater than the magnetizing inductance (in other words, i _Lk >i _Lm ), so that the current i _N1 of the first winding of the coupled inductor is greater than zero, and an induced current of the second winding N ₂ of the coupled inductor is generated, thus flowing through the first lift diode D ₃ and lifting the second current diode D ₄ respectively on the first capacitor C ₃ and the lifting of the second lift charging capacitor C _4. The series output capacitor C ₀ , the first superposition capacitor C ₁ , and the second superposition capacitor C ₂ provide energy to the output load R _o .

When the eleventh time t equal to the end time T11, when superimposing the second capacitor C ₂ discharges, so that the voltage across the second capacitor C is superimposed V _{C2 2} is equal to the voltage across the third winding N _3, then the second The superimposed diode D ₂ transitions to conduction, and this phase ends.

After the eleventh phase is completed, the next switching cycle T _{s is} entered, and the first phase circuit operation is restarted.

Before doing the steady-state voltage gain analysis, in order to simplify the analysis, it is based on the following assumptions:

Hypothesis 1: Ignore the transient phase with very short time.

Hypothesis 2: Since the magnetizing inductance L _{m is} much larger than the leakage inductance L _k , the leakage inductance L _{k is} ignored, so the coupling coefficient .

Hypothesis 3: All the capacitors in the converter are large enough to ignore the capacitor voltage chopping, so that the electrical (cross) voltage of the capacitor can be regarded as a constant.

Hypothesis 4: The main switch S ₁ and the auxiliary switch S ₂ are complementary driving, and there is a very short blind time between the two, since the blind time is extremely short, if the main switch S ₁ has a conduction ratio D, the auxiliary The turn-on ratio of the switch can be regarded as 1 minus the turn-on ratio D (in other words, 1-D).

Voltage gain analysis:

In the operation analysis, when the main switch S _{1 is} turned on, the time is the conduction ratio D multiplied by the switching period T _s , in other words, the conduction time DT _s of the main switch, and the voltage across the voltage of the magnetizing inductor V _Lm is equal to the input voltage. V _in . The main switch S ₁ non-conducting, the switching period T _s Save the primary switch S ₁ is turned DT _s time for, in other words, there is a main switch is non-conductive time (1-D) T _s, the magnetizing inductance L _m of The voltage across the voltage V _Lm is equal to the voltage across the clamp capacitor V _Cc (in other words, V _Lm = -V _Cc ).

Due to the steady state, the inductor satisfies the volt-second balance principle, that is, the average voltage of the inductor during the switching period T _s is zero, therefore,

...four

Finishing, the clamp capacitor voltage V _Cc is obtained

Five

In the linear circuit diagram of the first stage (as shown in FIG. 5), it is known that the cross-voltage V _N1 of the first winding of the coupled inductor is

Equation six

At the same time, the voltage across the first boost capacitor V _C3 and the cross voltage V _{C4 of} the second lift capacitor in the voltage _boosting unit 2 can be across the voltage V of the first winding of the coupled inductor. The reflection of _N1 is derived from the voltage across the second winding, V _N2 . The crossover voltage V _C3 of the first lift capacitor and the cross voltage V _C4 of the second lift capacitor are

Equation seven

On the other hand, the voltage V _C2 of the second superposition capacitor in the voltage superimposing unit 3 is

Equation eight

In the sixth stage linear circuit (as shown in FIG. 10), it is known that the cross-voltage V _N1 of the first winding N ₁ of the coupled inductor is

Formula nine

The crossover voltage V _C1 of the first superposed capacitor in the voltage superimposing unit 3 is

Ten

The fifth generation of the formula is entered into ten, and the cross-over voltage V _C1 of the first superposed capacitor is obtained.

Equation eleven

On the other hand, in the sixth stage of the linear circuit (as shown in Figure 10), using the Kirchhoff's voltage law, the cross-voltage V _C0 of the output capacitor can be obtained as

Twelve

The formula 7 and the 9th generation are entered into the 12th, and the cross-voltage V _C0 of the output capacitor is obtained.

Thirteen

The expression of the cross voltage V _C0 that can be obtained by the output capacitor is

Fourteen

Because the output voltage V _o is the sum of the voltages of the three capacitors,

Fifteen

Finishing, the output voltage V _{o is} expressed as

Formula 16

Therefore, a voltage gain M of the high-boost DC converter of the present invention can be expressed as

Equation seventeen

From the above formula, the voltage gain is known, and the coupling inductance turns ratio n and the conduction ratio D are two design degrees of freedom. The high-boost DC converter of the present invention can achieve a high step-up ratio by appropriately designing the coupled inductor turns ratio n, and does not have to operate at a very large conduction ratio D.

Referring to FIG. 16, a voltage gain curve corresponding to the coupled inductor turns ratio n and the turn-on ratio D, when the turn-on ratio D is equal to 0.6 and the coupled inductor turns ratio n is equal to 1, the voltage gain M is 5.5. When the conduction ratio D is equal to 0.6 and the coupled inductance turns ratio n is equal to 3, the voltage gain M is 20.5.

Voltage stress analysis of switching elements:

From the first stage, the voltage stress of the auxiliary switch S ₂ is

Eighteen

Similarly, the voltage stress of the main switch S ₁ from the sixth stage is

Nineteen

The switching voltage stress of the high-boost DC converter of the present invention is only 1/(1+3n-nD) times of the output voltage V _o . As the coupling inductance turns ratio n increases, the switching voltage stress is greatly reduced. Below the output voltage V _o , a metal oxide semiconductor field effect transistor (MOSFET) with a low on-resistance R _{ds (ON)} can be used as a switch to reduce switching conduction losses and boost the converter. Overall efficiency.

Voltage stress analysis of diode components:

From the first stage of the circuit action analysis, the voltage stress of the first superimposed diode D ₁ is

Twenty

And the voltage stress of the output diode D ₀ is

Twenty-one

From the sixth stage of the circuit action analysis, the voltage stress of the first lift diode D ₃ is

Twenty-two

The voltage stress of the second lift diode D ₄ is

Twenty-three

The voltage stress of the second superposed diode D ₂ is

Twenty-four

According to the above formula 20~24, and the voltage gain M (Expression 17), the first superimposed diode D ₁ , the second superimposed diode D ₂ , and the first lift 2 The polar body D ₃ , the second lift diode D ₄ , and the output diode D _{0 both} have a low voltage stress far below the output voltage V _o , so the diode can select a low rated withstand voltage Schottky diodes with low turn-on voltage drop reduce conduction losses and improve overall converter efficiency.

Experimental simulation verification:

Referring to Figure 17, first verify the steady-state characteristics of the converter. When the load is 400 watts (W), the input voltage V _in is equal to 24 volts (V), and the output voltage V _o is equal to 380 volts, and the main switch S is controlled separately. voltages v ₁ and a first pulse modulation signal S ₂ of the auxiliary switch voltage V _GS1 and a second pulse modulation signal _gs2, the present invention is a high-DC converter of the boost voltage gain of approximately 15.8 M In addition, according to Equation 17, when the conduction ratio D is 0.52, the conduction ratio M of the simulation result conforms to the analysis result. It is verified that the high boost DC converter of the present invention has a high voltage gain but does not have to operate at a very large turn-on ratio.

Referring to Figure 18, when the full 400 watts, respectively, of the main control switch S ₁ is the first voltage v _GS1 pulse modulation signal of the auxiliary switch S _2, and voltage v of the second pulse modulation signal _GS2, which The cross-voltage v _{ds1 of the} main switch and the cross-over voltage v _{ds2 of} an auxiliary switch are about 57 volts according to the voltage stress analysis of the switching element, and the voltage stress of the switching element of the analog waveform is about 59 volts, so the switching element voltage stress of only about one-sixth of the output voltage V _o. The simulation results generally conform to the analysis results, verifying that the power switch of the high-boost DC converter of the present invention has the advantage of low voltage stress, and can use a metal oxide semiconductor field effect having a low on-resistance R _{ds (ON)} with a low rated withstand voltage. The transistor is used to reduce the switch conduction loss and improve the overall efficiency of the converter.

Referring to Figure 19, when full 400 watts, the primary switch S ₁ and the zero voltage of the auxiliary switch S ₂ of the switching waveform, it can be seen that the main switch S ₁ is and an auxiliary switch S ₂ before the switch is turned on, the main switch the voltage across the S v _{ds1 1} and the voltage across the auxiliary switch S a v _{ds2 2} have been reduced to zero, indeed achieve zero voltage switching operation, switching losses decrease.

Referring to FIG. 20, when the full load is 400 watts, the first superimposed diode D ₁ , the second superimposed diode D ₂ , the first lift diode D ₃ , and the second lift diode are passed. The current waveform of the body D ₄ and the output diode D ₀ is analyzed to show that the leakage inductance L _k can alleviate the rate at which the diode current drops. It can be seen from the figure that after the current of the diode drops to zero, almost no reverse recovery current is generated, so that the diode reverse recovery loss can be reduced.

Referring to FIG. 21, the first superimposed diode D ₁ , the second superimposed diode D ₂ , the first lift diode D ₃ , and the second lift diode D are fully loaded at 400 watts. ₄ , and the voltage stress waveform of the output diode D ₀ . As can be seen from the figure, the first superimposed diode D ₁ , the second superimposed diode D ₂ , the first lift diode D ₃ , the second lift diode D ₄ , and the output two The maximum voltage across the pole body D ₀ , that is, the voltage stress is much lower than the output voltage of 380 volts, and the simulation results are in accordance with the analysis results.

In summary, the above embodiment has the following advantages:

1. The turns ratio n of the coupled inductor composed of the first to third windings N ₁ to N ₃ increases the design freedom of the voltage gain M, so that the high voltage gain is achieved, the main switch S ₁ does not have to be operated at a very large The turn-on ratio.

2. Since the clamp capacitor C _c forms an active clamp circuit with the auxiliary switch S ₂ , the main switch S ₁ and the auxiliary switch S ₂ can achieve the soft cutting performance of zero voltage switching, so the switching can be reduced. loss.

3. Since the voltage stress of the main switch S ₁ and the auxiliary switch S ₂ is much lower than the output voltage V _o , a metal oxide semiconductor field having a low on-resistance R _{ds (ON)} with a low rated withstand voltage can be used. The effect transistor is implemented to reduce its conduction loss.

4. The leakage inductance of the coupled inductor can effectively alleviate the first superimposed diode D ₁ , the second superimposed diode D ₂ , the first lift diode D ₃ , and the second lift diode The problem of the body D ₄ and the reverse recovery current of the output diode D ₀ .

5. The leakage inductance energy can be recycled and reused, which not only improves the efficiency, but also avoids the voltage surge problem caused when the main switch S ₁ and the auxiliary switch S _{2 are} switched to be non-conducting.

However, the above is only the embodiment of the present invention, and the scope of the invention is not limited thereto, and all the simple equivalent changes and modifications according to the scope of the patent application and the patent specification of the present invention are still Within the scope of the invention patent.

2‧‧‧Voltage lifting unit

V _C2 ‧‧‧cross-voltage of the second superimposed capacitor

3‧‧‧Voltage superimposed unit

4‧‧‧Control unit

N ₁ ‧‧‧first winding

N ₂ ‧‧‧second winding

N ₃ ‧‧‧third winding

S ₁ ‧‧‧ main switch

S ₂ ‧‧‧Auxiliary switch

C _r ‧‧‧Clamp Capacitor

C _c ‧‧‧Clamp Capacitor

C ₀ ‧‧‧Parasitic capacitance of the main switch

C ₁ ‧‧‧First superimposed capacitor

C ₂ ‧‧‧second superposition capacitor

C ₃ ‧‧‧First Lifting Capacitor

C ₄ ‧‧‧Second lift capacitor

D ₀ ‧‧‧Output diode

D ₁ ‧‧‧First superimposed diode

D ₂ ‧‧‧Second superimposed diode

D ₃ ‧‧‧First lift diode

D ₄ ‧‧‧Second lift diode

R _o ‧‧‧output load

V _in ‧‧‧ input voltage

V _o ‧‧‧output voltage

L _m ‧‧‧magnetized inductor

L _k ‧‧‧Leakage inductance

V _C3 ‧‧‧cross-pressure of the first lifting capacitor

V _C4 ‧‧‧cross-voltage of the second lifting capacitor

V _{gs1 ‧‧‧voltage of the} first pulse modulation signal

V _{gs2 ‧‧‧voltage of the} second pulse modulation signal

V _ds1 ‧‧‧cross pressure of the main switch

V _ds2 ‧‧‧Auxiliary switch cross pressure

T _s ‧‧‧ switching cycle

t‧‧‧Time

T0~t10‧‧‧First start time~11th start time

T11‧‧‧ eleventh end time

i _In ‧‧‧Input current

i _o ‧‧‧Output current

i _S1 ‧‧‧ on-current of the main switch

i _S2 ‧‧‧ conduction current of the auxiliary switch

i _D0 ‧‧‧Connecting current of the output diode

i _D1 ‧‧‧ conduction current of the first superimposed diode

i _D2 ‧‧‧ conduction current of the second superimposed diode

i _D3 ‧‧‧ conduction current of the first lift diode

i _D4 ‧‧‧Connecting current of the second lift diode

Cross-pressure of V _Cr ‧‧‧ parasitic capacitance

V _Cc ‧‧‧Clamp capacitance across the voltage

V _C0 ‧‧‧voltage across the output capacitor

V _C1 ‧‧‧cross-pressure of the first superimposed capacitor

i _Lm ‧‧‧Magnetic inductor current

i _Lk ‧‧‧ leakage inductor current

n‧‧‧Coupling inductance turns ratio

Other features and effects of the present invention will be apparent from the following description of the drawings, wherein: Figure 1 is a circuit diagram of a conventional boost converter; Figure 2 is a high boost DC converter of the present invention. FIG. 3 is an equivalent circuit diagram of the embodiment; FIG. 4 is an operational timing diagram of the embodiment; FIG. 5 is a circuit diagram of the operation of the embodiment in the first stage; The embodiment is a circuit diagram of the second stage; FIG. 7 is a circuit diagram of the embodiment operating in the third stage; FIG. 8 is a circuit diagram of the embodiment operating in the fourth stage; FIG. 10 is a circuit diagram of the sixth stage of the embodiment; FIG. 11 is a circuit diagram of the seventh stage of the embodiment; FIG. 12 is a circuit diagram of the eighth stage of the embodiment. Figure 13 is a circuit diagram of the operation of the embodiment in the ninth stage; Figure 14 is a circuit diagram of the operation of the embodiment in the tenth stage; Figure 15 is a circuit diagram of the operation of the eleventh stage of the embodiment; Coupling Figure 17 is a waveform diagram of the drive signal, input voltage and output voltage of the switch; Figure 18 is a waveform diagram of the voltage across the switch drive signal and the switch; 19 is another waveform diagram of the voltage across the switch drive signal and the switch; FIG. 20 is a current waveform diagram of the diode; and FIG. 21 is a cross-sectional waveform diagram of the diode.

Claims (8)

A high-boost DC converter includes: a first winding having a first end electrically connected to an anode of an input voltage, and a second end electrically connected to a first common contact; The switch has a first end electrically connected to the first common contact and a second end connected to the ground, and the main switch is controlled to switch between a conducting state and a non-conducting state; and an auxiliary switch having a first And electrically connecting the second end of the first common contact, and the auxiliary switch is controlled to switch between an on state and a non-conduction state; a clamp capacitor having a first end electrically connected to the auxiliary switch a first end, and a second end of the anode electrically connected to the input voltage; a voltage lifting unit having a lifting input electrically connected to the first common contact, and a lifting output for An induced voltage from the first winding is boosted to generate a lift voltage output from the lift output thereof, the voltage lift unit includes a first lift capacitor having a first electrical connection to the lift input End and a second end; a second winding Having a first end and a second end electrically connected to the second end of the first lifting capacitor; a second lifting capacitor having a first end electrically connected to the second end of the second winding, and an electrical connection a second end of the lift output; a first lift diode having an anode electrically connected to the first end of the second winding, and a cathode electrically connected to the lift output; a second lifter diode having an anode electrically connected to the lift input terminal and a cathode electrically connected to the second end of the second winding; an output diode having an electrical connection to the lift output terminal a second end anode, and a cathode electrically connected to a second common contact; an output capacitor having a first end electrically connected to the second common contact and a grounded second end when the output diode When the body is turned on, receiving a charge from the lift voltage to generate a capacitor voltage proportional to the lift voltage; and a voltage superimposing unit electrically connecting the second common contact to be connected in series to the output capacitor, and will be from the first The induced voltage of a winding is boosted to generate a superimposed voltage, and the superimposed voltage and the capacitor voltage are summed to generate an output voltage, and the voltage superimposing unit includes a first superimposing diode having an electrical connection. a common contact anode and a cathode; a third winding having a first end and a second end electrically connected to the cathode of the first superimposed diode; a first superposing capacitor having an electrical connection Second of the three windings a first end, and a second end electrically connected to the second common contact; a second superimposed diode having an anode electrically connected to the cathode of the first superimposed diode and a cathode; and a first The second stacked capacitor has a first end electrically connected to the cathode of the second superposed diode, and a second end electrically connected to the first end of the first superposed capacitor. The high-boost DC converter of claim 1, wherein the first end of the first winding is a striking end and the second end of the first winding is a non-tapping end. The high-boost DC converter of claim 1, wherein the first end of the second winding is a striking end and the second end of the second winding is a non-tapping end. The high-boost DC converter of claim 1, wherein the first end of the third winding is a striking end and the second end of the third winding is a non-tapping end. The high-boost DC converter of claim 1, wherein the main switch is an N-type power semiconductor transistor, and the first end of the main switch is a drain, and the second end of the main switch is a source . The high-boost DC converter of claim 1, wherein the auxiliary switch is an N-type power semiconductor transistor, and the first end of the auxiliary switch is a drain, and the second end of the auxiliary switch is a source . The high-boost DC converter according to claim 1, further comprising a control unit, wherein the control unit generates a first pulse modulation signal for switching the main switch and a second pulse modulation for switching the auxiliary switch signal. The high-boost DC converter of claim 7, wherein the on-time of the main switch does not overlap with the on-time of the auxiliary switch.