JPH05167450A - A/d converter circuit - Google Patents

Abstract

PURPOSE:To improve the resolution and to allow the A/D converter circuit to hardly receive the effect of noise in the A/D converter circuit comprising a comparator comparing an analog signal with a triangle wave with a prescribed frequency and a prescribed amplitude to convert the signal into a PWM signal and a counter measuring a positive or negative period of the PWM signal and converting it into a digital signal. CONSTITUTION:A current measured value of a PWM signal 9 by a counter 31 and a measured value at least at one preceding time are added and the result is used for a digital output. Or the PWM signal 9 is measured for a positive period/(entire period) or a negative period/(entire period) or a period being a prescribed multiple of the period and converted into a digital signal. The current measured value of the PWM signal 9 and the measured value at least at one preceding time may be obtained by subtracting data corresponding to a rectangular wave duty obtained through the comparison between a prescribed voltage and a triangle wave from the data corresponding to the duty of the PWM signal 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital conversion circuit suitable for use in, for example, a motor control circuit.

[0002]

2. Description of the Related Art For example, in a motor control circuit or the like, there is one in which control is performed by software using a microprocessor. According to such a motor control circuit using software, since the analog / digital converter IC is used, there is a drawback that the cost becomes high. Further, between the analog / digital converter IC and the microprocessor, the number of bits is changed. Since it is necessary to connect with a large number of lines, the input / output port of the microprocessor is occupied by the lines from the analog-digital converter IC, and there is also a problem that the microprocessor cannot be effectively used.

Therefore, the applicant of the present invention compares a command signal, which is an analog signal, with a triangular wave having a constant frequency and a constant amplitude, and converts it into a pulse width modulation signal, and a clock for a positive or negative section of the pulse width modulation signal. We have previously filed a patent application for an analog-digital conversion circuit that does not require an analog-digital converter IC by using a counter that counts pulses and converts them into digital signals. The invention according to Japanese Patent Application No. 3-109799 is that.

Based on the invention according to the above-mentioned application, the applicant of the present invention is also based on (positive section) / (entire period) of pulse width modulation signal or a constant multiple thereof or (negative section) / (full period).
Alternatively, a patent application was previously filed for an analog-digital conversion circuit that can obtain digital data by multiplying it by a constant, thereby preventing a decrease in conversion accuracy due to temperature changes, aging changes, and the like. Japanese Patent Application No. 3-109
That is the invention of No. 800.

Further, the applicant of the present invention ensures that the digital output data does not change even if the DC component of the triangular wave changes with temperature and the offset voltage of the comparator changes with temperature. We have previously filed a patent application for an analog / digital conversion circuit that subtracts data corresponding to the duty of a rectangular wave obtained by comparing a constant voltage and a triangular wave from data corresponding to the duty of a pulse width modulation signal. That is the invention of Japanese Patent Application No. 3-137219.

[0006]

The present invention is a further improvement of the invention according to each of the above applications. That is,
According to the inventions according to the above applications, the resolution may not always be sufficient. In particular, when the number of clock pulses measured in the positive or negative section of the pulse width modulation signal is small, the resolution becomes poor. For example, if the internal frequency of the microprocessor cannot be increased with respect to the carrier frequency of pulse width modulation, there is a problem that a desired resolution cannot be obtained. According to the inventions of the above applications,
When noise is added to the plus and minus DC power supplies and the ground terminal of the triangular wave generation circuit and the comparator, the reference voltage and input voltage of the comparator fluctuate, the duty of the pulse width modulation signal fluctuates, and the digital conversion output fluctuates. there were. In particular, when a low-cost switching power supply was used as the power supply, it was easily affected by noise.

The present invention has been made in order to solve such a problem, and a comparator for converting an analog signal into a pulse width modulation signal by comparing it with a triangular wave having a constant frequency and a constant amplitude, and a pulse width modulation signal. In an analog-digital conversion circuit that has a counter that measures the positive or negative section of and converts it into a digital signal, an analog-digital conversion circuit that can increase the resolution and is not easily affected by noise The purpose is to provide.

[0008]

According to the present invention, a comparator for comparing an analog signal with a triangular wave having a constant frequency and a constant amplitude to convert the analog signal into a pulse width modulated signal, and measuring a positive or negative section of the pulse width modulated signal. And a counter for converting the pulse width modulated signal by the counter to a digital signal, and a value obtained by adding a current measured value of the pulse width modulated signal by the counter and at least one previous measured value is digitally output.

A value obtained by adding the current measured value of the pulse width modulated signal and the measured values up to a plurality of times before may be used as the digital output, or the digital output may be obtained in synchronization with the pulse width modulated signal. .. The digital output may be calculated and output at fixed intervals. Further, the (positive section) / (entire period) of the pulse width modulation signal or a constant multiple thereof may be used as the digital output, and the (negative section) of the pulse width modulation signal may be used.
The digital signal output may be / (all cycles) or a constant multiple thereof. Further, the digital output may be obtained by subtracting the data corresponding to the duty of the rectangular wave obtained by comparing the constant voltage and the triangular wave from the data corresponding to the duty of the pulse width modulation signal.

[0010]

The digital signal is converted into a pulse width modulation signal corresponding to the command signal level by comparing the analog signal and the triangular wave with the comparator, and the digital signal is obtained by measuring only the positive or negative section of the pulse width modulation signal with the counter. obtain. This digital signal corresponds to the analog signal level. By adding the current measured value of the pulse width modulated signal by the counter and the measured value of at least one before, the count value is at least approximately doubled, and the resolution is approximately doubled. By adding the current measured value of the pulse width modulated signal by the counter and the measured value of at least one before, the function as a low-pass filter is provided, and the noise resistance is improved.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of an analog / digital conversion circuit according to the present invention will be described below with reference to the drawings.
In FIG. 1, the speed command voltage 7 that is an analog signal is input to the low-pass filter 1, and the output of the low-pass filter 1 and the triangular wave 8 are input to the comparator 2. The output of the comparator 2 is input to the microprocessor 3 including the timer 31. The microprocessor 3 obtains a digital signal corresponding to the speed command voltage by using an internal clock pulse in the counter included in the timer 31, and
The inverter 4 is controlled so that the deviation between the rotation speed signal of the motor 5 from the encoder 6 and the digital signal becomes zero.

Next, the operation of the above embodiment will be described in detail with reference to FIG. The speed command voltage 7 is shown in FIG.
As shown in (a), it contains noise and other harmonic components. The speed command voltage 7 is passed through the low-pass filter 1 to become a low-pass filter output from which harmonic components are removed (see reference numeral 71 in FIG. 2B).

Low-pass filter output 71 of command voltage 7
Is compared with a triangular wave 8 having a constant frequency and a constant amplitude by a comparator 2. As shown in FIG. 2B, the low-pass filter output 71 of the command voltage 7 has a different level position across the triangular wave 8 depending on its level. Therefore, the output of the comparator 2 becomes a pulse width modulation (hereinafter referred to as “PWM”) signal 9 as shown in FIG. 2C according to the level of the low-pass filter output 71 of the command voltage 7. In other words, the width of the “H” (hereinafter “positive”) section of the PWM signal 9 represents the magnitude of the command voltage 7.

The counter of the built-in timer 31 of the microprocessor 3 counts the internal clock pulse having a constant frequency as shown in FIG. 2 (d). The built-in counter counts the internal clock pulse in the positive section of the PWM signal 9 as shown in FIG. 2 (e), and "TIMER" at the falling edge of the PWM signal 9 as shown in FIG. 2 (f).
It is initialized to store the count value in a buffer called, generate an interrupt request, and clear the count value. The count value of the counter is a digital signal. In the counter buffer, as shown in FIG.
The count value at the falling edge of the M signal 9 is stored.

The process when the interrupt request is accepted is performed through the procedure shown in FIG. That is, the data of the RAM named Th (n) is changed to Th
Copy to RAM named (n-1), TIMER
Copy the count value of the buffer to the RAM named Th (n), add the data in the RAM named Th (n) and the data in the RAM named Th (n-1) to the RAM named REF. make a copy. At the time of returning from the interrupt, Th (n) is the measurement data of the current positive section of the PWM signal, Th (n-1) is the measurement data of the immediately preceding section of the PWM signal, and REF is both of them. The sum is stored. This embodiment is characterized in that the value of REF is used as the output of the analog / digital conversion circuit. On the other hand, in the invention according to each of the above applications, T
The value of IMER was used as the analog / digital conversion circuit output.

As described above, the speed command voltage 7 which is an analog signal shown in FIG. 2A is converted into a digital signal through a series of operations from FIG. 2B to FIG. 2G, and this digital signal is used. The value of a certain counter buffer REF is used as a speed command value for speed control by software. That is, the microprocessor 3 calculates the deviation between the digitally converted speed command value and the rotation speed of the motor 5 from the encoder 6, and the inverter 4 is set so that the deviation becomes zero.
To control.

As in the above embodiment, the resolution of the analog-to-digital conversion circuit output is improved by using the digital output of the value obtained by adding the current measurement value of the counter of the timer 31 and the previous measurement value. Hereinafter, the reason will be described in detail with reference to FIGS. 4 and 5. To make the explanation easier to understand, the internal clock is 1H as shown in FIG.
The frequency of z and the triangular wave is 2.5 Hz. Further, since the internal clock and the triangular wave are asynchronous, they do not necessarily look like FIG. 4, but the case where it is easy to explain is selected and shown.
FIG. 4A shows an internal clock of the microprocessor,
(B) to (g) are PWM signals, and show the cases where the duty is 90%, 80%, 50%, 30%, 10%, and 5%, respectively. Circles on the waveforms (b) to (g) indicate data sampled by the internal clock. Also,
The numbers shown in the first row of (b) to (g) are the count values of the positive section, and the numbers of the second row are the previous count values (Th in FIG. 3).
(Corresponding to (n-1)) and the current count value (Th in FIG. 3)
The value (corresponding to (n)) (corresponding to REF in FIG. 3) is shown.

Here, taking FIG. 4 (b) as an example, when the duty of the PWM signal is 90%, the count value in the positive section is 2 or 3. The value obtained by adding the previous count value and the present count value is 5. Less than,
As the duty decreases from (c) to (g), the count value in the positive section gradually decreases and finally becomes 0, and the value obtained by adding the previous count value and the current count value also becomes 0. Therefore, the count value in the positive section can take four values from 3 to 0 corresponding to the duty of the PWM signal. On the other hand, the value obtained by adding the positive interval twice before and after can take six values from 5 to 0. In other words, if you add it twice, it can take more values than if you do not add it.
It can be seen that the resolution as digital output is improved by a factor of 1.5.

FIG. 5 shows a case where the internal clock is 1 Hz and the triangular wave is 11 Hz, and the frequencies of both are separated. P
The count value of the positive section of the WM signal is 12 from 11 to 0.
The value obtained by adding these values twice before and after can take 22 values from 21 to 0. Therefore, the resolution is improved by 22 / 12≈1.83 times by using the added value. In this way, the wider the difference between the frequencies of the internal clock and the triangular wave, the closer the ratio between the range of values that can be obtained only once in the positive interval and the range of values that can be obtained by adding the positive interval two times before and after the interval becomes closer to 2. To go. That is, the resolution is approximately doubled by using the value obtained by adding the front and back. Practically, an internal clock of several MHz and a triangular wave frequency of several hundred Hz to several KHz are selected.

As in the above-described embodiment, by adding a value obtained by adding the current measured value of the counter of the timer 31 and the previous measured value to the digital output, it operates as a low-pass filter, and the noise resistance is improved. Can be improved. The reason will be described below. In the technical field of digital signal processing, the operation of adding the previous value and the current value of the numerical value input at a certain fixed cycle and outputting the result is called a "first-order FIR filter" and functions as a low-pass filter. It has been known. FIR is a finite impulse response.
se). The FIR filter is represented by the block diagram shown in FIG. Z- ^{1 in} FIG. 6 indicates the function of storing the previous value.

In the above embodiment, the operation of adding the measured values two times before and after is performed by the interrupt process at each falling edge of the PWM signal, and is not necessarily performed at a constant interval. The above FIR that adds data
It does not match the filter exactly. But PW
When the duty change of the M signal is small (when the amplitude of the input signal to the analog-digital conversion circuit is small), the previous data and the current data are added almost every fixed period, and the same function as the FIR filter is achieved. I can say. Therefore, the addition operation has an effect of reducing high-frequency noise.

In the above-mentioned embodiment, FIG. 2 (c) (d) (e)
As shown in, the clock pulse was counted in the positive section of the PWM signal, but the PWM signal is "L" (hereinafter "negative").
The clock pulse may be counted in the section of (). In this case, the count value decreases when the command voltage is high.

In the above-described embodiment, the previous data and the present data are added by the interrupt processing for each falling signal of the PWM signal. However, the output of the analog-digital conversion circuit is calculated for each falling signal of the PWM signal. If not used, it is not necessary to perform addition in the interrupt processing at the falling edge of the PWM signal. For example, when it is desired to use the output of the analog / digital conversion circuit every 1 msec, the addition may be performed by the process every 1 msec. The processing for every 1 msec may be interrupt processing, or when the time management is not strict, processing may be performed by a routine of a fixed cycle instead of interrupt. Figure 7
Shows an example in which the addition is performed in the processing every 1 msec. As shown in FIG. 7A, the previous data is stored in Th (n−1) and the current data is stored in Th (n) by PWM.
This is done by a signal falling interrupt, and as shown in FIG.
The processing to obtain REF from within the WM signal falling interrupt is 1m
It is performed every sec, and the process moves to the interrupt process that moves the entire system. The value of REF, which is the added value, is not updated at each fall of the PWM signal, so the real-time property of the digital output signal is inferior, but the output that moves the system every 1 msec is used by using the analog-digital conversion circuit. If you want to get it, the software shown in FIG. 7 is sufficient.

In the example of FIG. 7, the previous data and the present data are added every 1 msec.
In order to obtain the same effect as in the case (3), it is desirable to add the values in almost the same period as the period of the triangular wave. Practically, it is designed so that the ratio of the two is about 1/4 to 4. Also, PW
In order to accurately measure the positive section of the M signal, (b) of FIG.
The interrupt priority of the process shown in (a) is preferably lower than the interrupt priority of the process shown in (a). That is, the condition is set so that an interrupt is always generated at the falling edge of the PWM signal. Further, for the same reason, it is preferable that the processing of (b) is set to allow multiple interrupts.

In the above-described embodiments, the measurement data of two times before and after the positive or negative section of the PWM signal by the counter is added, but the measurement data of three times before and after may be added. This example is shown in FIGS. As shown in FIG. 9, the internal clock is 1 Hz and the triangular wave is 3/10 Hz. 1
The measurement data of only one time can take 5 values from 0 to 4, but the value obtained by adding 3 times will take 11 values from 0 to 10, and the resolution is improved by 2.2 times. .. As described above, the greater the difference between the frequency of the internal clock and the frequency of the triangular wave, the higher the resolution, and the resolution approaches 3 times. At this time, the PWM signal falling interrupt processing is as shown in FIG. Also in this case, as shown in FIG. 7, the process of obtaining REF may be performed by another process routine.

It is also possible to add the measured data before and after 4 times and further 5 times. However, if the number of times of addition is increased, the interrupt processing time becomes longer and the response time as an analog-digital conversion circuit becomes longer. It is practical to add 2 to 4 times because it becomes longer.

In the above-described embodiments, the measurement data of only the positive section or the negative section of the PWM signal is added to obtain a digital output. However, as in the invention of Japanese Patent Application No. 3-109800, the frequency of the triangular wave changes. For the purpose of compensating for the above, the present invention is applied to the one in which the (positive section) / (entire cycle) or (negative cycle) / (entire cycle) of the PWM signal or a section which is a constant multiple of these is measured. May be. 10 (a), (b) and (c) show these various embodiments, and FIG. 11 shows the operation of the example of FIG. 10 (a).

First, the example of FIG. 10A will be described. The PWM signal is input to the timer 1 and the timer 2 built in the microprocessor 3. Reference numeral 31a indicates a timer 1 and reference numeral 31b indicates a timer 2. P for timer 1
The positive section of the WM signal and the negative section of the timer 2 are measured by the internal clock. Counter 1 of timer 1 is PW
The internal clock is counted only when the M signal is positive, and PW
It is initialized to store the count value in the buffer named TIMER1 at the falling edge of the M signal, generate a timer 1 interrupt request, and perform the operation of clearing the count value. The counter 2 of the timer 2 counts the internal clock only when the PWM signal is negative, stores the count value in the buffer named TIMER2 at the rising edge of the PWM signal, issues a timer 2 interrupt request, and clears the count value. The default setting is to perform the operation. Therefore, the latest measured value of the positive section is always stored in TIMER1 and the latest measured value of the negative section is stored in TIMER2.

Next, the interrupt processing at the rising edge of the PWM signal of the timer 2 will be described with reference to FIG. First, the RAM data named Tl (n)
Copy to RAM named l (n-1). next,
Copy the value of TIMER2 to Tl (n). And T
The values of l (n) and Tl (n-1) are added and stored in the RAM named TL. Therefore, in TL, a value obtained by adding the current count value Tl (n) and the previous count value Tl (n-1) in the negative section of the PWM signal is updated and stored for each rising edge. FIG. 11 (g) shows this state.

Next, the interrupt processing of the timer 1 at the fall of the PWM signal will be described. The process from the top to the third line in FIG. 12A is equivalent to the process in FIG.
The same processing is only performed for the positive section of the M signal. The fourth line in FIG. 12B shows TH obtained immediately, that is, a value obtained by adding the count value Th (n) of the current positive section and the count value Th (n−1) of the previous time, and the timer 2 interrupt processing. Using the obtained TL, (positive section) × (constant K) /
(All cycles) is calculated and stored in the RAM named REF. Note that the constant K is 2 ⁸ = 256 or 2 ¹⁶ = 6553, which is easy to process due to the microprocessor configuration.
It is practical to use 6. Here, the data obtained by adding twice the positive section and the entire cycle is used, and the noise reduction effect is obtained not only for the positive section but also for the entire cycle.
The line for TH, TL, and REF may be sent to another processing routine as shown in FIG. 7, instead of the interrupt processing of the timer 1 and the timer 2.

It is not always necessary to use a value obtained by adding twice as the total period. At this time, a value obtained by adding twice only in the positive section is used, but the effect of resolution improvement and noise reduction can also be obtained by this. Specifically, in FIG.
When obtaining F, REF ← (TH × K) / [{TH (n) + Tl (n)}
X2]. Since Th (n-1) and Tl (n-1) are not used as denominators, the total period data has a value of only once.

Next, the embodiment of FIG. 10B will be described with reference to FIGS. 13 and 14. The timer 1 measures the positive section of the PWM signal, and the timer 2 measures the entire period of the PWM signal. Therefore, the counter 1 of the timer 1 is initially set to perform the operation of FIG. 13D, and the counter 2 of the timer 2 is initially set to perform the operation of FIG. 13E. In FIG. 13E, the measurement of the entire period is set to be completed at the rising edge of the PWM signal, but it may be set to be completed at the falling edge. The timer 1 sets the count value in the positive section to "T" every time the PWM signal falls.
It is stored in a buffer called “IMER1”. Timer 2 is P
Every time the WM signal rises, the count value of all cycles is set to "TIMER
2 ”is stored in the buffer.

FIG. 14B shows the interrupt processing of the timer 2. An interrupt request shown in FIG. 14B is made at each rising edge of the PWM signal, the value of Tall (n) is copied to Tall (n−1), and the value of the buffer “TIMER2” is Tal.
1 (n) and Tall (n) and Tall (n-
TALL is obtained by adding 1). TALL stores the sum of the count value of the current cycle and the count value of the previous cycle.

FIG. 14A shows the interrupt processing of the timer 1. At each falling edge of the PWM signal, the interrupt request of FIG. 14A is made, the value of Th (n) is copied to Th (n−1), the value of the buffer “TIMER1” is copied to Th (n), The sum of Th (n) and Th (n-1) is T
Let H. Through these processes, TH is stored with the sum of the count value of the current positive section and the count value of the previous positive section. In the fourth line of FIG. 14A, TH and a constant K (in general, this constant K is shown in FIG.
(256 or 65536 is used as in the case of 1), the multiplied value is divided by TALL, and the result is substituted into REF to obtain an analog-digital conversion circuit output. In addition,
The line for calculating TH, TALL, and REF in FIG. 14 may be taken to another processing routine as shown in FIG. 7 instead of the interrupt processing of the timer 1 and the timer 2.

In the embodiment shown in FIG. 10B and FIGS. 12 to 14 described above, the positive section of the PWM signal,
The value obtained by adding the data of the previous time and the data of this time is used for all cycles, and the effect of improving the resolution and reducing the noise is obtained.

Next, the embodiment shown in FIG. 10C will be described with reference to FIGS. In this embodiment, as shown by reference numeral 31 in FIG. 10C, the microprocessor 3 has only one timer 1 built therein, and this timer 1 measures both the positive section and the negative section of the PWM signal. To do. The timer 1 is initially set to store the value counted in the buffer "TIMER1" at the rising and falling edges of the PWM signal, generate a timer 1 interrupt request, and clear the counter value.

15 and 16 show the interrupt processing of the timer 1. As shown in FIGS. 15 and 16, the PWM signal level is judged immediately after the interruption processing is started. If the PWM signal is positive, it corresponds to A in FIG. 15 (a), and it can be seen that the interrupt processing has started at the rising edge of the PWM signal, and the buffer "TIMER1" contains the measured value in the negative section. Become. At this time, Tl (n) is copied to Tl (n-1), and the value of the buffer "TIMER1" is copied to Tl (n). Then, Tl (n) and Tl (n-1) are added and stored in TL. It means that the data obtained by adding the data of the previous negative section and the data of the present negative section is constantly updated and substituted in TL.

If the level of the PWM signal is negative, it corresponds to B in FIG. 15 (a), and it is understood that the interrupt processing has started at the fall of the PWM signal, and the buffer "TIME" is entered.
R1 ”contains the measured value of the positive section. At this time, Th (n) is copied to Th (n-1),
Copy the value of the buffer "TIMER1" to (n).
This means that TH, which is obtained by adding the data of the previous positive section and the data of this time, is constantly updated and substituted. Further, TH and TL are added to obtain TALL (data obtained by adding the cycle twice), (TH × K) / TALL is executed, and REF is obtained as an analog-digital conversion circuit output. K is
As mentioned above, 256 and 65536 are selected. In addition, T
The work for obtaining H, TL, TALL, and REF may be carried out to another processing routine as shown in FIG.

Also in this embodiment, the value obtained by adding the previous data and the current data is used for the positive section and the entire cycle of the PWM signal, and the effect of improving the resolution and reducing the noise is obtained.

Next, the invention according to Japanese Patent Application No. 3-137219, that is, the digital output data changes even if the DC component of the triangular wave changes with temperature and the offset voltage of the comparator changes with temperature. In order to prevent this, an embodiment in which the present invention is applied to data obtained by subtracting data corresponding to the duty of a rectangular wave obtained by comparing a constant voltage and a triangular wave from data corresponding to the duty of a PWM signal explain. In this case as well, there are the following selection branches corresponding to the various variations described so far. Whether all cycle data is obtained from timer 1 or timer 2. Which processing routine is used to obtain TH, TL, TALL, and REF? Whether the measured value of the positive section of the PWM signal is used as the digital signal or the measured value of the negative section is used. Whether to use the value only once for all cycle data, 2
Do you want to use the sum of batch values? The duty of the rectangular wave is used as the reference. Whether the duty of the positive section or the negative section is used as the reference.

Here, an example having the following conditions will be described. Get all cycles from timer 2. Moreover, the value added twice is obtained. TH _1, TH _2, TL _2, TALL, REF timer 1 is calculated by the routine other than the timer 2 interrupt. The positive section of the PWM signal is measured as a digital signal. The value added twice is used for all cycle data. The duty of the positive section of the rectangular wave is used as a reference. The subscript i of THi and TLi indicates whether the data is from the comparator 1 or the data from the comparator 2. Thi () and Tl in FIG.
The subscript i of i () has the same meaning.

A specific example having the above conditions will be described with reference to FIGS. As shown in FIG. 17, two comparators 1 and 2 denoted by reference numerals 21 and 22 are used.
have. One of the comparators 1 compares the command signal 7 that has passed through the low-pass filter 1 and the triangular wave 8 to PW.
The M signal is obtained, and the other comparator 2 has the + terminal grounded and the triangular wave 8 input to the − terminal, so that the ground voltage of 0 V and the triangular wave 8 are compared, and the duty is 5%.
We get a 0% square wave. Microprocessor 3 has a reference numeral 31
Two timers 1 and 2 shown by a and 31b are built in, one timer 1 measures the positive section of the comparator 1, and the other timer 2 measures the positive section and the negative section of the comparator 2. There is. The timer 1 is set to store the count value in the buffer "TIMER1" at the falling edge of the PWM signal, request the timer 1 interrupt, and clear the counter 1. The timer 2 buffers the count value at each rising and falling of the rectangular wave with the buffer "TIMER".
2 ”, request a timer 2 interrupt, and clear the counter 2.

Next, the interrupt processing will be described with reference to FIG. In the interrupt processing of timer 1,
9 (a), Th ₁ (n) is copied to Th ₁ (n−1), the value of TIMER1 is copied to Th ₁ (n), and the process is ended. Data of this positive period of the PWM signal to the Th ₁ (n) is, the data of the previous positive period of the PWM signal is stored in the Th _{1 (n-1).} Timer 2
As shown in FIG. 19 (b), the interruption process of No. 1 is first divided into two by judging the level of the rectangular wave. When the level of the rectangular wave is “H”, it can be seen that the interruption was at the rising edge of the rectangular wave, as indicated by A in FIG. Therefore, TI
The count value of the negative section of the rectangular wave is stored in MER2. Therefore, copy the Tl ₂ (n) Tl ₂ to (n-1), by copying the Tl ₂ (n) to _{TIMER2, Tl 2 (n),} Tl 2 (n-1) in this time of the rectangular The data of the negative section of the wave and the previous one will be stored.
The same applies when the level of the rectangular wave is “L”, and Th
₂ (n), the Th ₂ (n-1) so that its data and the previous positive sections of this square wave is stored.

FIG. 19C shows an interrupt process for operating the system by utilizing the output of the analog / digital conversion circuit. In this interrupt processing, a value TH _{1 obtained} by adding twice the data of the positive section of the PWM signal, a value TH _{2 obtained} by adding twice the data of the positive section of the rectangular wave, and a value obtained by adding twice the data of the negative section of the PWM signal TL ₂ , the value TALL obtained by adding the period of the rectangular wave twice is obtained, and by using these, the digital output REF, that is, (K × TH ₁ ) / (TALL) − (K × TH ₂ ) /
(TALL) + K / 2− (offset correction amount) is calculated. This equation corresponds to the equation (7) described in the specification of Japanese Patent Application No. 3-137219.

As described above, in this embodiment, the values obtained by adding twice before and after to the positive section of the PWM signal, the positive section of the rectangular wave, and the negative section of the rectangular wave are used.
The resolution improving effect and the noise reducing effect can be obtained.
Further, by subtracting the value obtained by adding both the positive and negative sections of the rectangular wave corresponding to the duty of the rectangular wave twice before and after from the value obtained by adding the measured value corresponding to the duty of the PWM signal twice before and after, the triangular wave It is possible to prevent the fluctuation of the digital output due to the temperature change of the DC component, the offset of the comparator and the temperature change of the voltage.

As shown in FIG. 20, the input signals to the two input terminals of the comparator 2 may be reversed from those in the embodiment shown in FIG. That is, the triangular wave 8 is input to the + input terminal of the comparator 2, and the ground voltage, that is, 0 V is input to the-input terminal. The operation of this embodiment is shown in FIG. This example is different from the embodiment of FIG. 17 in that the positive and negative of the rectangular wave are inverted, and is basically the same as the example of FIG. In this embodiment, the value TH _{1 obtained} by adding twice the data of the positive section of the PWM signal, the value TH _{2 obtained} by adding twice the data of the positive section of the rectangular wave, and the value TH ₂ of the data of the negative section of the PWM signal are given.
The added value TL ₂ , the added value of the rectangular wave period twice TAL
L is obtained, and using these, the digital output REF, that is, (K × TH ₁ ) / (TALL) − (K × TL ₂ ) /
(TALL) + K / 2− (offset correction amount) is calculated. Thus, the point that the duty of the rectangular wave is obtained based on the value TL ₂ obtained by adding twice the data of the negative section of the PWM signal and subtracted from the duty of the PWM modulation signal is different from the embodiment shown in FIG. ..

Although the respective embodiments described above are the analog / digital conversion circuits for the motor control circuit, the analog / digital conversion circuit according to the present invention can be applied not only to the motor control circuit but also to various circuits. Is.

[0048]

According to the present invention, a comparator for comparing an analog signal with a triangular wave having a constant frequency and a constant amplitude and converting it into a PWM signal, and a positive or negative section of the PWM signal are measured and converted into a digital signal. In the analog-to-digital conversion circuit which does not require the IC for analog-to-digital conversion by providing the counter, a digital value obtained by adding the current measurement value of the PWM signal by the counter and at least the previous measurement value is obtained. Since the output is used, the resolution of the analog / digital conversion output can be improved. The resolution of the analog-to-digital conversion output is further improved by providing a digital output of a value obtained by adding the current measured value of the PWM signal and the measured values up to a plurality of times before. Further, by adding a value obtained by adding the current measured value of the PWM signal by the counter and the measured value at least one before to the digital output, the digital output has a function as a low-pass filter, and the accuracy of the digital output due to noise is increased. Can be prevented.

If the (positive section) / (entire cycle) or (negative section) / (entire cycle) of the PWM signal or a section of a constant multiple of these is measured and digitized, it is converted into a signal. The digital output data does not depend on the frequency of the triangular wave for obtaining the PWM signal, and stable and highly accurate digital conversion can be performed. Furthermore, using the value obtained by adding the current measurement value of the PWM signal and at least the previous measurement value, the PW
The digital output obtained by subtracting the data corresponding to the duty of the rectangular wave obtained by comparing the constant voltage and the triangular wave from the data corresponding to the duty of the M signal shows that the DC component of the triangular wave changes with temperature, and Even if the offset voltage of the comparator changes with temperature and the duty of the PWM signal and the duty of the rectangular wave change, these changes are canceled and a highly accurate analog-digital conversion circuit output with no error due to temperature change is output. Can be given.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an analog / digital conversion circuit according to the present invention.

FIG. 2 is a timing chart showing the operation of the above embodiment.

FIG. 3 is a flowchart showing an interrupt operation in the above embodiment.

FIG. 4 is a waveform diagram showing the resolution improving effect of the above-described embodiment under a fixed condition.

FIG. 5 is a waveform diagram showing the resolution improving effect of the above embodiment under another condition.

FIG. 6 is an equivalent circuit diagram showing that the above embodiment functions as a low-pass filter.

FIG. 7 is a flowchart showing an interrupt operation of another embodiment of the analog / digital conversion circuit according to the present invention.

FIG. 8 is a flowchart showing an interrupt operation of still another embodiment of the analog / digital conversion circuit according to the present invention.

FIG. 9 is a waveform diagram showing the resolution improving effect of the above-mentioned embodiment under a certain condition.

FIG. 10 is a block diagram showing various other embodiments of the analog-digital conversion circuit according to the present invention.

FIG. 11 is a timing chart showing the operation of the embodiment shown in FIG.

FIG. 12 is a flowchart showing an interrupt operation of the above embodiment.

13 is a timing chart showing the operation of the embodiment of FIG. 10 (b).

FIG. 14 is a flowchart showing an interrupt operation of the above embodiment.

FIG. 15 is a timing chart showing the operation of the embodiment shown in FIG.

FIG. 16 is a flowchart showing an interrupt operation of the above embodiment.

FIG. 17 is a block diagram showing still another embodiment of the analog-digital conversion circuit according to the present invention.

FIG. 18 is a timing chart showing the operation of the embodiment.

FIG. 19 is a flowchart showing various interrupt operations according to the embodiment.

FIG. 20 is a block diagram showing still another embodiment of the analog-digital conversion circuit according to the present invention.

FIG. 21 is a timing chart showing the operation of the above embodiment.

[Explanation of symbols]

 2 comparator 7 analog signal 8 triangular wave 9 pulse width modulation signal 31 counter 31a counter 31b counter

Claims (7)

[Claims] 1. A comparator for comparing an analog signal with a triangular wave having a constant frequency and a constant amplitude to convert it into a pulse width modulation signal, and a counter for measuring a positive or negative section of the pulse width modulation signal and converting it into a digital signal. An analog-to-digital conversion circuit comprising: and a digital output of a value obtained by adding a current measurement value of the pulse width modulation signal by the counter and at least one previous measurement value. Analog-to-digital converter circuit. 2. The analog-digital conversion circuit according to claim 1, wherein a value obtained by adding a current measured value of the pulse width modulated signal and a measured value up to a plurality of previous measured values is used as a digital output. 3. The analog-digital conversion circuit according to claim 1, wherein the digital output is obtained in synchronization with the pulse width modulation signal. 4. The analog-digital conversion circuit according to claim 1, wherein the pulse width modulation signal is measured at regular intervals. 5. An analog-to-digital conversion circuit for obtaining (positive section) / (entire period) of the pulse width modulation signal or a constant multiple thereof as a digital output, wherein the digital signal according to claim 1 is used as positive section data. An analog / digital conversion circuit that uses the output. 6. An analog-to-digital conversion circuit for obtaining (negative interval) / (entire period) of the pulse width modulation signal or a constant multiple thereof as a digital output, wherein the digital signal according to claim 1 is used as data in the negative interval. An analog / digital conversion circuit that uses the output. 7. A rectangular wave obtained by comparing a constant voltage and a triangular wave from data corresponding to the duty of the pulse width modulated signal, the present measured value and at least one previous measured value of the pulse width modulated signal by the counter. An analog-digital conversion circuit for obtaining a digital output by subtracting data corresponding to the duty of the pulse width modulation signal, wherein the numerator of at least the pulse width modulation signal duty is obtained by using the digital output according to claim 1. ..