KR900005763B1 - Control system with improved robustness to disturbances - Google Patents

Abstract

a detector (12) producing a detected signal corresponding to a controlled variable of a controlled system. An error circuit (3A) produces an error signal corresponding to the detected signal of the detector periodically; a memorising circuit (3C) renewing a number of memorised values sequentially and periodically at intervals of a renewing cycle period of time; and an output circuit (3B) producing a control signal corresponding to a second mixed value which is obtained by mixing the error signal of the error circuit and one or more memorised values of the memory.

Description

Controller

1 is a basic block diagram of a control system for controlling the speed of the motor.

2 is a circuit diagram of a speed detector usable in the control system of FIG.

3 is a flowchart of a microprocessor showing a representative embodiment of the control system of the present invention in combination with FIG. 1, FIG. 2 and FIG.

4 is a control block diagram of an embodiment of the present invention shown by the combination of FIG. 1, FIG. 2, and FIG.

FIG. 5 is a block diagram showing an example of the transfer function of the combining means used in FIG. 3 in which N = 3.

6 is a graph showing two amplitude frequency characteristics to illustrate the advantages of the present invention.

FIG. 7 is a flowchart of a microprocessor showing another exemplary embodiment of the control system of the present invention in combination with FIG. 1, FIG. 2 and FIG.

8 is a flowchart of a microprocessor representing another embodiment of the control system of the present invention in combination with FIG. 1, FIG. 2 and FIG.

* Explanation of symbols for main parts of the drawings

11: control system 12A: sensor

11A: Motor 12B: Speed Detector

11B: Driver 13: Control Block

11C: Load 13A: Microprocessor

12: detection block 13B: memory

13C: D / A Converter

The present invention relates to a control system, and more particularly, to a control system required to have good disturbance resistance as a control system for a motor.

In the conventional control system, the PI controller (proportional constant controller) has been widely used to improve the disturbance resistance or to suppress the influence of disturbance. Recently, PI controllers provide digital control for use in microprocessors. For example, a digital PI controller for a microprocessor to control the speed of a DC motor is published in Holt-Saunders International Editions., And published by Benjamin C.Kou in Chapter 14, Section 4, P689. It is shown in P694. PI controllers that do not account for analog or digital can improve disturbance at lower frequencies. However, recent demands for improving disturbance resistance have become even more severe in some applications.

For example, a control system for controlling the capstan motor speed of a video tape recorder requires a greatly improved disturbance to torque disturbance.

This is because the size and inertia of capstan motors have been greatly minimized in recent years.

A new control system for improved disturbance was filed in US Patent Application No. 917,498, filed on October 10, 1986, prior to this application. This control system has excellent disturbance resistance, but requires a large capacity in the RAM area, which makes the system expensive.

Recent integrated circuit technology creates a small amount of RAM on a single chip of a microprocessor. So, if a small RAM is used, it is possible to make a cheap and easy control system.

It is an object of the present invention to provide a control system having improved disturbance resistance by using a small ram area (memory).

It is another object of the present invention to provide a control system for a motor having improved torque disturbance by using a small ram area (memory). The object of the present invention is achieved with the following control system configuration: detection means for generating a detection signal corresponding to a control variable in the control system; Error means for generating an error signal corresponding to the detection signal to the detection means periodically at intervals equal to the detection time; A plurality of memory values are sequentially arranged at an update main period corresponding to Q times the detection period by a value corresponding to the first mixed value obtained by mixing one or more of the memory values updated at intervals between the error signal of the error means and the update period L. Memory means for updating periodically, Q and L are integers of 2 or more; And outputting a control signal corresponding to a second mixed value obtained by mixing at least one of an error signal of the error means and a memory value of the memory means, and supplying this signal to the control system to control the control variable of the control system.

1 shows a separation structure of an embodiment of the present invention, wherein the control system 11 has a controlled DC motor 11A and a driver 11B for supplying a current I _m (power) to the DC motor 11A ( Drive means). The DC motor 11A is controlled by the load 11C (the source of torque disturbance) rotating at a predetermined speed. The detection block 12 (detection means) has a sensor 12A (sensor means) and a speed detector 12B (speed detection means). The sensor 12A generates the sensor signal A _a at a frequency corresponding to P _a times the rotation frequency f _m [HZ] of the DC motor 11A, and P _a is an integer of 2 or more.

For example, for a capstan motor of a video tape recorder, P _a is 2000. The speed detector 12B obtains the detection signal B _b and the display character signal F _g for every one or one-half cycle (detection cycle) of the sensor signal A _a . The detection signal B _b has _a digital or coded signal in a digital part corresponding to one or one-half period of the sensor signal A _a , which is the speed of the DC motor 11A.

The display character signal F _g is set to " H " (high voltage) each time the speed detector 12B obtains a newly detected code or detected value. The detailed structure and operation of the speed detector 12B will be described later. The control block 13 (control means) includes a microprocessor 13A, a memory 13B including RAM and ROM, and a D / A converter 13C. A microprocessor (13A) is accomplished by issuing the operation on the instruction stored in the ROM of the memory (13B), the control block 13 is a control signal C _s, which corresponds to the input of the detection signal B _b, and the detection signal B _b a control system ( It supplies to the driver 11B of 11). Detailed operation of the microprocessor 13A will be described later. The driver 11B supplies a current I _m corresponding to the control signal C _s to the DC motor 11A to generate a generation torque proportional to the control signal C _s .

Therefore, the control loop (speed control loop of the 11A motor) includes the control system 11 (DC motor 11A and the driver 12B), the detection block 12 (the sensor 12A and the speed detector 12B). ) And the control block 13 (microprocessor 13A, memory 13B and D / A converter 13C), the control variable (speed of the DC motor 11A) of the control system 11 is a predetermined value. Controlled by (Scheduled Speed).

Referring to the structure of the speed detector 12B in detail, FIG. 2 shows the structure of the speed detector 12B, and the shaper 31 compares the sensor signal A _a with a predetermined voltage and converts the shaped signal G _g into an angular waveform. Occurs. The shaping signal G _g is used for the input terminal of the AND circuit 33 and the trigger input terminal CK of the D flip-flop 35. The time pulse signal C _p of the oscillator 32 and the overflow signal W _w of the counter 34 are used as the other input terminal of the AND circuit 33, respectively. The oscillator 32 has an ore oscillator and a frequency analyzer and generates, for example, a visual pulse signal C _p having a frequency of about 1 MHz that is greater than the frequency of the shaped signal G _g . The counter 34 is 12 bits long and sums all the output pulses H _h of the AND circuit 33. The overflow signal _Ww of the counter 34 is " H " when the capacity of the counter 34 remains below a predetermined value, and the overflow signal _Ww is such that the capacity of the counter 34 becomes larger than a predetermined value. Is changed to "L", where "H" and "L" mean a high voltage (5V) and a low voltage (0V), respectively. Since the data input terminal of the D-type flip-flop 35 is connected with "H", the display character signal F _{g which} is an output signal of the D-type flip-flop 35 is "H" for every timing of the falling edge of the shaping signal G _g . ". The reset signal R _r of the control block 13 can reset the capacitances of the counter 34 and the D flip-flop 35 to B _b ″ LLLLLLLL LLLL ”and F _g ″ L”.

The speed detector 12B in FIG. 2 explains the operation. If the capacitance of the counter 34 and the D flip-flop 35 is in the reset or initial state, the shaping signal G _g is " L ". After the shaping signal G _g changes from "L" to "H", the counter 34 sums the output pulses H _h of the AND circuit 33 with the time pulse C _p of the oscillator 32. When the shaping signal G _{g changes} from "H" to "L", the output signal H _h of the AND circuit 33 becomes "L", and the counter 34 maintains the capacity until the next change of the shaping signal G _g . . As a result, the holding capacity of the counter 34 is a digital or coded number that is inversely proportional to the speed of the DC motor 11A and proportional to the 1/2 cycle of the sensor signal A _a of the sensor 12A.

The display character signal F _g changes from "L" to "H" for each falling edge of the shaping signal G _g . The control block 13 inputs the detection signal B _b , that is, the holding capacity of the counter 34 after the display text signal F _g is checked as "H". Then, the control block 13 resets the capacitance of the counter 34 and the D flip-flop 35 by making the reset signal R _r "H" in a short time. This makes the initial state of the counter 34 and the D flip-flop 35 ready for the next detection. This is because the holding capacity of the counter 34 becomes large when the speed of the DC motor 11A becomes very low during the acceleration time.

When the operation of the control block 13 is described with reference to the operation flowchart of the microprocessor 13A shown in FIG. 3, it can be seen that the name and capacity of the register stored in the microprocessor 13A are indicated by the following indication. have. The microprocessor 13A executes the next task by the instructions stored in the ROM of the memory 13B.

[Error Block 3A (Error Meaning)]

(3A-1) The display character signal F _g is examined until the display character signal F _g becomes "H". The microprocessor 13A starts to operate so that each time the speed detector 12B obtains a new detection code corresponding to the current speed of the DC motor 11A, the following procedure is executed.

(3A-2) The detection signal B _b , i.e., the holding capacitance of the counter 34, is input and changed to a digital or coded value S. Then, the capacity of the counter 34 and the D flip-flop 35 is reset by making the reset signal R _r "H" in a very short time.

(3A-3) The difference value E _o is calculated between the detector S and the predetermined value Sref corresponding to the predetermined speed. That is E _o = Sref-S. The error signal E is then obtained by multiplying the difference value E _o by a predetermined amount of values R. E = RE _o The new value of the error signal E is detected at a detection main period corresponding to the period of the sensor signal A _a .

[Output block 3B (output means)]

(3B-1) The output signal Y is obtained by mixing the error signal E and the synthesis value V of the synthesis block 3Cb in the memory block 3C. As described later, the ratio is 1: D, and D is 0.25 or more. It is a positive real part less than 1.5.

(3B-2) The output signal Y is output to the D / A converter 13C as the control signal C of the control block 13.

[Memory block 3C (memory means)]

The memory block 3C includes a selection task block 3C _a , a synthesis block 3C _b , a filtering error block 3C _c and an update block 3C _d .

[Selective Task Block (3C)]

At each timing (3C _a -1), the signal error E is stored in register F (QI _a ), Q is an integer greater than or equal to 2, and I _a is the first count variable. F [QI _a ] = E.

(3C _a -2) The first count variable I _a is multiplied by the modulo number Q. 'I I _a = _a +1 (MOD Q) is' the meaning of the I = Q is _a I _a I _a = +1 and I _a = 0'. Because in modulo B, A is the rest of A / B. Thus, the first count variable I _{a changes} from 0 to Q-1, and multiplies the number in the form of a cycle each time the speed detector 12B is detected.

(3C _a -3) If I _a = 0, the microprocessor 13A executes the tasks of the synthesis block 3C _b , the filtering error block 3C _c and the update block 3C _d . If I _a = 0, the microprocessor 13A executes the tasks of the synthesis block 3C _b , the filtering error block 3C _c and the update block 3C _d . If I _a is not 0, I _a is from 1 to Q-1, and the operation of the microprocessor 13A returns to the task of the error block 3A.

[Synthesis block 3C _b (synthetic means)]

(3C _b -1) The second count variable I _b is multiplied by the modulo number NL, L is an integer greater than or equal to 2, is equal to the integral of P _a / Q, and N is a positive integer containing 1. _{'I b = I b +1 (} MOD NL)' is a meaning of 'I _b = NL is I _b = I _b +1 and I _b +0'. Thus, the second count variable I _{b changes} from 0 to NL-1, and multiplies the number in the form of circulation for each detection time Q of the speed detector 12B.

(3C _b ) Another integer J is substituted for J _b . J = I _b . The synthesized value V of the (3C _b -3) synthesis block (3C _b ) is N set of memo values M, such as the positive coefficient W _n (n = 1, ..., N) (n = 1 to N). [J-nL (MOD NL)] (n = 1, ..., N) is calculated by combining linearly. The n memory value M [J-nL (MOD NL)] (n = 1, ..., N) has been updated at intervals of the update cycle L. that is

이다.

to be.

W _n is

이고,

ego,

Preferably,

이어서,

next,

Easily calculate the composite value V. It can be seen that the N sets of memory values for calculating the composite value V are replaced with only one composite value V.

[Filtering error block 3C _c (filtering error means)]

The (3C _c -1) filtration error signal E _c is calculated by linear combination of the multiple values F jm k (m = 1,2, ...., F _d ), which are the values of the sequential error signal E according to the obtained timing. F _d is a positive integer of 2 or more and 2Q or less. that is

이고,

ego,

The coefficient B _m in the formula is positive and represents the following relationship.

The calculated value of the filtered error signal E _c , F [m] (m = 1,2, ...., Q) is the register F [Q + m) (m = 1,2, ...., Q) Are sent to each. F [m] (m = 1, 2, ..., Q) for each calculation time of the filtered signal E _c indicates that the calculation values of the error signal E are sequential with respect to the obtained timing. In addition, the filtering error block (3C _c ), which is a relation between equations (5) and (7), has a gain almost equal to 1 in the low frequency region, and has a low pass digital filter characteristic with a reduction gain considerably smaller than 1 in the high frequency region. Able to know.

[Update block 3C _d (update means)]

(C _d -1) The memory value M [b] stored at the address corresponding to the second count variable I _b in the RAM of the memory 13B is a combination of the mixed value of the filtered error signal E _c and the synthesis block 3C _b . The ratio V is updated to the ratio 1: 1. M [Ib] = E _c + v. The update memory value M [jIb] is maintained until the next update time of M [Ib]. It is later than the NL renewal cycle. As a result, an NL memory value is obtained from M [O] to M [NL-1], and the NL memory is sequentially updated periodically at intervals of an update cycle period corresponding to Q times the detection period. After the task execution of the update block, the operation of the microprocessor 13A returns to the task of the error block 3A.

The control system of the embodiment of the present invention shown by the combination of FIG. 1, FIG. 2, and FIG. 3 will be described in detail below with significantly improved disturbance. 4 is a control block diagram of this embodiment. The control system 11 includes the driver block 51 having the gain B _a of the driver 11B, the torque constant block 52 having the torque constant K _t of the direct current motor 11A, and the direct current motor 11A. Composed of a mixed point block 53, K ₁ / (J _m S) transfer function, minus the load torque T _d of the load 11C (torque disturbance) from the generated torque Tm, J _m Is the combined inertia of the DC motor 11A and the load 11C, K ₁ is a constant, 1 / S Laplace integral operator. The speed f _m of the DC motor 11A in the control system is detected by the detection block 12 having the gain K _v . The control block 13 is composed of a memory block 3C having an error block 3A, an output block 3B and a synthesis block 3C _b , a filtering error block 3C _c and an update block 3C _d . The error block 3A has a blending point block 61 for obtaining E _o a difference between the detected value S and the predetermined value Sref and a proportional gain block 62 having a gain R. The output block 3B has a gain block 71 having a gain D and a mixed point block 72 to which the combined value V of the error signal E and the memory block 3C is added.

The output block 3B supplies the output signal Y as the control signal C _s to the driver block 51 of the control system 11. The filtering error block 3C _c generates the filtered error signal E _c by linearly combining the values E _d of the sequential error signals E in accordance with the obtained timing. In the memory block 3C, the update block 3C _d updates the mixed value of the filtered error signal E _c and the synthesized value V of the synthesis block 3C _d to one memory value M [I _b ]. The synthesis block 3C _b calculates a composite value V in which the N sets of memory values updated at intervals of the update cycle L, such as positive coefficients Wn (n = 1, ..., N), are linearly combined. In FIG. 4, Z _d ⁻¹ and Z _r ⁻¹ denote time delays of one update cycle period T _r of one detection period T _d , respectively. that is

이다.

to be.

The update cycle period is equal to Q times the detection period. so

이다.

to be.

For example, FIG. 5 is a detailed block diagram of the synthesis block 3C _{b in which} N = 3 relationship. The transfer function of the synthesis block 3C _b has three delay elements 101, 102, 103, and the output signals of the three delay elements 101, 102, 103 are counted by the counting circuits 104, 105 ( The coefficients W ₁ , W ₂ , and W ₃ by 106 are linearly combined to generate an output signal (synthesis value). Each delay element 101, 102, 103 delays for the time of the update cycle L. Thus, in the control block 13, the memory block 3C has a positive feedback loop that bypasses the error signal E to the control signal C _s , and the positive loop includes a transfer function having a series of delay elements N in series. The output signal (synthesis value) is generated by linearly combining the output signals of the delay elements N, such as the positive coefficient W _n (n = 1, ..., N), and each delay element N is the update cycle L. Delay for time. The control block 13 supplies a control signal C _s to the driver block 51 of the control system 11, and the DC motor 11A generates a generation torque T _m proportional to the control signal C _s .

The disturbance in the control system of this example is represented by a function of transmitting the torque disturbance T _b at the speed f _m of the DC motor 11A. that is

이다.

to be.

H (s) and F (Z _d ) in the formula

이다.

to be.

The frequency transfer function G _x (jω) of Eq. (11) where S = jω is given by the following equation at the bottom of the control frequency domain.

이고

ego

G0 (jω) is

이다.

to be.

The frequency transfer function G _o (jω) represents the conventional disturbance resistance of the conventional control system without the memory block (C). Equation (14) is obtained by multiplying the present disturbance G _x (jω) in the embodiment of the present invention by the frequency transfer function H (jω) and the conventional disturbance resistance in the low frequency region.

6 shows two examples of amplitude frequency characteristics in the low frequency region, and the following relationship is obtained.

The amplitude frequency characteristics 6A and 6B of FIG. 6 are (n = 2, W ₁ = 0, ₅ , W ₂ = 0.5, D = 1) and (N = 3, W ₁ = 0.33333, W ₂ =). 0.33333, D = 1), and each of the amplitude frequency characteristics 6A and 6B is a function of the frequency f _r having a period corresponding to L times the update cycle period T _r . Where f _r is

ego,

It can be seen that the amplitude of H (jω) is 0 at the frequency kf _r (k = 0,1,2 ...). As a result, the amplitude of G _x (jω) is also zero at this frequency. At different frequencies the amplitude H (jω) is equal or equal to 1, meaning that the amplitude of G _x (jω) is equal to the amplitude of G _o (jω). Thus, the control system of the embodiment of the present invention has a significantly improved torque disturbance at a special frequency kf _r (k = 0,1,2 ...).

In the case of the control system for controlling the speed of the motor described above, it is preferable that the time of the update cycle L is equal to an integer multiple of one rotation period of the motor. that is

or

이다.

to be.

K is a positive integer. This is because the control system for controlling the speed of the motor has many harmonic complexes of torque disturbances simultaneously occurring at the motor speed F _m , but the harmonic compound of such torque disturbances is represented by the equation (18) or (19). There is no influence on the motor speed f _m of the embodiment of the present invention.

The control system of the embodiment of the present invention shown by the combination of FIG. 1, FIG. 2, and FIG. 3 uses a relatively small RAM described later. The selection task block 3C _a in the memory block 3C performs the tasks of the synthesis block 3C _b , the filtering error block 3C _c and the update block 3C _d corresponding to the first count variable I _a . Or choose not to perform. A microprocessor (13A) is detected cycle Q (QT _d = T _r) error block (3A) and Q such block (3C _d) (3C _c) for each times the duty of the output block (3B) and (3C _d) the Perform a series of missions only once. The number of memory values M jI _b k (I _b = 0,1, ..., NL-1) of the update block 3C _d is NL corresponding to the word size of RAM, and L is obtained from equation (19). Same as KP _a / Q. P _a is the number of detection of the error block 3A per one rotation of the DC motor 11A, and P _a is always a large number. In this case P _a is 2000. K is a positive integer to represent the frequency f _r and K will be 1 or 2. N is a positive number for most disturbances in the frequency domain between kf _r (K + 1) kf _r (K = 0,1, ...) and N is 1,2 or 3.

So the ram size NL is greatly affected by the integer Q, and a larger Q can make a smaller ram size. Than 4000 words in the case where there is no _{P a = 2000, K = 1} , N = 2, if Q = 10, selected assignment block (3C _a) the present invention RAM size NL is selected assignment block (3C _a) with It's only 400 words much smaller. Thus, the ram size of the control system of the present invention is significantly reduced. It can be seen that the reduction of the ram size of the present invention does not affect the disturbance resistance of the control system for the following reason.

(1) The control frequency range of the control system is much smaller than 1/10 of the sensor signal A _a frequency.

(2) Torque disturbance in the control system is mostly a component corresponding to the rotational speed f _m of the DC motor 11A at the bottom of the control frequency region at all times. Thus, using a small wrap, the control system of the present invention can replace the required low frequency region.

The mixed value for updating the memory value is preferably calculated by use of the filtered error signal E _c without using the error signal E directly. The reason for this is that if the component is larger than (P _a / Q) fm caused by torque disturbance or electrical noise, the sampling operation of the memory block (3C) will cause the memory value M [I _b ] to be adversely affected in the control system. Switch to ingredients. The filtering error block 3C _c thus gives a great advantage in reducing the adverse effects.

7 is another flow chart of the operation of the microprocessor 13A in the control block 13, and shows another embodiment of the present invention by the combination of FIG. 1, FIG. 2, and FIG. The flowchart of FIG. 7 is as follows.

[Error Block 7A (Error Meaning)]

(7A-1) The display character signal F _g is checked until the display character signal F _g becomes "H". It starts the microprocessor 13A by executing the following procedure each time the speed detector 12B obtains a new detection code corresponding to the current speed of the DC motor 11A.

(7A-2) The detection signal B _b , i.e., the holding capacitance of the counter 34, is input or changed into the digital or coded value S. The capacitance of the counter 34 and the D flip-flop 35 are then reset by making the reset signal R _r "H" for a very short time.

(7A-3) The difference value E _o is calculated between the detected value S and the predetermined value Sref corresponding to the predetermined speed. That is E _o = Sref-S.

(7A-4) The proportional value E _p is obtained by multiplying the positive predetermined value R by the difference value E _o . That is E _p = RE _o . The integral value E _g is obtained by adding the past value E _g and the proportional value E _p . It is E _g = E _g + E _p . The error signal E is computed by mixing 1: K _g with the proportional value E _p and the integral value E _g . Where K _g is a positive constant. It is E = E _p + K _g E _g . Thus, the error block 7A includes a proportional integral filter means, so that the error signal E has not only a proportional part but also an integral part of the difference region E _o . The new value of the error signal E is obtained at intervals of the detection period corresponding to the period of the sensor signal A _a .

[Output block 7B (output means)]

(7B-1) The output signal Y is described later, but is obtained by mixing the combined value V _o and the error signal E of the synthesis block 7C _b in the memory block 7C at a ratio 1: D. Where D is a positive real number of 0.25 or more and 1.5 or less.

(7B-2) The output signal Y is output to the D / A converter 13C as the control signal C _s of the control block 13.

[Memory Block 7C (Memory Means)]

The memory block 7C is composed of a selection task block 7C _a , a synthesis block 7C _b , a filtering error block 7C _c and an update block 7C _d .

[Selective Task Block (7C _a )]

(7C _a -1) At this timing, error signal E is stored in register F [QI _a ], reverse Q is an integer greater than or equal to 3, and Ia is the first count variable. It is F [QI _a ] = E.

(7C _a -2) The first count variable I _a is multiplied by the modulo number Q. _{'I a = I a +1 (} MOD Q)' is a meaning of _a = Q is I I I _a = _a +1 and I _a = 0. Thus, the first count variable I _{a changes} from 0 to Q-1, and multiplies the number in the form of a circulation at each detection time of the speed detector 12B.

If (7C _a -3) I _o = Q _a , after the next detection period, the synthesized value V _o used in the output block 7B is replaced by the newest synthesized value V [P]. Where Q _a is an integer between 0 and Q-1. If I _a is not equal to Q _a , no substitution is performed.

(7C _a -4) If I _a = Q-1, the microprocessor 13A executes the task of the synthesis block 7C _b . If I _a = 0, the microprocessor 13A executes the task of the filtering error block 7C _c . If I _a is not equal to Q-1, 0, 1, it is I _a from 2 to Q-2, and the operation of microprocessor 13A returns to the task of error block 7A.

Synthesis Block 7Cb (Synthesis Means)

(7C _b -1) The second count variable I _b is multiplied by the modulus NL. Where L is an integer of 2 or more, and preferably an integer times of _a P / Q, N is a positive integer, including one. _{'I b = I b +1 (} MOD NL)' is a meaning of the reverse surface _{I b = NL I b = I} b +1 and I _b = 0. Thus, the second count variable I _b varies from 0 to NL-1, and multiplies the number in the form of a circulation for each detection time Q of the speed detector 12B.

The operation of (7C _b -2) 'J = I _b + P (MOK NL)' is performed to obtain an integer J which continues P to the second count variable I _b . Where P is an integer of 1 or more and 5 or less. The preferred number of P changes with Q, Q _a and F _d .

Another set of (7C _b -3) registers V jm k (m = 0, ..., P) is used to store the composite. The capacity of register V jm + 1 k is transferred to register V [m] from m = 0 to m = P-1.

(7C _b -4) The newest synthesized value V [P] is the N set of memory values M [J, such as a positive coefficient W _n (n = 1, ..., N) from n = 1 to n = N. -nL (MOD NL)] (n = 1, ..., N) is computed by combining linearly. Here, N memory values M [J-nL (MOD NL)] (n = 1, ..., N) have been updated at intervals of the update cycle L. that is

to be. The coefficient W _n (n = 1, ..., N) has the same relationship as in the formulas (2) to (4). As a result, a plurality of sequential synthesized values V [m] (m = 0, ..., P) are obtained with respect to the timing. The synthesized value V _o used in the output block 7B after the next detection time is replaced by one new synthesized value V [P-1].

V [O] is the oldest composite for use in update block 7C _d at each update time, V [P] is the newest synthesized value for use in output block 7B at every subsequent time, and V [P ] And V [O] have an interval of update cycle period P. Thus, the composite block 7C _b calculates the composite value V jm k (m = 0, ..., P) for future use. After the task of the synthesis block 7C _b , the operation of the microprocessor 13A returns to the task of the error block 7A.

[Filtering error block 7C _c (filtering error means)]

(7C _c -1) The filtered error signal E _c is calculated by linearly combining the multiple values F [m] (m = 1,2 ..., E _d ) of the sequential error signal E with respect to the obtained timing. . Where F _d is an integer greater than or equal to 2 and less than or equal to 2Q. that is

to be. The coefficient B _m is positive and is a relationship between equations (6) and (7). After calculating the filtration error signal E _c, the calculated value F [m] (m = 1,2 ..., Q) is set to register F [Q + m] (m = 1,2, ..., Q), respectively. Is sent. It is understood that the estimated value F [Q + m] (m = 1, 2, ..., 2Q) has a sequential error signal E with respect to the obtained timing for each calculation period of the filter signal E _c . In addition, the filtering error block 7C _c related to Equations (21), (6) and (7) has a low band digital filter characteristic having a gain of about 1 in the low frequency region and a reduction gain of less than 1 in the high frequency region. It can be seen that it has. After the task of the filtering error block 7C _c , the operation of the microprocessor 13A returns to the task of the error block 7A.

[Update block 7C _d (update means)]

(7C _d -1) The integer K is calculated by subtracting the integer K _d from the second count variable I _o with the modulo number NL. Where K _d is a positive integer and preferably K _d = 2.

(7C _d -2) sets of registers X jm k (m = 0,1, ..., 2K d) is used to update calculated value. The capacity of register [m + 1] is transferred sequentially to register X [m] from m = 0 to m = 2K _d −1. The capacity of the register X [2K _d ] is changed by a mixture of the ratio 1: 1 of the filtered error signal E _c of the filtering error block 7C _c and the synthesized value V jO k of the synthesis block 7C _d . It is X [2K _d ] = E _c + V [O]. As a result, 2K _d +1 of the mixed value E _c + V [O], i.e., the mixed value stored in such register X [m] (m = 0,1, ...., 2K _d ) which is sequential with respect to the obtained timing. Updated by linear combination. that is

to be. The coefficient C _m in the equation is

The update memory M [K] is maintained until the next update time of M [K] after the NL update cycle. As a result, NL memory values M [O] to M [NL-1] are obtained, and the NL memory values are sequentially and periodically updated at intervals of an update cycle period corresponding to Q times the detection period. After the task of the update block 7C _d , the operation of the microprocessor 13A returns to the task of the error block 7A.

Furthermore, the embodiment of the present invention by the combination of FIG. 1, FIG. 2 and FIG. 7 has the following advantages.

(1) The disturbance and disturbance of this embodiment was further improved than the embodiment shown by the combination of FIG. 1, FIG. 2 and FIG. This is because the error block 7A includes proportional integral means.

(2) The task of the microprocessor in the detection cycle is greatly reduced. This is because the task of the memory block 7C _b is divided into three sub-tasks: a synthesis block 7C _b , a filtering error block 7C _c , and an update block 7C _d , which have many estimates using the square of the number. to be. This makes the calculation delay of the microprocessor 13A small, and an ordinary microprocessor without hardware squarer can be used as the microprocessor 13A in this embodiment.

(3) Improvements in the synthesis block 7C _b and the update block 7C _d make the control system stable with this embodiment. In particular, the use of the new or newest composite in the output block 7B compensates for the time delay of the filtering error block 7C _c .

8 is another flow chart of the operation of the microprocessor 13A of the control block 13, and shows another embodiment of the present invention by the combination of FIG. 1, FIG. 2, and FIG. The flowchart of FIG. 8 is as follows.

[Error Block 8A (Error Meaning)]

(8A-1) The display character signal F _q is examined until the display character signal F _q becomes "H". It starts operation by executing the following procedure each time the microprocessor 13A obtains a new detection code corresponding to the current speed of the DC motor 13A of the speed detector 12B.

(8A-2) The detection capacity B _b , i.e., the holding capacitance of the counter 34, is inputted into the digital or coded value S and changed. Then, the capacity of the counter 34 and the D flip-flop 35 is reset by making the reset signal R _r "H" in a very short time.

(8A-3) The difference value E _o is calculated between the detected value S and the predetermined value S _ref corresponding to the predetermined speed. It is E _o = S _ref -S. The error signal E is then obtained by multiplying the positive predetermined value R by the difference value E _o . That is E = RE _o . The new value of the error signal E is obtained for each interval of the detection period corresponding to the period of the sensitive signal A _a .

[Output block 8B (output means)]

(8B-1) The proportional value Y _p is obtained by mixing the combined value V _o of the combined block 8C _b and the error signal E in the memory block 8C having a ratio 1: D described later. Where D is a positive real number of 0.25 or more and 1.5 or less. Calculated by the addition of the integral Y _g , the eigenvalue Y _g, and the proportional value Y _p . That is Y _g = Y _g + Y _p . The output signal Y is a value proportional to the integral value Y _p Y _g ratio 1: is calculated by a mixture of K _g. Where K _g is a positive constant. It is Y = Y _p + K _g Y _g .

(8B-2) The output signal Y is output to the D / A converter 13C as the control signal C _s of the control block 13. Thus, the output block 8B includes a proportional part filter means so that the output signal Y has an integral value of the mixed value E + DV _o as well as the proportional part.

[Memory Block 8C (Memory Means)]

The memory block 8C is composed of a selection task block 8C _a , a synthesis block 8C _b , a filtering error block 8C _c and an update block 8C _d .

[Optional mission block (8C _a )]

(8C _a -1) At this timing, error signal E is stored in register F [QI _a ], where Q is an integer greater than or equal to 3 and Ia is the first count variable. It is F [QI _a ] = E.

(8C _a -2) The first count variable I _a is multiplied by the modulo number Q. _{'I a = I a +1 (} MOD Q)' is a meaning of 'I _a = Q is I _a = I _a +1 and I _a = 0'. Thus, the first count variable I _{a changes} from 0 to Q-1, and multiplies the number in a cyclic fashion at each detection time of the speed detector 12B.

If (8C _a -3) I _a = Q _a , the synthesized value V _o used in the output block 8B after the next detection time is dashed by the newest synthesized value V [P]. Where Q _a is an integer between 0 and Q-1. If I _a is not equal to Q _a , no substitution is performed.

(8C _a -4) If I _a = Q-1, the microprocessor 13A executes the task of the synthesis block 8C _b . If I _a = 0, the microprocessor 13A performs the task of the filtering error block 8C _c . If I _a is not Q-1, 0 or 1, then I _a is from 2 to Q-2, and the operation of microprocessor 13A returns to the task of error block 8A.

Synthesis Block 8Cb (Synthesis Means)

(8C _b -1) The second count variable I _b is multiplied by the modulus NL. Where L is the integral product of P _a / Q and is a positive integer containing one. It _{is, 'I b = I b +1} (MOD NL) is if _{I b = NL I b = I} b +1 and I _b = 0' is a meaning of. Thus, the second count variable I _b varies from 0 to NL-1, and multiplies by a cyclic number for each detection time Q of the speed detector 12B.

The operation of (8C _b -2) 'J = I _b + P + K _d (MOD NL)' is performed to obtain an integer J which continues P + K _d to the second count variable. P is an integer of 1 or more and 5 or less, K _d is an integer of 2 or more, preferably K _d = 2. The preferred number of P changes for Q, Q _a and F _d .

The register X jm k (m = 0,1, ..., 2K _d ) of the (8C _b -3) set is used to compute the composite. The capacity of register X jm + 1 k is transferred to register X jm k sequentially from m = 0 to m = 2K _d −1.

The capacity of (8C _b -4) register X [2K _d ] is the N set of memory values M [J, such as a positive coefficient W _n (n = 1, ..., N) from n = 1 to n = N. -nL (MOD NL)] (n = 1, ..., N). N memory values M [J-nL (MOD NL)] (n = 1, ..., N) have been updated at intervals of the update cycle L. that is,

to be. The coefficient W _n (n = 1, ..., N) in the formula is the same relationship as in the formulas (2) to (4). As a result, a linear combination X jm k (m = 0, ..., 2K _d ) which is sequential with respect to timing is obtained.

(8C _b -5) Another set of registers V [m] (m = 0, ...., P) is used to store the composite value. The capacity of register V [m + 1] is transferred to register V [m] from m = 0 to m = P-1.

The new composite value V [P] of the (8C _b -6) synthesis block (8C _b ) is a linear combination X jm k (m =) as the positive coefficient C _m (m = 0,1, ..., 2K _d ). 0,1, ..., 2K _d ) are computed for a linear combination. that is

to be. The coefficient C _m in the equation is a relation between equation (23) and equation (24). As a result, a plurality of sequential synthesized values V [m] (m = 0, 1, ..., P) are obtained for the timing. V [O] is the oldest composite for use in update block 8C _d at the next updater, V [P] is the newest synthesized for use in output block 8B at a future time, and V [P ] And V [O] have an interval of update cycle period P. Thus, the composite value V [m] (m = 0, 1, ... P) is calculated for use as the composite block 8C _a . After the task of the synthesis block 8C _b , the operation of the microprocessor 13A returns to the task of the error block 8A.

[Filtering error block 8C _c (filtering error means)]

(8C _c -1) The filtered error signal E _c is calculated by linearly combining the multiple values F [m] (m-0, 1, ..., F _d ) of the sequential error signal E with respect to the obtained timing. Where F _d is an integer of 2 or more and 2Q or less. that is

to be. The coefficient B _m in the equation is positive and is a relationship between equation (6) and equation (7). After calculating the filtered error signal E _c, the estimate [m] (m = 0,1, ..., Q) is assigned to each register F [Q + m] (m = 1,2, ..., Q). Is sent). It can be seen that the estimated value F [m] (m = 1, 2, ..., 2Q) at the time of calculating the filtration signal E _c is an estimate of the error signal E that is sequential with respect to the obtained timing. In addition, the filtering error block 7C _c related to Equations (27), (6) and (7) has a low band digital filter characteristic having a gain of about 1 in the low frequency region and a reduction gain of less than 1 in the high frequency region. It can be seen that it has. After the task of the filtering error block 8C _c , the operation of the microprocessor 13A returns to the task of the error block 8A.

[Update block 8C _d (update means)]

(8C _d -1) The stored value M [I _b ] stored as the address corresponding to the second count variable in the RAM of the memory 13B is the mixed value V of the filter error signal E _c and the synthesized value V of the synthesis block 8C _b . The ratio is updated to 1: 1 by [O]. It is M [I _b ] = E _c + V [O]. The update storage device M [Ib] is maintained until the next update value of M [I _b ] which is after the NL update cycle. As a result, the NL memory values from M [O] to M [NL-1] are obtained, and after the task of the update block 8C _d to update the NL memory values sequentially and periodically, the operation of the microprocessor 13A is in error. Return to the mission of block 8A.

Embodiments of the invention by the combination of FIG. 1, FIG. 2 and FIG. 8 also have the following benefits;

(1) The disturbance and disturbance of this embodiment is further improved than the embodiment by the combination of FIG. 1, FIG. 2 and FIG. This is because the output block 8B includes proportional integral filter means.

(2) The task of the microprocessor 13A in the detection period is reduced, because the task of the memory block 8C is a composite block 8C _b , a filtering error block 8C _c , which has a large estimated value by use of a voluntary square. ) And the update block 8C _d . This makes the estimation delay of the microprocessor 13A small and a normal microprocessor without a hardware squarer can be used as the microprocessor 13A in this embodiment.

(3) Improvement of the composite block 8C _b makes the control system of this embodiment stable. In particular, the use of the new or newest composite in the output block 8B compensates for the time delay of the filtering error block 8C _c .

In each embodiment of the present invention, it is very advantageous to improve the disturbance resistance to perform the task of the memory block when the microprocessor 13A waits after completing the task of the error block and the output block. This is because the calculation time delay for obtaining the new value of the control signal, such as the new value of the detection signal, is minimized. Estimation time delay is a necessary factor that represents the overall control gain, and smaller estimate time delay results in a greater overall control gain. In particular, minimizing the estimation time delay is very important for the composite block to prepare more than one composite value for future use. Also, it can be seen that minimizing the estimation time for the task of the memory block is not so important. Because the microprocessor 13A executes the task of the memory block once at the rest of the detection period Q except for the Q times the estimated time delay for the task of the error block and the output block. The memory block is divided into two or more tasks, and when the microprocessor 13A waits after the task of the error block and the output block, it performs one or more sub-missions per detection cycle.

Although specific embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to such specific embodiments, and the present invention is clarified by the appended claims by those skilled in the art to which the present invention pertains. It is understood that changes and modifications may be made without departing from the scope or spirit of the invention. For example, the error signal may be a combined signal of the speed error and the phase error of the motor by controlling the phase as well as the speed of the motor when the control system for the motor has a phase detector such as a speed detector.

Claims (36)

Detection means for generating a detection signal corresponding to a control variable of the control system, error means for generating an error signal corresponding to the detection signal of the detection means periodically at an interval equal to the detection time, an error signal of the error means, Memory that sequentially and periodically updates a plurality of memory values at an update time interval corresponding to Q times the detection period by a value corresponding to the first mixed value obtained by mixing one or more of the memory values updated at intervals of the update period L. Generates a control signal corresponding to the second stage (where Q and L are integers of 2 or more), and the second mixed value obtained by mixing at least one of the error signal of the error means and the memory value of the memory means, and converting the signal into the control system. And an output means for supplying to and controlling the control variables of the control system. 2. The memory device according to claim 1, wherein the memory means periodically calculates one or more linear combinations of a series of memory values N (N is an integer of two or more) updated at intervals of an update cycle L by coefficients having the same signal. Controller. 2. The control apparatus according to claim 1, wherein said memory means comprises filtering error means having a low band filter characteristic for generating a filtered error signal. 4. The control apparatus according to claim 3, wherein the filtering error means generates a filtered error signal by linearly combining a plurality of error signal values of the error means according to the obtained timing. The control apparatus according to claim 1, wherein the error means includes a proportional integral filter means such that the error signal has an integral part as well as a proportional part of the detection signal. 2. The control apparatus according to claim 1, wherein the output means includes a proportional filter means so that the control signal has not only a proportional part but also an integral part of the second mixed value. 2. The apparatus of claim 1, wherein the memory means comprises: filtering error means having a low band filter characteristic for generating a filtered error signal, updating means for periodically updating the memory value sequentially according to a value corresponding to the first mixed value; And synthesizing means for generating at least one composite value corresponding to at least one linear combination of update values of the update means updated at intervals of update period L, wherein the first mixed value of the update means is filtered out of the filtering error means. And a combination of an error signal and a combined value of said combining means. 8. The control apparatus according to claim 7, wherein said synthesizing means periodically calculates one or more linear combinations of a series of memory values N at intervals of an update period L by coefficients having the same signal. 8. The control apparatus according to claim 7, wherein said control device comprises a microprocessor for performing the tasks of said error means, said output means, said synthesis error means, said update means, and said synthesis means, said microprocessor being within a detection period Q. And performing the tasks of the synthesizing error means, the updating means and the synthesizing means once every Q times of the tasks of the error means and the output means. 10. The method of claim 9, wherein a series of tasks of the synthesizing error means, the updating means, and the synthesizing means are divided into two or more sub-missions, and the microprocessor is assigned during the waiting time after completion of the error means and the output means. A control apparatus, characterized in that for executing one of the none at every detection cycle. 8. The control apparatus according to claim 7, wherein said updating means periodically updates one of the memory values by linearly combining a series of first mixed values sequentially in accordance with the obtained timing. 8. The control apparatus according to claim 7, wherein the second mixed value of the output means is obtained by mixing at least one of an error signal of the error means and a synthesized value of the combining means. 8. The control apparatus according to claim 7, wherein said synthesizing means calculates each synthesis value by linearly combining one or more linear combinations of memory values according to the obtained timing. 8. The control apparatus according to claim 7, wherein the filtering error means generates a filtered error signal by linearly combining a plurality of error signal values of the error means in accordance with the obtained timing. Detection means for generating a detection signal corresponding to a control variable of the control system, error means for generating an error signal corresponding to the detection signal of the detection means periodically at intervals of the detection period, and the error sequentially according to the obtained timing Detection using a filtering error means for generating a filtered error signal by linearly combining a plurality of error signal values of the means, and a first mixed value corresponding value obtained by mixing the filtered error signal of the filtering error means and a composite value of the combining means. And updating means for sequentially updating a plurality of memory values in an update period corresponding to Q (Q is an integer of 2 or more) of the period, wherein said updating means generates one or more composite values, and each synthesized value of the updating means Corresponding to one or more linear combinations of memory values, wherein the one or more memory values are in cycles of update cycle L (L is an integer of 2 or more). Control signal of the control system by generating a control signal corresponding to the second mixed value obtained by mixing at least one of the error signal of the error means and the combined value of the combining means and supplying the control signal to the control signal. Control device characterized in that it comprises an output means to. A motor to be controlled, drive means for supplying power corresponding to a control signal to the motor, sensor means for generating a sensor signal at a frequency proportional to the speed of the motor, and a proportional to the period of the sensor signal Velocity detection means for obtaining a detection signal having a digital number corresponding to the speed of the motor in a detection period and generating an error signal corresponding to the detection signal of the speed detection means, wherein the error signal has not only a proportional part but also an integral part. An error means having a proportional integral filter means, and a filtering error means for generating a filtered error signal having a low band filter characteristic, so that at least one of the filtered error signal and at least one memory value as old as the update period L is mixed. Memo for updating a plurality of memory values in an update period corresponding to Q times the detection period by the value corresponding to the first mixed value An output for generating a control signal corresponding to the means (Q and L are integers of 2 or more) and a second mixed value obtained by mixing at least one of the error signal of the error means and the memory value of the memory means and supplying it to the driving means. A control device comprising a means. The control apparatus according to claim 16, wherein the update period L of the memory means is an integer multiple of one rotation period of the motor. 17. The control apparatus according to claim 16, wherein the filtering means generates a filtered signal by linearly combining a plurality of error signal values of the error means in accordance with the obtained timing. 17. The apparatus according to claim 16, wherein the memory means comprises a filtering error means for generating a filtered error signal by linearly combining a plurality of error signal values of the error means in accordance with the obtained timing, and a value corresponding to the first mixed value. Update means for periodically updating the memory values sequentially, and synthesizing means for generating one or more composite values corresponding to one or more linear combinations of the memory values of the update means updated in the cycle of update cycle L, the first means of the updating means And a mixed value obtained by mixing the filtered error signal of the filtering error means and the synthesized value of the combining means. 20. The control apparatus according to claim 19, wherein the synthesizing means periodically calculates one or more linear combinations of the memory values N updated in the period of the update cycle L by coefficients having the same signal. 20. The apparatus of claim 19, wherein the control device comprises a microprocessor for performing the tasks of the error means, the output means, the synthesis error means, the update means and the synthesis means, the microprocessor being within a detection period Q. And performing the tasks of the synthesizing error means, the updating means and the synthesizing means once every Q times of the tasks of the error means and the output means. 22. The method of claim 21, wherein the task of the synthesizing error means, the updating means and the synthesizing means is divided into two or more sub-tasks, and the microprocessor detects the waiting time after completing the tasks of the error means and the output means. Control device characterized in that to perform one of the sub-missions per cycle. 20. The control apparatus according to claim 19, wherein said updating means periodically updates one of the memory values by linear combination of the first mixed values sequentially in accordance with the timing. 20. The control apparatus according to claim 19, wherein the second mixed value of said output means is obtained by mixing at least one of an error signal of said error means and a combined value of said combining means. 20. The control apparatus according to claim 19, wherein said synthesizing means calculates each synthesis value by linearly combining one or more linear combinations of memory values according to the obtained timing. A motor to be controlled, drive means for supplying power corresponding to a control signal to the motor, sensor means for generating a sensor signal having a frequency proportional to the speed of the motor, and proportional to a period of the sensor signal Speed detection means for obtaining a detection signal of a digital number corresponding to the speed of the motor at a detection period, error means for generating an error signal corresponding to the detection signal of the speed detection means, and for generating a filtered error signal. And a filter means having a low band filter characteristic. The filter means having a low band filter characteristic, wherein the filtered error signal is at least Q times the detection period by a value corresponding to the first mixture value obtained by mixing at least one memory value that is at least as old as the update cycle L. Memory means (Q and L are integers of 2 or more, respectively) for sequentially and periodically updating a plurality of memory values at a corresponding update cycle period; Generating a control signal corresponding to the second mixed value obtained by mixing the signal and at least one memory value of the memory means, and the proportional part filter means is provided so that the control signal has not only a proportional part but also an integral part of the second mixed value, A control device comprising an output means for supplying a control signal to the drive means. 27. The control apparatus according to claim 26, wherein the update cycle period L in said memory means is an integer multiple of one rotation period of said motor. 27. The control apparatus according to claim 26, wherein the filter means generates a filtered error signal by linearly combining a plurality of error signal values of the error means in accordance with the obtained timing. 27. The apparatus according to claim 26, wherein the memory means comprises: filtering error means for linearly combining a plurality of error signal values of the error means in accordance with the obtained timing to generate a filtered error signal, and a value corresponding to the first mixed value; Update means for sequentially and periodically updating the memory value by means of; and synthesizing means for generating at least one synthesized value corresponding to a linear combination of one or more update values of the update means updated in a cycle of update cycle L; And the first mixed value is obtained by mixing the filtered error signal of the filtering error means and the synthesized value of the combining means. 30. The control apparatus according to claim 29, wherein said synthesizing means periodically calculates at least one of linear combinations of the memory N updated in the period of the update cycle L by coefficients having the same signal. 30. The apparatus of claim 29, wherein the control device comprises a microprocessor for performing the tasks of the error means, the output means, the synthesis error means, the update means and the synthesis means, wherein the microprocessor comprises the synthesis error means, And the task of said updating means and said synthesizing means is executed once every Q times the task of said error means and said output means within a detection period Q. The task of claim 31, wherein the task of the synthesizing error means, the updating means, and the synthesizing means is divided into two or more sub-tasks, and the microprocessor is configured to detect the error period and the output means every detection period during the waiting time after the task ends. A control device, characterized in that for carrying out one of the submissions. 30. The control apparatus according to claim 29, wherein said updating means periodically updates one of the memory values by linear combination of the first mixed values sequentially in accordance with the obtained timing. 30. The control apparatus according to claim 29, wherein the second mixed value of the output means is obtained by mixing at least one of the error means error signal and the combined value of the combining means. 35. The control apparatus according to claim 34, wherein the combined value of said combining means used in said output means is newer than the combined value of said combining means used in said updating means. 30. The control apparatus according to claim 29, wherein said synthesizing means calculates each synthesis value by linearly combining one or more linear combinations of memory values according to the obtained timing.

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