JPH0512102A - Memory controller - Google Patents

Abstract

PURPOSE:To install a memory board having arbitrary capacity at an arbitrary connecting position regardless of the connecting position and storage capacity of the memory board without manual setting and to speed up the simultaneous writing of an initial value and refreshing. CONSTITUTION:For respective memory boards 7 to 9, a memory controller 6 sets the effective address area of the respective memory boards with board enabling signals 12 to 14. With the requests 10 and 11 of a central processing unit 4 and a refreshing controller 5, a memory controller 6 simultaneously supplies the board enabling signals 12 to 14 to plural memory boards.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a memory control device,
In particular, it relates to a control device for a plurality of memory boards on a common bus of an information processing device.

[0002]

2. Description of the Related Art Conventionally, in an information processing apparatus having a plurality of memory boards on a common bus, it is necessary to install the memory boards at designated positions or set valid addresses on the memory boards. The method was used, and it was a method that does not allow access to multiple memory boards at the same time.

[0003]

According to the above-mentioned conventional method of sequentially installing the memory boards at the installation locations that are effective in the predetermined address area or setting the effective address area on the memory board with the switch, There is a problem in that memory boards with different capacities must be installed at predetermined positions, or switches must be switched when the memory board configuration is changed. Further, there is a problem that different memory boards cannot be accessed or refreshed at the same time for writing initial values.

[0004]

A memory control device of the present invention is connected to a common first bus for transferring information and a common second bus for specifying an area for storing information, and has a board enable signal. There is provided means for individually creating a board enable signal for a plurality of memory units (memory boards) each having an input terminal by the contents of the second bus and an input signal from the outside.

Preferably, the memory control device of the present invention is
Independently provided with means for generating board enable signals for permitting transmission and reception of signals between each memory board and the common bus, and further providing control means for simultaneously generating a plurality of board enable signals. Allows access to multiple memory boards at the same time.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings with reference to the drawings.

Referring to FIG. 1, a system using a memory control device 6 according to an embodiment of the present invention has a common bus line (address bus) for a signal (address signal) designating an area for storing information. 1, a common bus line (data bus) 2 for transferring information, a common bus line (control bus) 3 for transferring control signals, and these three buses 1 to 1
3 has a central processing unit 4 and storage units (memory boards) 7, 8 and 9, respectively, and a refresh control unit 5 connected to the address bus 1 and the control bus 3. The memory controller 6 is connected to the address bus 1, the data bus 2 and the control bus 3 by connecting buses 61, 62 and 63, respectively.
And the board enable signals 12, 13 and 14 are supplied to the memory boards 7, 8 and 9, respectively.

The central processing unit 4 uses the memory control unit 6 to enable one of its board enable signals 12, 13, 14 and the memory board (1 of 7-9) supplied with a valid board enable signal. Then, the presence / absence of a memory board and the storage capacity are sequentially checked to determine the address area where the board enable signals 12 to 14 are valid in the memory controller 6. The central processing unit 4 also sends a multi-board enable signal 10 to the memory controller 6 to enable a plurality of board enable signals (two or more of 12-14). The refresh controller 5 also sends a multi-board enable signal 11 to the memory controller 6 to enable a plurality of memory boards (two or more of 7-9).

Referring to FIG. 2, in the memory control device 6, the latch control signals 22, 23, 24 generated by the timing control unit 20 according to the conditions of the signals from the address bus 61 and the control bus 63 respectively cause the data bus 62 to transmit data. The signals are stored in the latches 25, 26 and 27, respectively. Latch outputs 28, 29, 3 of these latches
0 and the signal from the address bus 61 are compared by comparators 31 and 3
2 and 33 are compared, and comparison outputs 34, 35 and 36 are output respectively.

According to the multi-board enable signal 10 from the central processing unit 4 and the multi-board enable signal 11 from the refresh control unit 5, the multi-board enable control section 21 receives the multi-board enable control signal 37,
38, 39 are generated. These multi-board enable control signals 37, 38, 39 and comparison outputs 34, 35, 3
6, gates 40, 41 and 42 generate board enable signals 12, 13 and 14, respectively.

Thus, by enabling the board enable signals 12, 13, and 14 corresponding to the target memory board according to the address areas to be stored in the latches 25, 26, and 27, it is possible to allocate an arbitrary storage area. .

The multi-board enable signal 10 from the central processing unit causes a plurality of board enable signals 12,
It is possible to enable 13 and 14 and write to a plurality of memory boards 7, 8 and 9 at a time. Further, a plurality of board enable signals 12, 13, 14 can be made effective by a multi-board enable signal 11 from the refresh control device, and a plurality of memory boards 7, 8, 9 can be refreshed at one time.

[0013]

As described above, according to the present invention, the memory control device sets the effective address area of each memory board by the board enable signal for each memory board, so that the connection position and the storage capacity of the memory board are set. There is an effect that a memory board having an arbitrary capacity can be installed at an arbitrary connection position without manual setting regardless of the above.

Further, by enabling the memory controller to simultaneously enable a plurality of memory boards in response to a multi-board enable request from the central processing unit and the refresh controller, it is possible to write initial values and speed up refreshing. .

[Brief description of drawings]

FIG. 1 is a block diagram of a system using a memory control device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a memory control device according to an embodiment of the present invention.

[Explanation of symbols]

1 Address Bus 2 Data Bus 3 Control Bus 4 Central Processing Unit 5 Refresh Control Unit 6 Memory Control Unit 7, 8, 9 Memory Board 10 Multi-Board Enable Signal (Central Processing Unit Side) 11 Multi-Board Enable Signal (Refresh Control Unit Side) 12, 13, 14 Board enable signal 20 Timing control unit 21 Multi-board enable control unit 22, 23, 24 Latch control signal 25, 26, 27 Latch 28, 29, 30 Latch output 31, 32, 33 Comparator 34, 35, 36 Comparison output 37, 38, 39 Multi-board enable control output 61 Connection to address bus 62 Connection to data bus 63 Connection to control bus

Claims (2)

[Claims] 1. A plurality of memory boards connected to a common first bus for transferring information and a common second bus for specifying an area for storing information, each having a board enable signal input terminal. And a means for generating a board enable signal according to the contents of the second bus and an input signal from the outside. 2. A means for generating a board enable signal for permitting transmission / reception of a signal between each memory board and a common bus is independently provided by the number of installed memory boards, and a plurality of the board enable signals are simultaneously generated. A memory control device further comprising control means.